Cirrus Logic CS61600-IP1 Datasheet
Semiconductor Corporation
PCM Jitter Attenuator
CS61600
Features
Unique Clock-Tracking Circuitry Filters
••
50 Hz or Higher Frequency Jitter for
T1 and PCM-30 Applications
Minimal External Components Required
••
14 Pin DIP
••
Single 5 Volt Supply
••
3 Micron CMOS for High Reliability
••
and Low Power Dissipation: 50 mW
Typical at 25 °C
FIFORST OVR RESET
General Description
The CS61600 from Crystal Semiconductor accepts T1
(1.544 Mb/s) or CCITT standard (2.048 Mb/s) data and
clock inputs, and tolerates at least 7 (and up to 14) unit
intervals, peak-to-peak, of jitter. Before outputting data
and clock, jitter is attenuated using an internal clocktracking variable oscillator and a 16 bit FIFO elastic
store.
The jitter attenuation function can be determined by
appropriate specification of the external crystal.
The CS61600 is transparent to data format, and is intended for application in carrier systems, switching
systems, Local Area Network gateways and multiplexers.
ORDERING INFORMATION
CS61600-IP1 - 14 Pin Plastic DIP; T1 and 2.048 MHz
DIN
CLKIN
13
231
FIFO CONTROL
8
VARIABLE OSCILLATOR
16-BIT FIFO
HALF FULL
DETECT
4
XTALIN
5
XTALOUT
÷
4
11
OSCOUT
9
DOUT
10
CLKOUT
6
ARE
12
ARC
14
V+
7
GND
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445-7222 FAX: (512) 445-7581
Copyright Crystal Semicondutor Corporation 1994
(All Rights Reserved)
APR ’90
DS9F3
1
CS61600
ABSOLUTE MAXIMUM RATINGS
Parameter Symbol Min Max Units
DC Supply (V+)-GND -0.3 7.0 V
Input Voltage V
Input Current, Any Pin (Note 1) I
Ambient Operating Temperature T
Storage Temperature T
in
in
A
stg
Note: 1. Transient currents of up to 100 mA will not cause SCR latch-up.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
GND - 0.3 (V+) + 0.3 V
-10 10 mA
-40 85 °C
-65 150 °C
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol Min Typ Max Units
DC Supply (V+)-GND 4.5 5.0 5.5 V
Ambient Operating Temperature T
DIGITAL CHARACTERISTICS (T
= -40° to 85° C; V+ = 5V ±10%; GND = 0V)
A
Parameter Symbol Min Typ Max Units
High-Level Input Voltage V
Low-Level Input Voltage V
High-Level Output Voltage (Notes 2 and 3) V
Low-Level Output Voltage (Notes 2 and 4) V
Input Leakage Current I
Notes: 2. Outputs will drive CMOS logic levels into a CMOS load.
3. I
= -40 µA
out
= 1.6 mA
4. I
out
A
IH
IL
OH
OL
in
-402585°C
2.0 - - V
--0.8V
2.4 - - V
--0.4V
--
±10.0 µA
Specifications subject to change without notice.
2 DS9F3
CS61600
DIGITAL CHARACTERISTICS (T
= -40° to 85° C; V+ = 5V ±10%; GND = 0V)
A
Parameter Symbol Min Typ Max Units
Power Dissipation P
D
-5085mW
Input Jitter Tolerance 7 - 14* U.I.
* Depends on accuracy of cr ystal with respect to CLK IN frequency. See
SWITCHING CHARACTERISTICS (T
= -40° to 85° C; V+ = 5V ±10%; GND = 0V;
A
Applications
section.
Inputs: Logic 0 = 0V, Logic 1 = V+)
Parameter Symbol Min Typ Max Units
Crystal Frequency T1
CCITT (Note 5)
CLKIN Frequency T1
CCITT (Note 6)
CLKOUT Frequency T1
CCITT (Note 6)
Clock Pulse Width T1
CCITT
(Note 7)
Acceptable CLKIN range (Note 8) -
f
t
pwh
t
t
pwh
t
f
c
f
in
out
pwl
pwl
-
-
-
-
-
-
-
-
-
-
6.176000
8.192000
1.544
2.048
1.544
2.048
324
324
244
244
±130
-
MHz
-
-
MHz
-
-
MHz
-
-
ns
-
-
ns
-
- ppm
Duty Cycle (Note 9) - 50 - %
Rise Time, All Digital Outputs (Note 10) t
Fall Time, All Digital Outputs (Note 10) t
DIN to CLKIN Falling Setup Time t
CLKIN Falling to DIN Hold Time t
CLKOUT Falling to DOUT Propogation Delay t
r
f
su
h
phl
- 36 100 ns
- 17 100 ns
30 - - ns
50 - - ns
- - 200 ns
Note: 5. Crystal should have sufficient pull range when in the oscillator circuit, to meet the system’s frequency
tolerance requirement over the operating temperature range. See
Applications
section for more
information on crystals.
6. Although CLKIN and CLKOUT will vary in instantaneous frequency (jitter) over time, CLKOUT
will have the same average frequency as CLK IN.
7. The sum of the pulse widths must always meet the frequency specifications.
8. Crystal must have at least ±130ppm pull range over operating temperature range.
9. Duty cycle is (t
10. At C
= 50pF.
L
PWH
/ (t
PWH
+ t
)) x 100%.
PWL
DS9F3 3
CS61600
Any Digital Output
Figure 1. Signal Rise and Fall Characteristics
CLKIN, CLKOUT
t
r
90% 90%
10% 10%
t
pwh
Figure 2. Clock Signal Quality
t
pwl
t
f
CLKIN
t
su
t
h
DIN
Figure 3. Switching Characteristics
4 DS9F3
CLKOUT
DOUT
t
phl
PEAK-TO-PEAK
(SINUSOIDAL)
JITTER
AMPLITUDE
IN UNIT
INTERVALS
10.0
7.0
5.0
1.5
1.0
0.2
0.1
CS61600 PERFORMANCE
AT&T
43802
SPECIFICATION
CS61600
CCITT
G.823
SPECIFICATION
-10
-20
-30
0
10.0
JITTER
GAIN
(dB)
500 8.0k
100.0 1.0k 10.0k
JITTER FREQUENCY (Hz)
Figure 4. Input Jitter Tolerance
BELL SYSTEM
PUB 43802
20 dB/
decade
CS61600
PERFORMANCE
SPECIFICATION
18k2.4k20
Input of five
unit intervals
of jitter at all
frequencies.
-40
10 100 1k 10k
JITTER FREQUENCY
(Hz)
Figure 5. Jitter Attenuat ion Char acteristic
DS9F3 5