Cirrus Logic CS61584A User Manual

Copyright  Cirrus Logic, Inc. 2005

(All Rights Reserved)

http://www.cirrus.com

CS61584A

Dual T1/E1 Line Interface

SEP ‘05

DS261F1

Dual T1/E1 Line Interface

CS61584A

Features

l Dual T1/E1 Line Interface
l 3.3 Volt and 5 Volt Versions
l Crystal-less Jitter Attenuator Meets

European CTR 12 and ETSI ETS 300 011
Specifications

l Matched Impedance Transmit Drivers
l Transmitter Tri-state Capability
l Common Transmit and

ReceiveTransformers for all Modes

l Serial and Parallel Host Mo de Operation
l User-customizable Pulse Shapes
l Supports JTAG Boundary Scan
l Compliant with:

– ITU-T Recommendations: G.703, G.704,

G.706, G.732, G.775 and I.431

– American National Standards (ANSI): T1.102,

T1.105, T1.403, T1.408, and T1.231

– FCC Rules and Regulations: Part 68 and Part

15

– AT&T Publication 62411
– ETSI ETS 300 011, 300 233, CTR 12, TBR 13

l TR-NET-00499

Description

The CS61584A is a dual li ne interface for T1/E 1 appli­cations, designed for high-volume cards where low
power and high density are requ ired. The device is op­timized for flexible microprocessor control through a
serial or paralle l Host mode interface. Ha rdware mode
operation is also available.

Matched impedance drivers reduce power consumption
and provide substantial transmitter return loss. The
transmitter pulse shapes are customizable to allow non­standard line loads . Crystalless jitter a ttenuation com­plies with most stringent standards. Support of JTAG
boundary scan enhances system testability and
reliability.

ORDERING INFORMATION

See

page 53.

CS61584A-IQ3:3.3V, 64-pin TQFP, -40 to +85° C
CS61584A-IL5:5.0V, 68-pin PLCC, -40 to +85° C
CS61584A-IQ5:5.0V, 64-pin TQFP, -40 to +85° C

Preliminary Product Information

P.O. Box 17847, Austin, Texas 78760
[phone] FAX: [phone]
http://www.cirrus.com

Serial Port

Parallel Port

Hardware Mode

TCLK1

(TDATA1) TPOS1

(AIS1) TNEG1

RCLK1

(RDATA1) RPOS1

(BPV1) RNEG1

TCLK2

(TDATA2) TPOS2

(AIS2) TNEG2

RCLK2

(RDATA2) RPOS2

(BPV2) RNEG2

IPOL

IPOL (DTACK)

CLKE

JTAG

INT

SCLK

SDO

SDI

CS

4

P/S
P/S

ATTEN0

E
N
C
O
D
E
R

D
E
C
O
D
E
R

E
N
C
O
D
E
R

D
E
C
O
D
E
R

INT

RD(DS)

RLOOP2

JITTER

JITTER

AD0

LLOOP

CS

RLOOP1

ATTEN1

R
E
M
O
T
E

L

ATTENUATOR

O
O
P
B
A
C
K

R
E
M
O
T
E

L

ATTENUATOR

O
O
P
B
A
C
K

CLOCK GENERATOR

REFCLK XTALOUT 1XCLK TV+ TGND RV+ RGND DV+ DGND

SPOL

AD1

AD2

TAOS1

TAOS2

CONTROL

L
O
C
A

TAOS

L
L

O
O
P

LOS &

B
A

AIS

C

DETECT

K
1

L
O
C
A

TAOS

L
L

O
O
P

LOS &

B
A

AIS

C

DETECT

K
1

2 2 2 2 3

This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.

Copyright  Cirrus Logic, Inc. 2000

AD3

AD4

CON02

PULSE

SHAPING

CIRCUITRY

CLOCK &

DATA

RECOVERY

PULSE

SHAPING

CIRCUITRY

CLOCK &

DATA

RECOVERY

AD5

CON11

AV+ AGND

CON12

CON01

(All Rights Reserved)

AD6

DRIVER

DRIVER

CON21

RECEIVER

RECEIVER

BGREF

AD7

PD1
SAD4
ZTX1

ALE(AS)

CON22

WR(R/W)

CON31

CONTROL

PD2
SAD5
ZTX2

LOS1
SAD6
LOS1

BTS

CON32

L
O
C
A
L

L
O
O
P
B
A
C
K
2

L
O
C
A
L

L
O
O
P
B
A
C
K
2

LOS2
SAD7
LOS2

TTIP1

TRING1

RTIP1

RRING1

TTIP2

TRING2

RTIP2

RRING2

RESET
MODE

Hardware Mode
Parallel Port
Serial Port

JAN ‘01

DS261PP5

1

TABLE OF CONTENTS

1. CHARACTERISTICS AND SPECIFICATIONS .................................. ....... ...... ....... ...... ....... ..... 5

ABSOLUTE MAXIMUM RATINGS ...........................................................................................5

RECOMMENDED OPERATING CONDITIONS.......................................................................5

ANALOG CHARACTERISTICS................................................................................................ 6

ANALOG CHARACTERISTICS................................................................................................ 7

DIGITAL CHARACTERISTICS................................................................................................. 8

SWITCHING CHARACTERISTICS . ...... ....... ...... ......................................................................8

SWITCHING CHARACTERISTICS - SERIAL PORT .............................................................10

SWITCHING CHARACTERISTICS - PARALLEL PORT........................................................11

SWITCHING CHARACTERISTICS - JTAG............................................................................ 14

2. OVERVIEW ............................................................................................................................. 15

2.1 AT&T 62411 Customer Premises Application .................................................................. 16

2.2 Asynchronous Multiplexer Application ............................................................................. 16

2.3 Synchronous Application ................................................................................................. 16

3. TRANSMITTER .......................................................................................................................16

4. RECEIVER .............................................................................................................................. 18

5. JITTER ATTENUATOR ................... ...... ....... ...... ....... ...... .......................................................19

6. REFERENCE CLOCK ............................................................................................................20

7. POWER-UP RESET ................................................................................................................20

8. LINE CONTROL AND MONITORING .................................................................................... 20

8.1 Line Code Encoder/Decoder ............................................................................................20

8.2 Alarm Indication Signal ....................................................................................................20

8.3 Bipolar Violation Detection ...............................................................................................21

8.4 Excessive Zeros Detection ..............................................................................................21

8.5 Loss of Signal .................................................................................................................. 21

8.6 Transmit All Ones ............................................................................................................21

8.7 Receive All Ones ............................................................................................................. 21

8.8 Local Loopback ................................................................................................................22

8.9 Remote Loopback ............................................................................................................22

8.10 Driver Tristate ................................................................................................................ 22

8.11 Power Down ................................................................................................................... 22

8.12 Reset Pin ....................................................................................................................... 23

9. HOST MODE ...........................................................................................................................23

9.1 Register Set ..................................................................................................................... 23

9.1.1 Status Registers ..................................................................................................23

DS261PP5

CS61584A

CS61584A

Contacting Cirrus Logic Support

For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:

http://www.cirrus.com/corporate/contacts/sales.cfm

Preliminary product inf o rmation describes products whi c h are i n production, but for whi ch f ul l char act erization data is not yet avai l ab le . Ad vance p roduct infor-
mation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information
contained in this document i s accurat e and reli able. However , t he infor mation is subje ct to chang e without noti ce and is provi d ed “AS IS” without warrant y of

any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being
relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warran t y , pa tent infringement, and limitation of liability. N o responsibility is ass umed by Cirrus Logic, In c . for the use of this information, including
use of this inf orma t i on as the basis for manufacture or sale o f any items, nor for i nf ringements of pat en t s or other rights o f thir d parti es. This document i s the
property of Cirrus Logic, Inc. a nd by furni shing th is i nformati on, Cir rus L ogic, In c. grant s no l icense, express or i mpli ed under any patent s, mask work righ ts,
copyrights, trademarks, trad e secrets o r ot her i ntellect ual pro pert y right s of Cirrus L ogic, I nc. Ci rrus L ogic, In c., cop yright owner of the in forma tion co ntaine d
herein, gives consent for copies to be made of the information only for use within your organization with respect to Cirrus Logic integrated circuits or other parts
of Cirrus Logic, Inc. The same consent is gi ven for simi lar inf ormat ion con tai ned on a ny Cirru s Logic we bsite or disk. T his consent does not extend to othe r
copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. The names of products of Cirrus Logic,
Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some
jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com

2 DS261PP5

2 DS261F1

.

DS261PP5

CS61584A

CS61584A

9.1.2 Mask Registers ................................................................................................... 25

9.1.3 Control A Registers ............................................................................................. 26

9.1.4 Control B Registers ............................................................................................. 27

9.1.5 Arbitrary Waveform Registers ............................................................................. 27

9.2 Serial Port Operation ....................................................................................................... 30

9.3 Parallel Port Operation ....................................................................................................31

10. JTAG BOUNDARY SCAN .................................................................................................... 31

10.1 JTAG Data Registers (DR) ............................................................................................ 32

10.2 JTAG Instructions and Instruction Register (IR) ............................................................ 33

10.3 JTAG TAP Controller ..................................................................................................... 33

10.4 Test-Logic-Reset State .................................................................................................. 33

10.5 Run-Test/Idle State ........................................................................................................ 34

10.6 Select-DR-Scan State ................................................................................................... 34

10.7 Capture-DR State ..........................................................................................................34

10.8 Shift-DR State ................................................................................................................ 34

10.9 Exit1-DR State ............................................................................................................... 34

10.10 Pause-DR State ...........................................................................................................35

10.11 Exit2-DR State ............................................................................................................. 35

10.12 Update-DR State ......................................................................................................... 35

10.13 Select-IR-Scan State ................................................................................................... 35

10.14 Capture-IR State .......................................................................................................... 35

10.15 Shift-IR State ............................................................................................................... 35

10.16 Exit1-IR State .............................................................................................................. 36

10.17 Pause-IR State ............................................................................................................ 36

10.18 Exit2-IR State .............................................................................................................. 36

10.19 Update-IR State ........................................................................................................... 36

10.20 JTAG Application Examples ........................................................................................ 36

11. PIN DESCRIPTIONS ............................................................................................................ 39

12. PACKAGE DIMENSIONS .................................................................................................... 46

13. APPLICATIONS ................................................................................................................... 48

13.1 Line Interface ................................................................................................................. 48

13.2 Power Supply ................................................................................................................ 50

13.3 Quartz Crystal Specifications ........................................................................................ 50

13.4 Crystal Oscillator Specifications .................................................................................... 50

13.5 Transformers ................................................................................................................. 51

13.6 Designing for AT&T 62411 ............................................................................................ 51

13.7 Line Protection ............................................................................................................... 51

13.8 Loop Selection Equations .............................................................................................. 51

LIST OF TABLES

Table 1. Line Configuration Selections............................................................................................. 17

Table 3. Jitter Attenuation Control.................................................................................................... 19

Table 4. CS61584A Register Set..................................................................................................... 23

Table 5. Status Registers................................................................................................................. 24

Table 6. Mask Registers................................................................................................................... 25

Table 7. Control A Registers............................................................................................................ 26

Table 8. Control B Registers............................................................................................................ 27

Table 9. Arbitrary Waveform Registers............................................................................................ 28

Table 10. Boundary Scan Register .................................................................................................. 32

Table 11. Device Identifcation Register............................................................................................ 33

Table 12. ......................................................................................................................................... 33

DS261PP5 3

DS261F1 3

DS261PP5

Table 13. CS61584A External Components.....................................................................................48

Table 14. Quartz Crystal Specifications ...........................................................................................50

Table 15. Suggested Quartz Crystals...............................................................................................50

Table 16. Suggested Crystal Oscillators ..........................................................................................50

Table 17. Transformer Specifications...............................................................................................51

Table 18. Recommended Transformers........................................................................................... 52

LIST OF FIGURES

Figure 1. Signal Rise And Fall Characteristics ..............................................................................9

Figure 2. Recovered Clock and Data Switching Characteristics ...................................................9

Figure 3. Transmit Clock and Data Switching Characteristics ......................................................9

Figure 4. Serial Port Write Timing Diagram ................................................................................. 10

Figure 5. Serial Port Read Timing Diagram ................................................................................10

Figure 6. Parallel Port Timing - Motorola Mode . ...... ....................................................................12

Figure 7. Parallel Port Timing - Intel Read Mode ........................................................................12

Figure 8. Parallel Port Timing - Intel Write Mode ........... ...... ...... ....... ...... ....... .............................12

Figure 9. Parallel Port Timing - Motorola Mode to RAM . ...... ...... ....... .......................................... 1 3

Figure 10. Parallel Port Timing - Intel Read Mode from RAM or ROM ......................................... 13

Figure 11. Parallel Port Timing - Intel Write Mode to RAM .......... ....... ....................................... ... 13

Figure 12. JTAG Switching Characteristics ................................................................................... 14

Figure 13. Examples of CS61584A Applications ...........................................................................15

Figure 14. Typical Pulse Shape at DSX-1 Cross Connect ............................................................17

Figure 15. Mask of the Pulse at the 2048 kbps Interface ..............................................................17

Figure 16. Minimum Input Jitter Tolerance of Receiver (Clock Recovery Circuit and

jitter Attenuator) ............................................................................................................ 18

Figure 17. Typical Jitter Transfer Function .................................................................................... 19

Figure 18. Alarm Indication Event Relationships ...........................................................................24

Figure 19. Phase Definition of Arbitrary Waveforms .....................................................................29

Figure 20. Example of Summing of Waveforms ............................................................................ 29

Figure 21. Serial Read/Write Format (SPOL = 0) ..........................................................................30

Figure 22. Address Command byte ............................................................................................... 30

Figure 23. JTAG Circuitry Block Diagram ..................................................................................... 31

Figure 24. TAP Controller State Diagram ...................................................................................... 34

Figure 25. JTAG Instruction Register update ................................................................................37

Figure 26. JTAG Data Register update .........................................................................................38

Figure 27. Hardware Mode Configuration ..................................................................................... 48

Figure 28. Host Mode Serial Port Configuration ............................................................................49

Figure 29. Host Mode Parallel Port Configuration ......................................................................... 49

CS61584A

CS61584A

4 DS261PP5

4 DS261F1

DS261PP5

CS61584A

CS61584A

1. CHARACTERISTICS AND SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Min Max Unit

DC Supply (TV+1, TV+2, RV+1, RV+2, AV+, DV+) (Note 1) - 6.0 V
Input Voltage (Any Pin) V
Input Current (Any Pin) (Note 2) I
Ambient Operating Temperature T

Storage Temperature T

Notes: 1. Referenced to RGND1, RGND2, TGND1, TGND2, AGND, DGND at 0 V.

2. Transient currents of up to 100 mA will not cause SCR latch-up.

WARNING: Operation at or beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes.

in

in

A

stg

RECOMMENDED OPERATING CONDITIONS

Parameter Symbol Min Typ Max Unit

DC Supply (TV+1, TV+2, RV+1, RV+2, AV+, DV+) (Note 3)

3.3 V

5.0 V
Ambient Operating Temperature T
Power Consumption Per Channel (3.3 V) (Note 4)

T1 (Note 5)
T1 (Note 6)
E1, 75 Ω (Note 5)
E1, 120 Ω (Note 5)

Power Consumption Per Channel (5.0 V) (Note 4)

T1 (Note 5)
T1 (Note 6)
E1, 75 Ω (Note 5)
E1, 120 Ω (Note 5)

REFCLK Frequency T1 1XCLK = 1

T1 1XCLK = 0

REFCLK Frequency E1 1XCLK = 1

E1 1XCLK = 0

A

P

C

P

C

RGND - 0.3 (RV+) + 0.3 V

-10 10 mA

-40 85 °C

-65 150 °C

3.135

4.75

-40 25 85 °C

-

-

-

-

-

-

-

-

(1.544 -

100 ppm)

(12.352 -

100 ppm)

(2.048 -

100 ppm)

(16.384 -

100 ppm)

3.3

5.0

310
190
250
230

350
250
320
310

1.544

12.352

2.048

16.384

3.465

5.25

-

-

-

-

-

-

-

-

(1.544 +
100 ppm)
(12.352 +
100 ppm)

(2.048 +
100 ppm)
(16.384 +
100 ppm)

MHz
MHz

MHz
MHz

V

mW

mW

Notes: 3. TV+1, TV+2, AV+, DV+, RV+1, RV+2 should be connected together. TGND1, TGND2, RGND1, GND2,

DGND1, DGND2, DGND3 should be connected together.

4. Per channel power consumption while driving line load over operating temperature range. Includes
device and load. Digital input levels are within 10% of the supply rails and digital outputs are driving a
50 pF capacitive load.

5. Assumes 100% ones density and maximum line length at maximum supply voltage (3.465 V or 5.25 V).

6. Assumes 50% ones density and 300 ft. line length at typical supply voltage (3.3 V or 5.0 V).

Specifications are subject to change without notice

DS261PP5 5

DS261F1 5

DS261PP5

CS61584A

CS61584A

ANALOG CHARACTERISTICS (T

Parameter Symbol Min Typ Max Unit

= -40 to 85 °C; power supply pins within ±5% of nominal.)

A

Receiver

RTIP/RRING Differential Input Impedance - 20 - kΩ
Sensitivity Below DSX-1 (0 dB = 2.4 V) - -13.6 - dB
Loss of Signal Threshold - 0.3 - V
Data Decision Threshold T1, DSX-1 (Note 7)

(Note 8)

T1, FCC Part 68 and E1 (Note

9)

(Note 10)
Allowable Consecutive Zeros before LOS 160 175 190 bits
Receiver Input Jitter Tolerance (DSX-1, E1)

10 Hz and bel ow (N ot e 11)
2kHz
10 kHz - 100 kHz

Receiver Return Loss (Notes 12, 13, and 14)

51 kHz - 102 kHz
102 kHz - 2.048 MHz

2.048 MHz - 3.072 MHz

60
55
45
40

300

6.0

0.4

12
18
14

65
50

22
24
22

70

-

-

-

-

-

75
55
60

-

-

-

-

-

-

% of

Peak

UI

dB

Jitter Attenuator

Jitter Attenuator Corner Frequency

T1 (Notes 12 and 15)

E1
Attenuation at 10 kHz Jitter Frequency (Notes 12 and 15) - 60 - dB
Attenuator Input Jitter Tolerance (Note 12)

(Before Onset of FIFO Overflow or Underflow Protection)

1.25

-

28 43 - UI

4.0

1.25

-

-

Hz

pk-pk

Transmitter

Arbitrary Pulse Amplitude at Transformer Secondary

T1, DSX-1

T1, DS1

E1, 75 Ω

E1, 120 Ω

-

-

-

-

73
52
43
52

mV/LS

-

-

-

-

B

Notes: 7. For input amplitude of 1.2 V

8. For input amplitude of 0.5 V

9. For input amplitude of 1.07 V

10. For input amplitude of 4.14 V

11. Jitter tolerance increases at lower frequencies. Refer to the Receiver section.

12. Not production tested. Parameters guaranteed by design and characterization.

13. Typical performance using the line interface circuitry recommended in the Applications section.

14. Return loss = 20 log
= cable impedance.

z

0

15. Attenuation measured with sinusoidal input jitter equal to 3/4 of measured jitter tolerance. Circuit

attenuates jitter at 20 dB/decade above the corner frequency. Output jitter can increase significantly
when more than 28 UI's are input to the attenuator. The jitter attenuator -3 dB knee in T1 mode is
selectable for 4.0 Hz or 1.25 Hz. Refer to the Jitter Attenuator section.

6 DS261PP5

6 DS261F1

ABS((z1 + z0) / (z1 - z0)) where z1 = impedance of the transmitter or receiver, and

10

to 4.14 Vpk.

pk

to 1.2 Vpk, and 4.14 Vpk to 5.0 Vpk.

pk

to 4.14 Vpk.

pk

to 5.0 Vpk.

pk

DS261PP5

CS61584A

CS61584A

ANALOG CHARACTERISTICS (Continued)

Parameter Symbol Min Typ Max Unit

Transmitter (Continued)

AMI Output Pulse Amplitudes (Note 16)

E1, 75 Ω (Note 17)
E1, 120 Ω (Note 18)
T1, DSX-1 (Note 19)

Recommended Transmitter Output Load (3.3 V) (Note 16)

T1
E1, 75 Ω
E1, 120 Ω

Recommended Transmitter Output Load (5.0 V) (Note 16)

T1
E1, 75 Ω
E1, 120 Ω

Jitter Added During Remote Loopback

10 Hz - 8 kHz
8kHz - 40kHz
10 Hz - 40 kHz
Broad Band (Note 20)

Power in 2 kHz band about 772 kHz (Notes 12 and 13)
(DSX-1 only)

Power in 2 kHz band about 1.544 MHz (Note 12 and 13)
(referenced to power in 2 kHz band at 772 kHz, DSX-1 only)

Positive to Negative Pulse Imbalance (Notes 12 and 13)

T1, DSX-1
E1, amplitude at center fo pulse interval
E1, width at 50% of nominal amplitude

Transmitter Return Loss (Notes 12, 13, and 14)

51 kHz - 102 kHz
102 kHz - 2.048 MHz

2.048 MHz - 3.072 MHz

E1 Short Circuit Current 5.0 V

3.3 V
E1 and DSX-1 Output Pulse Rise/Fall Times (Note 22) - 50 - ns
E1 Pulse Width (at 50% of peak amplitude) - 244 - ns
E1 Pulse Amplitude for a space E1, 75 Ω

(Note 21)

E1, 120 Ω

2.14

2.7

2.4

-

-

-

-

-

-

-

-

-

-

12.6 15 17.9 dBm

-29 -38 - dB

-

-5

-5

8
14
10

-

-

-0.237

-0.3

2.37

3.0

3.0

24.8

18.6

30.0

76.6

57.4

90.6

0.020

0.015

0.015

0.045

0.2

-

-

25
18
12

-

70

-

-

2.6

3.3

3.6

-

-

-

-

-

-

-

-

-

-

0.5
5
5

-

-

-

50

-

0.237

0.3

mA
mA

V

Ω

Ω

UI

dB

%
%

dB

rms
rms

V
V

Notes: 16. Using a transformer that meets the specifications in the Applications section.

17. Measured across 75 Ω at the output of the transmit transformer for CON3/2/1/0 = 0/0/0/0.

18. Measured across 120 Ω at the output of the transmit transformer for CON3/2/1/0 = 0/0/0/1.

19. Measured at the DSX-1 Cross-Connect for line length settings CON3/2/1/0 = 0/0/1/0, 0/0/1/1, 0/1/0/0,
0/1/0/1, and 0/1/1/0 after the length of #22 ABAM cable specified in Table 1.

20. Input signal to RTIP/RRING is jitter free. Values will reduce slightly if jitter free clock is input to TCLK.

21. Transformer secondary shorted with 0.5 Ω resistor during the transmission of 100% ones.

22. At transformer secondary and measured from 10% to 90% of amplitude.

DS261PP5 7

DS261F1 7

DS261PP5

CS61584A

CS61584A

DIGITAL CHARACTERISTICS (T

= -40 to 85 °C; power supply pins within ±5% of nominal.)

A

Parameter Symbol Min Max Unit

High-Level Input Voltage (Note 23) V
Low-Level Input Voltage (Note 23) V
High-Level Output Voltage (I

Low-Level Output Voltage (I

= -40 µA) (Note 24) V

out

= 1.6 mA) (Note 24) V

out

IH

IL

OH

OL

(DV+) - 0.5 - V

-0.5V

(DV+) - 0.3 - V

-0.3V

Input Leakage Current (Digital pins except J-TMS and J-TDI) - ±10 µA

Notes: 23. Digital inputs are designed for CMOS logic levels.

24. Digital outputs are TTL compatible and drive CMOS levels into a CMOS load.

SWITCHING CHARACTERISTICS (T

= -40 to 85 °C; power supply pins within ±5% of nominal;

A

Inputs: Logic 0 = 0 V, Logic 1 = DV+.)

Parameter Symbol Min Typ Max Unit

T1 Clock/Data

TCLK Frequency (Note 25) f
TCLK Duty Cycle t
RCLK Duty Cycle (Note 26) t

pwh2/tpw2
pwh1/tpw1

Rise Time (All Digital Outputs) (Note 27) t
Fall Time (All Digital Outputs) (Note 27) t
RPOS/RNEG (RDATA) to RCLK Rising Setup Time t
RCLK Rising to RPOS/RNEG (RDATA) Hold Time t
TPOS/TNEG (TDATA) to TCLK Falling Setup Time t
TCLK Falling to TPOS/TNEG (TDATA) Hold Time t

tclk

r
f

su1

h1

su2

h2

-1.544-MHz
20 50 80 %
45 50 55 %

- - 65 ns

- - 65 ns

-274-ns

-274-ns
25 - - ns
25 - - ns

E1 Clock/Data

TCLK Frequency (Note 25) f
TCLK Duty Cycle t
RCLK Duty Cycle (Note 26) t

pwh2/tpw2
pwh1/tpw1

Rise Time (All Digital Outputs) (Note 27) t
Fall Time (All Digital Outputs) (Note 27) t
RPOS/RNEG (RDATA) to RCLK Rising Setup Time t
RCLK Rising to RPOS/RNEG (RDATA) Hold Time t
TPOS/TNEG (TDATA) to TCLK Falling Setup Time t
TCLK Falling to TPOS/TNEG (TDATA) Hold Time t

tclk

r
f

su1

h1

su2

h2

-2.048-MHz
20 50 80 %
45 50 55 %

- - 65 ns

- - 65 ns

-194-ns

-194-ns
25 - - ns
25 - - ns

Notes: 25. The maximum burst rate of a gapped TCLK input clock is 8.192 MHz. For the gapped clock to be

tolerated by the CS61584A, the jitter attenuator must be switched to the transmit path of the line
interface. The maximum gap size that can be tolerated on TCLK is 28 UIp-p.

26. RCLK duty cycle may be outside the specified limits when the jitter attenuator is in the transmit path
and when the jitter attenuator is employing the overflow/underflow protection mechanism.

27. At max load of 50 pF.

8 DS261PP5

8 DS261F1

DS261PP5

CS61584A

CS61584A

Any Digital Output

RCLK
(for CLKE = high)

RPOS
RNEG
RDATA
BPV

t

r

90% 90%

10% 10%

Figure 1. Signal Rise And Fall Characteristics

t

pw1

t

pwl1

t

su1

t

pwh1

t

h1

t

f

RCLK
(for CLKE = low)

Figure 2. Recovered Clock and Data Switching Characteristics

Figure 3. Transmit Clock and Data Switching Characteristics

TCLK

TPOS
TNEG
TDATA

t

pwh2

t

su2

t

pw2

t

h2

DS261PP5 9

DS261F1 9

DS261PP5

CS61584A

CS61584A

SWITCHING CHARACTERISTICS - SERIAL PORT (T

nominal ± 0.3 V; Inputs: Logic 0 = 0 V, Logic 1 = RV+)

Parameter Symbol Min Typ Max Unit

SDI to SCLK Setup Time t
SCLK to SDI Hold Time t
SCLK Low Time t
SCLK High Time t
SCLK Rise and Fall Time t
CS

to SCLK Setup Time t
SCLK to CS
CS

Inactive Time t

Hold Time (Note 28) t

SDO Valid to SCLK (Note 29) t
CS

to SDO High Z t

Notes: 28. If SPOL = 0, then CS

should return high no sooner than 20 ns after the 16th rising edge of SCLK during

a serial port read.

29. Output load capacitance = 50 pF.

dc

cdh

cl

ch

, t

r

cc

cch

cwh

cdv
cdz

f

= -40 to 85 °C; DV+, TV+, RV+ =

A

25 - - ns
25 - - ns
50 - - ns
50 - - ns

- - 15 ns
20 - - ns
20 - - ns

100 - - ns

- - 50 ns

-50-ns

t

cwh

CS

SCLK

SDI

SCLK

SDO

CS

t

ch

t

cc

t

dc

LSB LSB MSB

CONTROL BYTE DATA BYTE

t

cl

t

cdh

t

cdh

Figure 4. Serial Port Write Timing Diagram

t

cdv

t

cch

t

cdz

HIGH

SPOL = 0

Figure 5. Serial Port Read Timing Diagram

10 DS261PP5

10 DS261F1

DS261PP5

CS61584A

CS61584A

SWITCHING CHARACTERISTICS - PARALLEL PORT (T

= -40 to 85 °C;

A

TV+, RV+ = nominal ± 0.3 V; Inputs: Logic 0 = 0 V, Logic 1 = RV+)

Parameter Symbol Min Max Unit

Cycle Time t
Pulse Width, DS Low or RD
Pulse Width, DS High or RD

High PW

Low PW
Input Rise/Fall Times t
R/W

Hold Time t

R/W

Setup Time Before DS High t

CS

Setup Time Before DS, WR, or RD Active t

CS

Setup Time Before DS, WR, or RD Active for RAM/ROM t

CS

Hold Time t
Read Data Hold Time t
Write Data Hold Time t
Muxed Address Valid to AS or ALE Fall t
Muxed Address Hold Time t
Delay Time DS, WR

, or RD to AS or ALE Rise t

cyc

, t

r
rwh
rws

cs

csr

ch

dhr

dhw

asl
ahl

asd

el

eh

f

250 - ns
150 - ns
150 - ns

-30ns
10 - ns
50 - ns
50 - ns

130 - ns

20 - ns
10 80 ns

5-ns
15 - ns
10 - ns
25 - ns

Pulse Width AS or ALE High 40 - ns
Delay Time AS or ALE to DS, WR
Output Data Delay Time from DS or RD
Data Setup Time t
DTACK
DTACK

Delay t
Hold Time t

AS/ALE Min Low Interval for RAM/ROM t

, or RD t

ased

t

ddr

dsw

dkd
dkh

aamir

40 - ns
20 120 ns
80 - ns

5-ns

5-ns
50 - ns

DS261PP5 11

DS261F1 11

AS

DS

R/W

AD0-AD7

(READ)

CS

AD0-AD7

(WRITE)

(READ and WRITE)

DTACK

DS261PP5

PW

ash

PW

t

asd

t

asl

t

asl

t

ased

t

rws

t

ahl

t

cs

t

ahl

t

dkd

Figure 6. Parallel Port Timing - Motorola Mode

eh

t

cyc

t

ddr

t

dsw

t

dhw

CS61584A

CS61584A

t

rwh

t

dhr

t

ch

t

dkh

ALE

WR

RD

CS

AD0-AD7

ALE

RD

AD0-AD7

WR

CS

t

cyc

PW

t

asd

t

asd

ash

t

ased

t

cs

t

asl

t

ahl

PW

el

t

ddr

Figure 7. Parallel Port Timing - Intel Read Mode

t

cyc

PW

t

asd

t

asd

ash

t

ased

t

cs

t

asl

PW

el

t

ch

t

dhr

t

ch

t

dhw

t

ahl

t

dsw

Figure 8. Parallel Port Timing - Intel Write Mode

12 DS261PP5

12 DS261F1

DS261PP5

CS61584A

CS61584A

ALE

WR

RD

CS

AD0-AD7

AS

DS

R/W

AD0-AD7

(READ)

CS

AD0-AD7

(WRITE)

(READ and WRITE)

DTACK

t

asd

t

asd

PW

ash

t

t

asd

t

asl

t

asl

t

ahl

aamir

t

ahl

PW

ash

PW

t

ased

t

rws

t

asl

t

t

csr

t

asl

ahl

t

ahl

eh

t

cyc

t

ddr

t

dsw

t

dkd

t

t

ch

t

dhw

Figure 9. Parallel Port Timing - Motorola Mode to RAM

t

cyc

PW

ash

t

aamir

t

csr

t

asl

t

ahl

PW

ash

t

ased

t

asl

t

ahl

PW

t

ddr

Figure 10. Parallel Port Timing - Intel Read Mode from RAM or ROM

t

rwh

dhr

t

dkh

el

t

ch

t

dhr

t

cyc

ALE

WR

t

asd

t

asd

PW

ash

t

aamir

PW

ash

t

ased

PW

el

RD

t

csr

t

ch

CS

t

asl

t

asl

t

dhr

AD0-AD7

t

t

ahl

t

ahl

dsw

Figure 11. Parallel Port Timing - Intel Write Mode to RAM

DS261PP5 13

DS261F1 13

DS261PP5

CS61584A

CS61584A

SWITCHING CHARACTERISTICS - JTAG (T

= -40 to 85 °C; TV+, RV+ = nominal ± 0.3 V;

A

Inputs: Logic 0 = 0 V, Logic 1 = RV+)

Parameter Symbol Min Max Unit

Cycle Time t
J-TMS/J-TDI to J-TCK Rising Setup Time t
J-TCK Rising to J-TMS/J-TDI Hold Time t
J-TCK Falling to J-TDO Valid t

t

cyc

J-TCK

t

t

su

J-TMS
J-TDI

J-TDO

h

cyc

su

h

dv

t

200 - ns

50 - ns
50 - ns

-60ns

dv

Figure 12. JTAG Switching Characteristics

14 DS261PP5

14 DS261F1

DS261PP5

CS61584A

CS61584A

2. OVERVIEW

The CS61584A is a dual line interface for T1/E1
applications, designed for high-volume cards
where low power and high density are required.
The device can be operated in either Hardware
mode using control pins or in Host mode using an
internal register set. One board design can support
all T1/E1 short-haul modes by only changing com­ponent values in the receive and transmit paths (if
REFCLK and TCLK are connected externally).
Figure 13 illustrates applications of the CS61584A
in various environments.

LOOP TIMED APPLICATION

CS62180B

FRAMER

TPOS
TNEG

TCLK

RCLK
RPOS

RNEG

REFCLK

ATTENUATOR

JITTER

CS61584A

The line driver generates waveforms compatible
with E1 (CCITT G.703), T1 short haul (DSX-1)
and T1 FCC Part 68 Option A (DS1). A single
transformer turns ratio is used for all waveform
types. The driver internally match es the impedance
of the load, providing excellent return loss to insure
superior T1/E1 pulse quality. An additional benefit
of the internal impedance matching is a 50 percent
reduction in power consumption compared to im­plementing return loss using external resistors that
causes the transmitter to drive the equivalent of two
line loads.

LINE DRIVER

LINE RECEIVER

TTIP

TRING

RTIP

RRING

TRANSMIT

CIRCUITRY

RECEIVE

CIRCUITRY

MUX

CS62180B

FRAMER

TDATA

TCLK

(gapped)

RCLK

RDATA

TCLK
TPOS
TNEG

RCLK
RPOS

RNEG

ASYNCHRONOUS MUX APPLICATION

(i.e., VT1.5 card for SONET or SDH mux)

REFCLK

AMI

B8ZS,

HDB3,

CODER

(Including 62411 systems with multiple T1 lines)

REFCLK

JITTER

ATTENUATOR

CS61584A

JITTER

ATTENUATOR

AIS

DETECT

SYNCHRONOUS APPLICATION

LINE DRIVER

LINE RECEIVER

CS61584A

LINE DRIVER

LINE RECEIVER

Figure 13. Examples of CS61584A Applications

TTIP

TRING

RTIP

RRING

TTIP

TRING

RTIP

RRING

TRANSMIT

CIRCUITRY

RECEIVE

CIRCUITRY

TRANSMIT

CIRCUITRY

RECEIVE

CIRCUITRY

DS261PP5 15

DS261F1 15

DS261PP5

CS61584A

CS61584A

The line receiver contains all the necessary clock
and data recovery circuits.

The jitter attenuator meets AT&T 62411 require­ments when using either a 1X or 8X reference
clock supplied by either a quartz crystal, crystal os­cillator, or external reference at the REFCLK input
pin.

2.1 AT&T 62411 Customer Premises Application

The AT&T 62411 specification applies to the T1
interface between the customer premises and the
carrier, and must be implemented by the customer
premises equipment in order to connect to the
AT&T network.

In 62411 applications, the management of jitter is a
very important design consideration. Typically, the
jitter attenuator is placed in the receive path of the
CS61584A to reduce the jitter input to the system
synchronizer. The jitter attenuated recovered clock
is used as the input to the transmit clock to imple-

ment a loop-timed system. A Stratum 4 (±32 ppm)
quality clock or better should be input to R EFCLK.
Note that any jitter present on the reference clock
will not be filtered by the jitter attenuator.

2.2 Asynchronous Multiplexer Application

Asynchronous multiplexers accept multiple T1/E1
lines (which are asynchronous to each other ), and
combine them into a higher speed tran smission rate
(e.g. M13 muxes and SONET muxes). In these sys­tems, the jitter attenuator is placed in the transmit
path of the CS61584A to remove the gapped clock
jitter input by the multiplexer to TCLK. Because
the transmit clock is jittered, the reference clock to
the CS61584A is provided by an external source
operating at 1X or 8X the data rate. Because T1/E1
framers are not usually required in asynchronous
multiplexers, the B8ZS/AMI/HDB3 coders in the
CS61584A are activated to provide data interfaces
on TDATA and RDATA.

2.3 Synchronous Application

A typical example of a synchronous application is
a T1 card in a central office switch or a 0/1 digital
cross-connect system. These systems place the jit­ter attenuator in the receive path to reduce the jit ter
presented to the system. A Stratum 3 or better sys­tem clock is input to the CS61584A transmit and
reference clocks.

3. TRANSMITTER

The transmitter accepts data from a T1 or E1 sys­tem and outputs pulses of appropriate shape to the
line. The transmit clock (TCLK) and transmit data
(TPOS and TNEG, or TDATA) are supplied syn­chronously. Data is sampled on the falling edge of
the TCLK input.

During Hardware mode operation, the configura­tion pins (CON[3:0]) control transmitted pulse
shapes, transmitter source impedance, receiver
slicing level, and driver tristate as shown in
Table 1. During Host mode operation, the configu­ration is established by the CON[3:0] bits in the
Control B registers. Typical output pulses are
shown in Figures 14 and 15. These pulse shapes are
fully pre-defined by circuitry in the CS61584A,
and are fully compliant with appropriate standards
when used with our application guidelines in stan­dard installations. Both channels must be operated
at the same line rate (both T1 or both E1).

Host mode operation permits arbitrary transmit
pulse shapes to be created and downloaded to the
CS61584A. These custom pulse shapes can be used
to compensate for waveform degradation caused by
non-standard cables, transformers, or protection
circuitry (refer to the Arbitrary Wavefor m Regis­ters section).

Note that the pulse width for Part 68 Option A
(324 ns) is narrower than the optimal pulse width
for DSX-1 (350 ns). The CS61584A automatically
adjusts the pulse width based on the configuration
selection.

16 DS261PP5

16 DS261F1

DS261PP5

500

1.0

0.5

0

-0.5

0 250 750 1000

NORMALIZED
AMPLITUDE

ANSI T1.102
SPECIFICATION

CS61584A

OUTPUT

PULSE SHAPE

TIME (nanoseconds)

e

Percent of
nominal
peak
voltage

120
110
100

90
80

50

269 ns

244 ns
194 ns

CS61584A

CS61584A

G.703
Specification

Figure 14. Typical Pulse Shape at DSX-1 Cross Connect

C

C

C

C

Transmit Pulse

O

O

O

O

Width at 50%

N

N

N

N

3

2

1

0

Amplitude

0000 244ns (50%) E1: square, 2.37 V into 75Ω 50% AMI/HDB3
1000 244ns (50%) Arbitrary E1 Wave into 75Ω 50% AMI/HDB3
0001 244ns (50%) E1: square, 2.37 V into 75Ω 50% AMI/HDB3
1001 244ns (50%) Arbitrary E1 Wave into 120Ω 50% AMI/HDB3
0010 350ns (54%) DSX-1: 0-133 ft. 65% AMI/B8ZS
0011 350ns (54%) DSX-1: 133-266 ft. 65% AMI/B8ZS
0100 350ns (54%) DSX-1: 266-399 ft. 65% AMI/B8ZS
0101 350ns (54%) DSX-1: 399-533 ft. 65% AMI/B8ZS
0110 350ns (54%) DSX-1: 533-655 ft. 65% AMI/B8ZS
1010 350ns (54%) Arbitrary DSX-1 Waveform 65% AMI/B8ZS
0111 324ns (50%) DS1: FCC Part 68 Option A with undershoot 65% AMI/B8ZS
1100 324ns (50%) DS1: FCC Part 68 Option A (0 dB) 65% AMI/B8ZS
1011 324ns (50%) Arbitrary DS1 Waveform 65% AMI/B8ZS
1101 Reserved
1110 Transmit Hi Z Tristate TTIP/TRING Driver Outputs 50% AMI/HDB3
1111 Transmit Hi Z Tristate TTIP/TRING Driver Outputs 65% AMI/B8ZS

DS261PP5 17

DS261F1 17

10

0

-10

-20

Figure 15. Mask of the Pulse at the 2048 kbps Interface

Transmit Pulse Shape Receiver

Table 1. Line Configuration Selections

219 ns

488 ns

Slicing

Level

Nominal Puls

Line Code

Encoder /

Decoder