Cirrus Logic CS61583-IQ5, CS61583-IL5 Datasheet

Dual T1/E1 Line Interface

CS61583

Features

Dual T1/E1 Line In terface

•

Low Power Consumption

•

(Typically 220mW per Line Interface) Matched Impedance Transmit Drivers

•

Common Transmit and Receive Transform-

•

ers for all Modes Selectable Jitter Attenuation for Transmit

•

or Receive Paths Supports JTAG Boundary Scan

•

Hardware Mode Derivative of the CS61584

•

TCLK1 TPOS1/

TDATA1 TNEG1/

AIS1 RCLK1 RPOS1/

RDATA1 RNEG1/

BPV1

TCLK2 TPOS2/

TDATA2 TNEG2/

AIS2 RCLK2

RPOS2/ RDATA2

RNEG2/ BPV2

CLKE TAOS1

RESET

ATTEN2

JITTER

ATTENUATOR

JITTER

ATTENUATOR

CON01

CON11

CON21

L O C A L

L O O P B A C K

L O C A L

L O O P B A C K

General Description

The CS61583 is a dual line interface for T1/E1 applications, designed for high-volume cards where low power and high density are required. Each channel features individual control and status pins which eliminates the need for external microprocessor support. The matched impedance drivers reduce power consumption and provide substantial return loss to insure superior T1/E1 pulse quality.

The CS61583 provides JTAG boundary scan to enhance system testability and reliability. The CS61583 is a 5 volt device and is a hardware mode derivative of the CS61584.

ORDERING INFORMATION

CS61583-IL5: 68-pin PLCC, -40 to +85 °C CS61583-IQ5: 64-pin TQFP, -40 to +85 °C

LLOOP1

CONTROL

TAOS

LOS

DETECT

TAOS

LOS

DETECT

RLOOP1

CIRCUITRY

RECOVERY

CIRCUITRY

RECOVERY

CODER2CODER1ATTEN1

PULSE

SHAPING

CLOCK &

DATA

PULSE

SHAPING

CLOCK &

DATA

CON02

CON12

DRIVE R

DRIVER

AMI2AMI1

CON22

RECEIVER

TAOS2

LLOOP2

RLOOP2

TTIP1 TRING1

RTIP1 RRING1

TTIP2 TRING2

RTIP2 RRING2

JTAG

CLOCK GEN ERAT OR

REFCLK 1XCLK

Crystal Semiconductor Corporation

P. O. Box 17847, Austin, Texas, 78760 (512) 445 7222 FAX:(512) 445 7581

LOS1 LOS2

2 2 2 2 3 2

TV+ TGND RV+ RGND DV+ DGND AV+ AGND

BGREF

JULY ’96

DS172PP5

Table of Contents

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Specifications

Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . 3

Recommended Operating Conditions. . . . . . . . . . . . . . . . . . 3

Digital Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Analog Specifications

Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Jitter Attenuator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Switching Characteristics

T1 Clock/Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

E1 Clock/Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

JTAG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

CS61583

General Description

Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Jitter Attenuator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Power-Up Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Line Control and Monitoring . . . . . . . . . . . . . . . . . . . . . . . . 13

Line Code Encoder/Decoder. . . . . . . . . . . . . . . . . . . 13

Alarm Indication Signal . . . . . . . . . . . . . . . . . . . . . . 14

Bipolar Violation Detection . . . . . . . . . . . . . . . . . . . 14

Loss of Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Transmit All Ones . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Local Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Remote Loopback. . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

JTAG Boundary Scan. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Physical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

2 DS172PP5

CS61583

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Min Max Units

DC Supply (TV+1, TV+2, RV+1, RV+ 2, AV+, DV+) (Note 1) - 6.0 V Input Voltage (Any Pin) V Input Current (Any Pin) (Note 2) I Ambient Operating Temperature T Storage Temperature T

stg

RGND - 0.3 (RV+) + 0.3 V

-10 10 mA

-40 85 °C

-65 150 °C

WARNING: Operations at or beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes.

Notes: 1. Referenced to RGND1, RGND2, TGND1, TGND2, AGND, DGND at 0V.

2. Transient cur rents of up to 100 mA will not cause SCR latch-up.

RECOMMENDED OPERATING CONDITIONS

Parameter Symbol Min Typ Max Units

DC Supply (TV+1, TV+2, RV+1, RV+ 2, AV+, DV+) (Note 3) 4.75 5.0 5.25 V Ambient Operating Temperature T

Power Consumption T1 (Notes 4 and 5) (Each Channel) T1 (Notes 4 and 6)

E1, 75Ω (Notes 4 and 5)

E1, 120Ω (Notes 4 and 5)

REFCLK Frequency

T1 1XCLK = 1

T1 1XCLK = 0

E1 1XCLK = 1

E1 1XCLK = 0

Notes: 3. TV+1, TV+2, AV+, DV+, RV+1, RV+2 should be connected together. TGND1, TGND2, RGND1,

RGND2, DGND1, DGND2, DGND3 should be connected together.

4. Power consumption while driving line load over operating temperature range. Includes IC and load. Digital input levels are within 10% of the supply rails and digital outputs are driving a 50 pF capacitive load.

5. As sumes 100% ones density and maximum line length at 5.25V.

6. As sumes 50% ones density and 300ft. line length at 5.0V.

-40 25 85 °C

1.544 -

100 ppm

12.352 -

100 ppm

2.048 -

100 ppm

16.384 -

100 ppm

310 220 275 275

1.544

12.352

2.048

16.384

1.544 +

100 ppm

12.352 + 100 ppm

2.048 +

100 ppm

16.384 + 100 ppm

MHz

mW mW mW mW

DS172PP5 3

CS61583

DIGITAL CHARACTERISTICS (T

= -40 to 85 °C; power supply pins within ±5% of nominal)

Parameter Symbol Min Typ Max Units

High-Level Input Voltage (Note 7) V Low-Level Input Voltage (Note 7) V High-Level Output Voltage (Note 8)

(Digital pins) I

OUT

= -40 µA

Low-Level Output Voltage (Note 8) (Digital pins) I

OUT

= 1.6 mA

Input Leakage Current (Digital pins except J-TMS, and J-TDI)

(DV+)-0.5 - - V

IH IL

--0.5V

(DV+)-0.3 - - V

--0.3V

±10 µA

Notes: 7. Digital inputs are designed for CMOS logic levels .

8. Digital outputs are TTL compatible and drive CMOS levels into a CMOS load.

ANALOG SPECIFICATIONS (T

= -40 to 85 °C; power supply pins within ±5% of nominal)

Parameter Min Typ Max Units

Receiver

RTIP/RRING Differential Input Impedance

- 20k Sensitivity Below DSX-1 (0 dB = 2.4 V) -13.6 - - dB Loss of Signal Threshold - 0.3 - V Data Decision Threshold T1, DSX-1 (Note 9)

(Note 10)

E1 (Note 11)

(Note 12)

60 55 45 40

65 50

75 55 60

% of

Peak

Allowable Consecutive Zeros before LOS 160 175 190 bits Receiver Input Jitter 10 Hz and below (Note 13)

Tolerance (DSX-1, E1) 2 kHz

10 kHz - 100 kHz

Receiver Return Loss 51 kHz - 102 kHz (Notes 14,

102 kHz - 2.048 MHz 21, and 22)

2.048 MHz - 3.072 MHz

300

6.0

0.4 12

18 14

dB dB dB

Jitter Attenuator

Jitter Attenuation Curve T1 (Notes 14 and 15) Corner Frequency E1

5.5

Hz Attenuation at 10 kHz Jitter Frequency (Notes 14 and 15) - 60 - dB Attenuator Input Jitter Tolerance (Note 14)

(Before Onset of FIFO Overflow or Underflow Protection)

Notes: 9. For input amplitude of 1.2 Vpk to 4.14 V

10. For input amplitude of 0.5 Vpk to 1.2 Vpk, and 4.14 Vpk to 5.0 V

28 43 - UI

11. For input amplitude of 1.07 Vpk to 4.14 Vpk,

12. For input amplitude of 4.14 V

to 5.0 Vpk,

13. Jitter tolerance increases at lower frequencies. Refer to the Receiver section.

14. Not production tested. Parameters guaranteed by design and characterization.

15. Attenuation measur ed with sinusoidal input jitter equal to 3/4 of measured jitter tolerance. Circuit attenuates jitter at 20 dB/decade above the corner frequency. Output jitter can increase significantly when more than 28 UI’s are input to the attenuator. Refer to the Jitter Attenuator section.

Ω

UI UI UI

pk-pk

4 DS172PP5

CS61583

ANALOG SPECIFICATIONS (T

= -40 to 85 °C; power supply pins within ±5% of nominal)

Parameter Min Typ Max Units

Transmitter

AMI Output Pulse Amplitudes (Note 16)

E1, 75Ω (Note 17) E1, 120Ω (Note 18) T1, DSX-1 (Note 19)

2.14

2.7

2.4

2.37

3.0

2.6

3.3

3.6

Recommended Transmitter Output Load (Note 16)

T1 E1, 75Ω E1, 120Ω

Jitter Added During 10 Hz - 8 kHz Remote Loopback 8 kHz - 40 kHz

10 Hz - 40 kHz Broad Band (Note 20)

Power in 2 kHz band about 772 kHz (Notes 14 and 21)

(DSX-1 only)

Power in 2 kHz band about 1.544 MHz (Notes 14 and 21)) (referenced to power in 2 kHz band at 772 kHz) (DSX-1 only)

76.6

57.4

90.6

0.005

0.008

0.010

0.015

12.6 15 17.9 dBm

-29 -38 - dB

Positive to Negative Pulse Imbalance (Notes 14 and 21)

T1, DSX-1 E1, amplitude at center of pulse interval E1, width at 50% of nominal amplitude

-5

0.2

0.5 +5 +5

Transmitter Return Loss (Notes 14, 21, and 22)

51 kHz - 102 kHz 102 kHz - 2.048 MHz

2.048 MHz - 3.072 MHz

18 14 10

25 18 12

E1 Short Circuit Current (Note 23) - - 50 mA E1 and DSX-1 Output Pulse Rise/Fall Times (Note 24) - 25 - ns E1 Pulse Width (at 50% of peak amplitude) - 244 - ns E1 Pulse Amplitude E1, 75Ω

for a space E1, 120Ω

-0.237

-0.3

0.237

0.3

Notes: 16. Using a tr ansformer that meets the specifications in the Applications section.

17. Measur ed across 75 Ω at the output of the transmit transformer for CO N2/1/0 = 0/0/0.

18. Measur ed across 120 Ω at the output of the transmit transformer for CO N2/1/0 = 0/0/1.

19. Measur ed at the DSX-1 cross- connect for line length settings CON2/1/0 = 0/1/0, 0/1/1, 1/0/0, 1/0/1, and 1/1/0 after the appropriate length of #22 ABA M cable specified in Table 1.

20. Input s ignal to RTIP/RRING is jitter free. Values will reduc e slightly if jitter free c lock is input to TCLK.

21. Ty pical performance using the line interface circuitry recommended in the Applications section.

22. Return loss = 20 log

=cable impedance.

ABS((z1+z0)/(z1-z0)) where z1=impedance of the transmitter or receiver, and

23. Transfor mer secondary shorted with 0.5 Ω resistor during the transmission of 100% ones.

24. At trans former secondary and measured from 10% to 90% of amplitude.

V V V

Ω Ω Ω

UI UI UI UI

% %

dB dB dB

rms

V V

DS172PP5 5

CS61583

SWITCHING CHARACTERISTICS - T1 CLOCK/DATA (T

= -40 to 85 °C; power supply

pins within ±5% of nominal; Inputs: Logic 0 = 0V, Logic 1 = DV+) (See Figures 1, 2, and 3)

Parameter Symbol Min Typ Max Units

TCLK Frequency (Note 25) f TCLK Duty Cycle t RCLK Duty Cycle (Note 26) t

pwh2/tpw2 pwh1/tpw1

Rise Time (All Digital Outputs) (Note 27) t Fall Time (All Digital Outputs) (Note 27) t RPOS/RNEG (RDATA) to RCLK Rising Setup Time t RCLK Rising to RPOS/RNEG (RDATA) Hold Time t TPOS/TNEG (TDATA) to TCLK Falling Setup Time t TCLK Falling to TPOS/TNEG (TDATA) Hold Time t

tclk

r f

su1

su2

- 1.544 - MHz 30 50 70 % 45 50 55 %

- - 65 ns

- 274 - ns

- 274 - ns 25 - - ns 25 - - ns

Notes: 25. The maximum burst rate of a gapped TCLK input clock is 8.192 MHz. For the gapped clock to be

tolerated by the CS61583, the jitter attenuator must be switched to the transmit path of the line interface. The maximum gap size that can be tolerated on TCLK is 28 UIp-p.

26. RCLK duty cycle may be outside the specified limits when the jitter attenuator is in the r eceive path, and when the jitter attenuator is employing the overflow/underflow protection mec hanism.

27. At max load of 50 pF.

SWITCHING CHARACTERISTICS - E1 CLOCK/DATA (T

= -40 to 85 °C; power supply

pins within ±5% of nominal; Inputs: Logic 0 = 0V, Logic 1 = DV+) (See Figures 1, 2, and 3)

Parameter Symbol Min Typ Max Units

TCLK Frequency (Note 25) f TCLK Duty Cycle t RCLK Duty Cycle (Note 26) t

pwh2/tpw2 pwh1/tpw1

tclk

r f

su1

su2

- 2.048 - MHz 30 50 70 % 45 50 55 %

- - 65 ns

- 194 - ns

- 194 - ns 25 - - ns 25 - - ns

6 DS172PP5

CS61583

RCLK (CLKE = 1)

RPOS RNEG RDATA BPV

Any Digital Output

Figure 1. Signal Rise and Fall Characteristics

pwl1

su1

90% 90%

10% 10%

pw1

pwh1

RCLK (CLKE =0)

Figure 2. Recovered Clock and Data Sw itching Characterist ics

pw2

pwh2

TCLK

t TPOS TNEG TDATA

Figure 3. Transmit Clock and Data Switching Characteristics

DS172PP5 7

su2

CS61583

SWITCHING CHARACTERISTICS - JTAG

TV+, RV+ = nominal ±0.3V; Inputs: Logic 0 = 0V, Logic 1 = RV+) (See Figure 4)

Parameter Symbol Min Typ Max Units

Cycle Time t J-TMS/J-TDI to J-TCK rising setup time t J-TCK rising to J-TMS/J-TDI hold time t J-TCK falling to J-TDO valid t

(TA = - 40 ° to 85 ° C;

200 - - ns

50 - - ns 50 - - ns

- - 50 ns

cyc

J-TCK

J-TMS J-TDI

J-TDO

Figure 4. JAG Switching Characte ristics

8 DS172PP5

CS61583

OVERVIEW

The CS61583 is a dual line interface for T1/E1 applications, designed for high-volume cards where low power and high density are required. One board design can support all T1/E1 shorthaul modes by only changing component values in the receive and transmit paths (if REFCLK and TCLK are externally tied together). Figure 5 illustrates applications of the CS61583 in various environments.

All control of the device is achieved via external pins, eliminating the need for microprocessor

LOOP TIMED APPLICATION

CS62180B

FRAMER

TPOS

TNEG

TCLK

RCLK RPOS

RNEG

REFCLK

JITTER

ATTENUATOR

CS61583

support. The following pin control options are available on a per channel basis: line length selection, coder mode, jitter attenuator location, transmit all ones, local loopback, and remote loopback.

The line driver generates waveforms compatible with E1 (CCITT G.703), T1 short haul (DSX-1), and T1 FCC Part 68 Option A (DS1). A single transformer turns ratio is used for all waveform types. The driver internally matches the impedance of the load, providing excellent return loss to insure superior T1/E1 pulse quality. An addi-

LINE D R IV ER

LINE RECEIVER

TTIP

TRING

RTIP

RRING

TRANSMIT

CIRCUITRY

RECEIVE

CIRCUITRY

MUX

CS62180B

FRAMER

TDATA

TCLK

(gapped)

RCLK

RDATA

TCLK TPOS TNEG

RCLK RPOS

RNEG

ASYNCHRONOU S MU X APPLICATION

(i.e., VT1 .5 c ard f or S O NET o r S DH mu x)

REFCLK

AMI B8ZS, HDB3,

CODER

REFCLK

ATTENUATOR

(Including 62411 system s w ith m u ltiple T1 lines)

JITTER

CS61583

JITTER

AIS

DETECT

SYNCHRONOUS A PPLICATION

LINE DRIVER

LINE RECEIVER

CS61583

LINE D R IV ER

LINE RECEIVER

Figure 5. Examples of CS61583 A pplications

TTIP

TRING

RTIP

RRING

TTIP

TRING

RTIP

RRING

TRANSMIT

CIRCUITRY

RECEIVE

CIRCUITRY

TRANSMIT

CIRCUITRY

RECEIVE

CIRCUITRY

DS172PP5 9

CS61583

tional benefit of the internal impedance matching is a 50 percent reduction in power consumption compared to implementing return loss using external resistors that causes the transmitter to drive the equivalent of two line loads.

The line receiver contains all the necessary clock and data recovery circuits.

The jitter attenuator meets AT&T 62411 requirements when using a 1X or 8X reference clock supplied by either a crystal oscillator or external reference at the REFCLK input pin.

AT&T 62411 Customer Premises Application

The AT&T 62411 specification applies to the T1 interface between the customer premises and the carrier, and must be implemented by the customer premises equipment in order to connect to the AT&T network.

In 62411 applications, the management of jitter is a very important design consideration. Typically, the jitter attenuator is placed in the receive path of the CS61583 to reduce the jitter input to the system synchronizer. The jitter attenuated recovered clock is used as the input to the transmit clock to implement a loop-timed system. A Stra-

tum 4 (±32 ppm) quality clock or better should be input to REFCLK. Note that any jitter present on the reference clock will not be filtered by the

jitter attenuator.

not usually required in asynchronous multiplexers, the B8ZS/AMI/HDB3 coders in the CS61583 are activated to provide data interfaces

on TDATA and RDATA.

Synchronous Application

A typical example of a synchronous application is a T1 card in a central office switch or a 0/1 digital cross-connect system. These systems place the jitter attenuator in the receive path to reduce the jitter presented to the system. A Stratum 3 or better system clock is input to the CS61583 transmit and reference clocks.

TRANSMITTER

The transmitter accepts data from a T1 or E1 system and outputs pulses of appropriate shape to the line. The transmit clock (TCLK) and transmit data (TPOS & TNEG, or TDATA) are supplied synchronously. Data is sampled on the falling edge of the TCLK input.

The configuration pins CON[2:0] control transmitted pulse shapes, transmitter source impedance, and receiver slicing level as shown in Table 1. Typical output pulses are shown in Figures 6 and 7. These pulse shapes are fully pre-defined by circuitry in the CS61583, and are fully compliant with appropriate standards when used with our application guidelines in standard installations. Both channels must be operated at the same line rate (both T1 or both E1).

Asynchronous Multiplexer Application

Note that the pulse width for Part 68 Option A

Asynchronous multiplexers accept multiple T1/E1 lines (which are asynchronous to each other), and combine them into a higher speed transmission rate (e.g. M13 muxes and SONET

(324 ns) is narrower than the optimal pulse width for DSX-1 (350 ns). The CS61583 automatically adjusts the pulse width based on the configuration selection.

muxes). In these systems, the jitter attenuator is placed in the transmit path of the CS61583 to remove the gapped clock jitter input by the multiplexer to TCLK. Because the transmit clock is jittered, the reference clock to the CS61583 is provided by an external source operating at 1X or 8X the data rate. Because T1/E1 framers are

10 DS172PP5

The transmitter impedance changes with the line length options in order to match the load imped-

ance (75Ω for E1 coax, 100Ω for T1, 120Ω for E1 shielded twisted pair), providing a minimum of 14 dB return loss for T1 and E1 frequencies

CS61583

NORMALIZED AMPLITUDE

1.0

ANSI T1.102

SPECIFICATION

0.5

CS61583 OUTPUT

PULSE SHAPE

-0.5

0 250 750 1000

500

TIME (nanoseconds)

Figure 6. Typical Pulse Shape at DSX-1 Cross Connect

during the transmission of both marks and spaces. This improves signal quality by minimizing reflections from the transmitter. Impedance matching also reduces load power consumption by a factor of two when compared to the return loss achieved by using external resistors.

The CS61583 driver will automatically detect an inactive TLCK input (i.e., no valid data is being clocked to the driver). When this condition is detected, the driver is forced low (except during remote loopback) to output spaces and prevent TTIP and TRING from entering a constant transmit-mark state.

Percent of nominal peak voltage

120 110 100

90 80

-10

-20

269 ns

244 ns

194 ns

219 ns

488 ns

G.703 Specification

Nominal Pulse

Figure 7. Pulse Mask at the 2048 kbps Interface

When any transmit configuration established by CON[2:0], TAOS, or LLOOP changed states, the transmitter stabilizes within 22 TCLK bit periods. The transmitter takes longer to stabilize when RLOOP1 or RLOOP2 is selected because the timing circuitry must adjust to the new frequency from RCLK.

When the transmitter transformer secondaries are shorted through a 0.5 ohm resistor, the transmit-

Transmit Pulse

Width at 50%

Amplitude

000001244 ns (50%)

244 ns (50%)

Transmit Pulse Shape

E1: square, 2.37 Volts into 75 E1: square, 3.00 Volts into 120

Ω

Receiver

Slicing

Level

50% 50%

0 1 0 350 ns (54%) DSX-1: 0-133 ft. / or DS1 FCC Part 68 Option A with undershoot 65% 0 1 1 350 ns (54%) DSX-1: 133-266 ft. 65% 1 0 0 350 ns (54%) DSX-1: 266-399 ft. 65% 1 0 1 350 ns (54%) DSX-1: 399-533 ft. 65% 1 1 0 350 ns (54%) DSX-1: 533-655 ft. 65% 1 1 1 324 ns (50%) DS1: FCC Part 68 Option A (0 dB) 65%

Table 1. Configuration Selection

DS172PP5 11

CS61583

ter will output a maximum of 50 mA-rms, as required by European specification BS6450.

RECEIVER

The receiver extracts data and clock from the T1/E1 signal on the line interface and outputs clock and synchronized data to the system. The signal is detected differentially across the receive transformer and can be recovered over the entire range of short haul cable lengths. The transmit and receive transfomer specifications are identical and are presented in the Applications section.

As shown in Table 1, the receiver slicing level is set at 65% for DS1/DSX-1 short-haul and at 50% for all other applications.

The clock recovery circuit is a second-order phase locked loop that can tolerate up to 0.4 UI of jitter from 10 kHz to 100 kHz without generating errors (Figure 8). The clock and data recovery circuit is tolerant of long strings of consecutive zeros and will successfully recover a 1-in-175 jitter-free line input signal.

Recovered data at RPOS and RNEG (or RDATA) is stable and may be sampled using the recovered clock RCLK. The CLKE input determines the clock polarity for which output data is stable and valid as shown in Table 2. When

CS61583

300 138

100

PEAK-TO-PEAK

JITTER

(unit intervals)

Figure 8. Minimum Input Jitter Tolerance of Receiver

28 10

(Clock Recovery Circuit and Jitter Attenuator)

AT&T 62411

(1990 Version)

Performance

10 1k 10k1 100 100k700

300

JITTER FREQUENCY (Hz)

CLKE is low, RPOS and RNEG (or RDATA) are valid on the rising edge of RCLK. When CLKE is high, RPOS and RNEG (or RDATA) are valid on the falling edge of RCLK.

CLKE DATA CLOCK Clock Edge

for Valid Data

LOW RPOS, RNEG

or RDATA

HIGH RPOS, RNEG

or RDATA

Table 2. Re covere d Data /Cloc k Optio ns

RCLK RCLK

Rising Rising

Falling Falling

JITTER ATTENUATOR

The jitter attenuator can be switched into either the receive or transmit paths. Alternatively, it can also be removed from both paths to reduce the propagation delay.

The location of the attenuators for both channels is controlled by the ATTEN0 and ATTEN1 pins. Table 3 shows how these pins are decoded.

ATTEN1 ATTEN0 Locatio n of

Jitter Attenuator

00 Receiver 0 1 Disabled 1 0 Transmitter 11 Reserved

Table 3. Jitter Attenuation Control

The attenuator consists of a 64-bit FIFO, a narrow-band monolithic PLL, and control logic. Signal jitter is absorbed in the FIFO which is designed to neither overflow nor underflow. If overflow or underflow is imminent, the jitter transfer function is altered to insure that no biterrors occur. Under this condition, jitter gain may occur and jitter should be attenuated externally in a frame buffer. The jitter attenuator will typically tolerate 43 UIs before the overflow/underflow mechanism occurs. If the jitter attenuator has not had time to "lock" to the aver-

12 DS172PP5

CS61583

age incoming frequency (e.g. following a device reset) the attenuator will tolerate a minimum of 22 UIs before the overflow/underflow mechanism occurs.

For T1/E1 line cards used in high-speed mutiplexers (e.g., SONET and SDH), the jitter attenuator is typically used in the transmit path. The attenuator can accept a transmit clock with

gaps ≤ 28 UIs and a transmit clock burst rate of ≤ 8 MHz.

When the jitter attenuator is in th e receive path and loss of signal occurs, the frequency of the last recovered signal is held. When the jitter attenuator is not in the receive path, the last recovered frequency is not held and the output frequency becomes the frequency of the reference clock.

A typical jitter attenuation curve is shown in Figure 9.

jittered transmit clock, the reference clock should not be tied to the transmit clock and a separate external oscillator should drive the reference clock input. Any jitter present on the reference clock will not be filtered by the jitter attenuator.

POWER-UP RESET

On power-up, the device is held in a static state until the power supply achieves approximately 60% of the power supply voltage. When this threshold is crossed, the device waits another 10 ms to allow the power supply to reach operating voltage and then calibrates the transmit and receive circuitry. This initial calibration takes less than 20 ms but can occur only if REFCLK and TCLK are present. The power-up reset performs the same functions as the RESET pin.

LINE CONTROL AND MONITORING

b) Maximum

Attenuation

Attenuation in dB

Limit

1 10 100 1 k 10 k

Figure 9. Typical Jitter Transfer Function

a) Minimum Attenuation Limit

62411 (1990 Version) Requirements

CS61583 Performance

Frequency in Hz

REFERENCE CLOCK

The CS61583 requires a reference clock with a minimum accuracy of ±100 ppm for T1 and E1

applications. This clock can be either a 1X clock (i.e., 1.544 MHz or 2.048 MHz), or can be a 8X clock (i.e., 12.352 MHz or 16.384 MHz) as selected by the 1XCLK pin. In systems with a

Line control and monitoring of the CS61583 is achieved using the control pins. The controls and indications available on the CS61583 are detailed below.

Line Code Encoder/Decoder

Coding may be transparent, AMI, B8ZS, or HDB3 and is selected using the CODER1, CODER2, AMI1, and AMI2 pins. In the coder mode, AMI, B8ZS, and HDB3 line codes are available. The input data to the encoder is on TDATA and the output data from the decoder is in NRZ format on RDATA. See Table 4.

CODER[2:1]=0 CODER[2:1]=1

AMI[2:1]=0

Transparent Mode

Enabled

and

AMI[2:1] Pin(s)

Disabled

Table 4. Coder Mode Options

B8ZS/HDB3

Encoder/Decoder

Enabled

AMI[2:1]=1

AMI

Encoder/Decoder

Enabled

DS172PP5 13

CS61583

Alarm Indication Signal

In coder mode, the TNEG pin becomes the alarm indication signal (AIS) output controlled by the receiver. The receiver detects the AIS condition on observation of 99.9% ones density in a 5.3 ms period (< 9 zeros in 8192 bits) and sets the AIS pin high. The AIS condition is ex-

ited when ≥ 9 zeros are detected in 8192 bits.

Bipolar Violation Detection

In coder mode, the RNEG pin becomes the bipolar violation (BPV) strobe output controlled by the receiver. The BPV pin goes high for one RCLK period when a bipolar violation is detected in the received signal. Note that B8ZS or HDB3 zero substitutions are not flagged as bipolar violations when the decoder is enabled.

Loss of Signal

The loss of signal (LOS) indication is detected by the receiver and reported when the LOS pin

is high. Loss of signal is indicated when 175±15 consecutive zeros are received. The LOS condition is exited according to the ANSI T1.231-1993 criteria that requires 12.5% ones

density over 175±75 bit periods with no more than 100 consecutive zeros. Note that bit errors may occur at RPOS and RNEG (or RDATA) prior to the LOS indication if the analog input level falls below the receiver sensitivity.

The LOS pin is set high when the device is reset or in powered up and returns low when data is recovered by the receiver.

Transmit All Ones

Transmit all ones is selected by setting the TAOS pin high. Selecting TAOS causes continuous ones to be transmitted to the line interface on TTIP and TRING at the frequency of REFCLK. In this mode, the transmit data inputs TPOS and TNEG (or TDATA) are ignored. A TAOS overrides the data transmitted to the line interface during local and remote loopbacks.

Local Loopback

A local loopback is selected by setting the LLOOP pin high. Selecting LLOOP causes the TCLK, TPOS, and TNEG (or TDATA) inputs to be looped back through the jitter attenuator (if enabled) to the RCLK, RPOS, and RNEG (or RDATA) outputs. Data received at the li ne interface is ignored, but data at TPOS and TNEG (or TDATA) continues to be transmitted to the line interface at TTIP and TRING.

A TAOS request overrides the data transmitted to the line interface during local loopback. Note that simultaneous selection of local and remote loopback modes is not valid.

Remote Loopback

A remote loopback is selected by setting the RLOOP pin high. Selecting RLOOP causes the data received from the line interface at RTIP and RRING to be looped back through the jitter attenuator (if enabled) and retransmitted on TTIP and TRING. Data transmitted at TPOS and TNEG (or TDATA) is ignored, but data recovered from RTIP and RRING continues to be transmitted on RPOS and RNEG (or RDATA).

Remote loopback is functional if TCLK is absent. A TAOS request overrides the data transmitted to the line interface during a remote loopback. Note that simultaneous selection of local and remote loopback modes is not valid.

Reset Pin

The CS61583 is continuously calibrated during operation to insure the performance of the device over power supply and temperature. The continuous calibration function eliminates the need to reset the line interface during operation.

A device reset may be selected by setting the RESET pin high for a minimum of 200 ns. The reset function initiates on the falling edge of RESET and takes less than 20 ms to complete. The control logic is initialized and the transmit and

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