Dual T1/E1 Line Interface
CS61583
Features
Dual T1/E1 Line In terface
•
Low Power Consumption
•
(Typically 220mW per Line Interface)
Matched Impedance Transmit Drivers
•
Common Transmit and Receive Transform-
•
ers for all Modes
Selectable Jitter Attenuation for Transmit
•
or Receive Paths
Supports JTAG Boundary Scan
•
Hardware Mode Derivative of the CS61584
•
TCLK1
TPOS1/
TDATA1
TNEG1/
AIS1
RCLK1
RPOS1/
RDATA1
RNEG1/
BPV1
TCLK2
TPOS2/
TDATA2
TNEG2/
AIS2
RCLK2
RPOS2/
RDATA2
RNEG2/
BPV2
CLKE TAOS1
RESET
E
R
N
E
C
M
O
O
D
T
E
E
R
L
D
O
E
O
C
P
O
B
D
A
E
C
R
K
E
R
N
E
C
M
O
O
D
T
E
E
R
L
D
O
E
O
C
P
O
B
D
A
E
C
R
K
ATTEN2
JITTER
ATTENUATOR
JITTER
ATTENUATOR
CON01
CON11
CON21
L
O
C
A
L
L
O
O
P
B
A
C
K
L
O
C
A
L
L
O
O
P
B
A
C
K
General Description
The CS61583 is a dual line interface for T1/E1 applications, designed for high-volume cards where low power
and high density are required. Each channel features
individual control and status pins which eliminates the
need for external microprocessor support. The
matched impedance drivers reduce power consumption
and provide substantial return loss to insure superior
T1/E1 pulse quality.
The CS61583 provides JTAG boundary scan to enhance system testability and reliability. The CS61583 is
a 5 volt device and is a hardware mode derivative of
the CS61584.
ORDERING INFORMATION
CS61583-IL5: 68-pin PLCC, -40 to +85 °C
CS61583-IQ5: 64-pin TQFP, -40 to +85 °C
LLOOP1
CONTROL
TAOS
LOS
DETECT
TAOS
LOS
DETECT
RLOOP1
CIRCUITRY
RECOVERY
CIRCUITRY
RECOVERY
CODER2CODER1ATTEN1
PULSE
SHAPING
CLOCK &
DATA
PULSE
SHAPING
CLOCK &
DATA
CON02
CON12
DRIVE R
DRIVER
AMI2AMI1
CON22
RECEIVER
RECEIVER
TAOS2
LLOOP2
RLOOP2
TTIP1
TRING1
RTIP1
RRING1
TTIP2
TRING2
RTIP2
RRING2
JTAG
4
CLOCK GEN ERAT OR
REFCLK 1XCLK
Crystal Semiconductor Corporation
P. O. Box 17847, Austin, Texas, 78760
(512) 445 7222 FAX:(512) 445 7581
LOS1 LOS2
2 2 2 2 3 2
TV+ TGND RV+ RGND DV+ DGND AV+ AGND
Copyright Crystal Semiconductor Corporation 1996
(All Rights Reserved)
BGREF
JULY ’96
DS172PP5
1
Table of Contents
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Specifications
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . 3
Recommended Operating Conditions. . . . . . . . . . . . . . . . . . 3
Digital Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Analog Specifications
Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Jitter Attenuator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Switching Characteristics
T1 Clock/Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
E1 Clock/Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
JTAG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
CS61583
General Description
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Jitter Attenuator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Power-Up Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Line Control and Monitoring . . . . . . . . . . . . . . . . . . . . . . . . 13
Line Code Encoder/Decoder. . . . . . . . . . . . . . . . . . . 13
Alarm Indication Signal . . . . . . . . . . . . . . . . . . . . . . 14
Bipolar Violation Detection . . . . . . . . . . . . . . . . . . . 14
Loss of Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Transmit All Ones . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Local Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Remote Loopback. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
JTAG Boundary Scan. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Physical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2 DS172PP5
CS61583
ABSOLUTE MAXIMUM RATINGS
Parameter Symbol Min Max Units
DC Supply (TV+1, TV+2, RV+1, RV+ 2, AV+, DV+) (Note 1) - 6.0 V
Input Voltage (Any Pin) V
Input Current (Any Pin) (Note 2) I
Ambient Operating Temperature T
Storage Temperature T
in
in
A
stg
RGND - 0.3 (RV+) + 0.3 V
-10 10 mA
-40 85 °C
-65 150 °C
WARNING: Operations at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
Notes: 1. Referenced to RGND1, RGND2, TGND1, TGND2, AGND, DGND at 0V.
2. Transient cur rents of up to 100 mA will not cause SCR latch-up.
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol Min Typ Max Units
DC Supply (TV+1, TV+2, RV+1, RV+ 2, AV+, DV+) (Note 3) 4.75 5.0 5.25 V
Ambient Operating Temperature T
A
Power Consumption T1 (Notes 4 and 5)
(Each Channel) T1 (Notes 4 and 6)
E1, 75Ω (Notes 4 and 5)
P
C
E1, 120Ω (Notes 4 and 5)
REFCLK Frequency
T1 1XCLK = 1
T1 1XCLK = 0
E1 1XCLK = 1
E1 1XCLK = 0
Notes: 3. TV+1, TV+2, AV+, DV+, RV+1, RV+2 should be connected together. TGND1, TGND2, RGND1,
RGND2, DGND1, DGND2, DGND3 should be connected together.
4. Power consumption while driving line load over operating temperature range. Includes IC and load.
Digital input levels are within 10% of the supply rails and digital outputs are driving a 50 pF
capacitive load.
5. As sumes 100% ones density and maximum line length at 5.25V.
6. As sumes 50% ones density and 300ft. line length at 5.0V.
-40 25 85 °C
-
-
-
-
1.544 -
100 ppm
12.352 -
100 ppm
2.048 -
100 ppm
16.384 -
100 ppm
310
220
275
275
1.544
12.352
2.048
16.384
-
-
-
-
1.544 +
100 ppm
12.352 +
100 ppm
2.048 +
100 ppm
16.384 +
100 ppm
MHz
MHz
MHz
MHz
mW
mW
mW
mW
DS172PP5 3
CS61583
DIGITAL CHARACTERISTICS (T
= -40 to 85 °C; power supply pins within ±5% of nominal)
A
Parameter Symbol Min Typ Max Units
High-Level Input Voltage (Note 7) V
Low-Level Input Voltage (Note 7) V
High-Level Output Voltage (Note 8)
(Digital pins) I
OUT
= -40 µA
Low-Level Output Voltage (Note 8)
(Digital pins) I
OUT
= 1.6 mA
V
V
Input Leakage Current
(Digital pins except J-TMS, and J-TDI)
(DV+)-0.5 - - V
IH
IL
OH
OL
--0.5V
(DV+)-0.3 - - V
--0.3V
--
±10 µA
Notes: 7. Digital inputs are designed for CMOS logic levels .
8. Digital outputs are TTL compatible and drive CMOS levels into a CMOS load.
ANALOG SPECIFICATIONS (T
= -40 to 85 °C; power supply pins within ±5% of nominal)
A
Parameter Min Typ Max Units
Receiver
RTIP/RRING Differential Input Impedance
- 20k Sensitivity Below DSX-1 (0 dB = 2.4 V) -13.6 - - dB
Loss of Signal Threshold - 0.3 - V
Data Decision Threshold T1, DSX-1 (Note 9)
(Note 10)
E1 (Note 11)
(Note 12)
60
55
45
40
65
50
70
-
-
75
55
60
% of
Peak
Allowable Consecutive Zeros before LOS 160 175 190 bits
Receiver Input Jitter 10 Hz and below (Note 13)
Tolerance (DSX-1, E1) 2 kHz
10 kHz - 100 kHz
Receiver Return Loss 51 kHz - 102 kHz (Notes 14,
102 kHz - 2.048 MHz 21, and 22)
2.048 MHz - 3.072 MHz
300
6.0
0.4
12
18
14
-
-
-
-
-
-
-
-
-
-
-
-
dB
dB
dB
Jitter Attenuator
Jitter Attenuation Curve T1 (Notes 14 and 15)
Corner Frequency E1
-
-
4
5.5
-
-
Hz
Hz
Attenuation at 10 kHz Jitter Frequency (Notes 14 and 15) - 60 - dB
Attenuator Input Jitter Tolerance (Note 14)
(Before Onset of FIFO Overflow or Underflow Protection)
Notes: 9. For input amplitude of 1.2 Vpk to 4.14 V
pk
10. For input amplitude of 0.5 Vpk to 1.2 Vpk, and 4.14 Vpk to 5.0 V
28 43 - UI
pk
11. For input amplitude of 1.07 Vpk to 4.14 Vpk,
12. For input amplitude of 4.14 V
to 5.0 Vpk,
pk
13. Jitter tolerance increases at lower frequencies. Refer to the Receiver section.
14. Not production tested. Parameters guaranteed by design and characterization.
15. Attenuation measur ed with sinusoidal input jitter equal to 3/4 of measured jitter tolerance.
Circuit attenuates jitter at 20 dB/decade above the corner frequency. Output jitter
can increase significantly when more than 28 UI’s are input to the attenuator. Refer to the
Jitter Attenuator section.
Ω
UI
UI
UI
pk-pk
4 DS172PP5
CS61583
ANALOG SPECIFICATIONS (T
= -40 to 85 °C; power supply pins within ±5% of nominal)
A
Parameter Min Typ Max Units
Transmitter
AMI Output Pulse Amplitudes (Note 16)
E1, 75Ω (Note 17)
E1, 120Ω (Note 18)
T1, DSX-1 (Note 19)
2.14
2.7
2.4
2.37
3.0
3.0
2.6
3.3
3.6
Recommended Transmitter Output Load (Note 16)
T1
E1, 75Ω
E1, 120Ω
Jitter Added During 10 Hz - 8 kHz
Remote Loopback 8 kHz - 40 kHz
10 Hz - 40 kHz
Broad Band (Note 20)
Power in 2 kHz band about 772 kHz (Notes 14 and 21)
(DSX-1 only)
Power in 2 kHz band about 1.544 MHz (Notes 14 and 21))
(referenced to power in 2 kHz band at 772 kHz) (DSX-1 only)
-
-
-
-
-
-
-
76.6
57.4
90.6
0.005
0.008
0.010
0.015
-
-
-
-
-
-
-
12.6 15 17.9 dBm
-29 -38 - dB
Positive to Negative Pulse Imbalance (Notes 14 and 21)
T1, DSX-1
E1, amplitude at center of pulse interval
E1, width at 50% of nominal amplitude
-
-5
-5
0.2
-
-
0.5
+5
+5
Transmitter Return Loss (Notes 14, 21, and 22)
51 kHz - 102 kHz
102 kHz - 2.048 MHz
2.048 MHz - 3.072 MHz
18
14
10
25
18
12
-
-
E1 Short Circuit Current (Note 23) - - 50 mA
E1 and DSX-1 Output Pulse Rise/Fall Times (Note 24) - 25 - ns
E1 Pulse Width (at 50% of peak amplitude) - 244 - ns
E1 Pulse Amplitude E1, 75Ω
for a space E1, 120Ω
-0.237
-0.3
-
-
0.237
0.3
Notes: 16. Using a tr ansformer that meets the specifications in the Applications section.
17. Measur ed across 75 Ω at the output of the transmit transformer for CO N2/1/0 = 0/0/0.
18. Measur ed across 120 Ω at the output of the transmit transformer for CO N2/1/0 = 0/0/1.
19. Measur ed at the DSX-1 cross- connect for line length settings CON2/1/0 = 0/1/0, 0/1/1,
1/0/0, 1/0/1, and 1/1/0 after the appropriate length of #22 ABA M cable specified in Table 1.
20. Input s ignal to RTIP/RRING is jitter free. Values will reduc e slightly if jitter free c lock is input to TCLK.
21. Ty pical performance using the line interface circuitry recommended in the Applications section.
22. Return loss = 20 log
=cable impedance.
z
0
ABS((z1+z0)/(z1-z0)) where z1=impedance of the transmitter or receiver, and
10
23. Transfor mer secondary shorted with 0.5 Ω resistor during the transmission of 100% ones.
24. At trans former secondary and measured from 10% to 90% of amplitude.
V
V
V
Ω
Ω
Ω
UI
UI
UI
UI
dB
%
%
dB
dB
dB
rms
V
V
DS172PP5 5
CS61583
SWITCHING CHARACTERISTICS - T1 CLOCK/DATA (T
= -40 to 85 °C; power supply
A
pins within ±5% of nominal; Inputs: Logic 0 = 0V, Logic 1 = DV+) (See Figures 1, 2, and 3)
Parameter Symbol Min Typ Max Units
TCLK Frequency (Note 25) f
TCLK Duty Cycle t
RCLK Duty Cycle (Note 26) t
pwh2/tpw2
pwh1/tpw1
Rise Time (All Digital Outputs) (Note 27) t
Fall Time (All Digital Outputs) (Note 27) t
RPOS/RNEG (RDATA) to RCLK Rising Setup Time t
RCLK Rising to RPOS/RNEG (RDATA) Hold Time t
TPOS/TNEG (TDATA) to TCLK Falling Setup Time t
TCLK Falling to TPOS/TNEG (TDATA) Hold Time t
tclk
r
f
su1
h1
su2
h2
- 1.544 - MHz
30 50 70 %
45 50 55 %
- - 65 ns
- - 65 ns
- 274 - ns
- 274 - ns
25 - - ns
25 - - ns
Notes: 25. The maximum burst rate of a gapped TCLK input clock is 8.192 MHz. For the gapped clock to be
tolerated by the CS61583, the jitter attenuator must be switched to the transmit path of the line
interface. The maximum gap size that can be tolerated on TCLK is 28 UIp-p.
26. RCLK duty cycle may be outside the specified limits when the jitter attenuator is in the r eceive path,
and when the jitter attenuator is employing the overflow/underflow protection mec hanism.
27. At max load of 50 pF.
SWITCHING CHARACTERISTICS - E1 CLOCK/DATA (T
= -40 to 85 °C; power supply
A
pins within ±5% of nominal; Inputs: Logic 0 = 0V, Logic 1 = DV+) (See Figures 1, 2, and 3)
Parameter Symbol Min Typ Max Units
TCLK Frequency (Note 25) f
TCLK Duty Cycle t
RCLK Duty Cycle (Note 26) t
pwh2/tpw2
pwh1/tpw1
Rise Time (All Digital Outputs) (Note 27) t
Fall Time (All Digital Outputs) (Note 27) t
RPOS/RNEG (RDATA) to RCLK Rising Setup Time t
RCLK Rising to RPOS/RNEG (RDATA) Hold Time t
TPOS/TNEG (TDATA) to TCLK Falling Setup Time t
TCLK Falling to TPOS/TNEG (TDATA) Hold Time t
tclk
r
f
su1
h1
su2
h2
- 2.048 - MHz
30 50 70 %
45 50 55 %
- - 65 ns
- - 65 ns
- 194 - ns
- 194 - ns
25 - - ns
25 - - ns
6 DS172PP5
CS61583
RCLK
(CLKE = 1)
RPOS
RNEG
RDATA
BPV
Any Digital Output
Figure 1. Signal Rise and Fall Characteristics
t
pwl1
t
su1
t
r
90% 90%
10% 10%
t
pw1
t
pwh1
t
h1
t
f
RCLK
(CLKE =0)
Figure 2. Recovered Clock and Data Sw itching Characterist ics
t
pw2
t
pwh2
TCLK
t
TPOS
TNEG
TDATA
Figure 3. Transmit Clock and Data Switching Characteristics
DS172PP5 7
su2
t
h2
CS61583
SWITCHING CHARACTERISTICS - JTAG
TV+, RV+ = nominal ±0.3V; Inputs: Logic 0 = 0V, Logic 1 = RV+) (See Figure 4)
Parameter Symbol Min Typ Max Units
Cycle Time t
J-TMS/J-TDI to J-TCK rising setup time t
J-TCK rising to J-TMS/J-TDI hold time t
J-TCK falling to J-TDO valid t
(TA = - 40 ° to 85 ° C;
200 - - ns
50 - - ns
50 - - ns
- - 50 ns
t
cyc
su
h
dv
cyc
J-TCK
t
su
t
h
J-TMS
J-TDI
J-TDO
t
dv
Figure 4. JAG Switching Characte ristics
8 DS172PP5
CS61583
OVERVIEW
The CS61583 is a dual line interface for T1/E1
applications, designed for high-volume cards
where low power and high density are required.
One board design can support all T1/E1 shorthaul modes by only changing component values
in the receive and transmit paths (if REFCLK
and TCLK are externally tied together). Figure 5
illustrates applications of the CS61583 in various
environments.
All control of the device is achieved via external
pins, eliminating the need for microprocessor
LOOP TIMED APPLICATION
CS62180B
FRAMER
TPOS
TNEG
TCLK
RCLK
RPOS
RNEG
REFCLK
JITTER
ATTENUATOR
CS61583
support. The following pin control options are
available on a per channel basis: line length selection, coder mode, jitter attenuator location,
transmit all ones, local loopback, and remote
loopback.
The line driver generates waveforms compatible
with E1 (CCITT G.703), T1 short haul (DSX-1),
and T1 FCC Part 68 Option A (DS1). A single
transformer turns ratio is used for all waveform
types. The driver internally matches the impedance of the load, providing excellent return loss
to insure superior T1/E1 pulse quality. An addi-
LINE D R IV ER
LINE RECEIVER
TTIP
TRING
RTIP
RRING
TRANSMIT
CIRCUITRY
RECEIVE
CIRCUITRY
MUX
CS62180B
FRAMER
TDATA
TCLK
(gapped)
RCLK
RDATA
TCLK
TPOS
TNEG
RCLK
RPOS
RNEG
ASYNCHRONOU S MU X APPLICATION
(i.e., VT1 .5 c ard f or S O NET o r S DH mu x)
REFCLK
AMI
B8ZS,
HDB3,
CODER
REFCLK
ATTENUATOR
ATTENUATOR
(Including 62411 system s w ith m u ltiple T1 lines)
JITTER
CS61583
JITTER
AIS
DETECT
SYNCHRONOUS A PPLICATION
LINE DRIVER
LINE RECEIVER
CS61583
LINE D R IV ER
LINE RECEIVER
Figure 5. Examples of CS61583 A pplications
TTIP
TRING
RTIP
RRING
TTIP
TRING
RTIP
RRING
TRANSMIT
CIRCUITRY
RECEIVE
CIRCUITRY
TRANSMIT
CIRCUITRY
RECEIVE
CIRCUITRY
DS172PP5 9
CS61583
tional benefit of the internal impedance matching
is a 50 percent reduction in power consumption
compared to implementing return loss using external resistors that causes the transmitter to
drive the equivalent of two line loads.
The line receiver contains all the necessary clock
and data recovery circuits.
The jitter attenuator meets AT&T 62411 requirements when using a 1X or 8X reference clock
supplied by either a crystal oscillator or external
reference at the REFCLK input pin.
AT&T 62411 Customer Premises Application
The AT&T 62411 specification applies to the T1
interface between the customer premises and the
carrier, and must be implemented by the customer premises equipment in order to connect to
the AT&T network.
In 62411 applications, the management of jitter
is a very important design consideration. Typically, the jitter attenuator is placed in the receive
path of the CS61583 to reduce the jitter input to
the system synchronizer. The jitter attenuated recovered clock is used as the input to the transmit
clock to implement a loop-timed system. A Stra-
tum 4 (±32 ppm) quality clock or better should
be input to REFCLK. Note that any jitter present
on the reference clock will not be filtered by the
jitter attenuator.
not usually required in asynchronous multiplexers, the B8ZS/AMI/HDB3 coders in the
CS61583 are activated to provide data interfaces
on TDATA and RDATA.
Synchronous Application
A typical example of a synchronous application
is a T1 card in a central office switch or a 0/1
digital cross-connect system. These systems
place the jitter attenuator in the receive path to
reduce the jitter presented to the system. A Stratum 3 or better system clock is input to the
CS61583 transmit and reference clocks.
TRANSMITTER
The transmitter accepts data from a T1 or E1
system and outputs pulses of appropriate shape
to the line. The transmit clock (TCLK) and
transmit data (TPOS & TNEG, or TDATA) are
supplied synchronously. Data is sampled on the
falling edge of the TCLK input.
The configuration pins CON[2:0] control transmitted pulse shapes, transmitter source
impedance, and receiver slicing level as shown in
Table 1. Typical output pulses are shown in Figures
6 and 7. These pulse shapes are fully pre-defined
by circuitry in the CS61583, and are fully compliant with appropriate standards when used with our
application guidelines in standard installations.
Both channels must be operated at the same line rate
(both T1 or both E1).
Asynchronous Multiplexer Application
Note that the pulse width for Part 68 Option A
Asynchronous multiplexers accept multiple
T1/E1 lines (which are asynchronous to each
other), and combine them into a higher speed
transmission rate (e.g. M13 muxes and SONET
(324 ns) is narrower than the optimal pulse
width for DSX-1 (350 ns). The CS61583 automatically adjusts the pulse width based on the
configuration selection.
muxes). In these systems, the jitter attenuator is
placed in the transmit path of the CS61583 to
remove the gapped clock jitter input by the multiplexer to TCLK. Because the transmit clock is
jittered, the reference clock to the CS61583 is
provided by an external source operating at 1X
or 8X the data rate. Because T1/E1 framers are
10 DS172PP5
The transmitter impedance changes with the line
length options in order to match the load imped-
ance (75Ω for E1 coax, 100Ω for T1, 120Ω for
E1 shielded twisted pair), providing a minimum
of 14 dB return loss for T1 and E1 frequencies
CS61583
NORMALIZED
AMPLITUDE
1.0
ANSI T1.102
SPECIFICATION
0.5
0
CS61583
OUTPUT
PULSE SHAPE
-0.5
0 250 750 1000
500
TIME (nanoseconds)
Figure 6. Typical Pulse Shape at DSX-1 Cross Connect
during the transmission of both marks and
spaces. This improves signal quality by minimizing reflections from the transmitter. Impedance
matching also reduces load power consumption
by a factor of two when compared to the return
loss achieved by using external resistors.
The CS61583 driver will automatically detect an
inactive TLCK input (i.e., no valid data is being
clocked to the driver). When this condition is detected, the driver is forced low (except during
remote loopback) to output spaces and prevent
TTIP and TRING from entering a constant transmit-mark state.
Percent of
nominal
peak
voltage
120
110
100
90
80
50
10
0
-10
-20
269 ns
244 ns
194 ns
219 ns
488 ns
G.703
Specification
Nominal Pulse
Figure 7. Pulse Mask at the 2048 kbps Interface
When any transmit configuration established by
CON[2:0], TAOS, or LLOOP changed states, the
transmitter stabilizes within 22 TCLK bit periods. The transmitter takes longer to stabilize
when RLOOP1 or RLOOP2 is selected because
the timing circuitry must adjust to the new frequency from RCLK.
When the transmitter transformer secondaries are
shorted through a 0.5 ohm resistor, the transmit-
C
C
C
Transmit Pulse
O
O
O
Width at 50%
N
N
N
2
1
0
Amplitude
000001244 ns (50%)
244 ns (50%)
Transmit Pulse Shape
E1: square, 2.37 Volts into 75
E1: square, 3.00 Volts into 120
Ω
Ω
Receiver
Slicing
Level
50%
50%
0 1 0 350 ns (54%) DSX-1: 0-133 ft. / or DS1 FCC Part 68 Option A with undershoot 65%
0 1 1 350 ns (54%) DSX-1: 133-266 ft. 65%
1 0 0 350 ns (54%) DSX-1: 266-399 ft. 65%
1 0 1 350 ns (54%) DSX-1: 399-533 ft. 65%
1 1 0 350 ns (54%) DSX-1: 533-655 ft. 65%
1 1 1 324 ns (50%) DS1: FCC Part 68 Option A (0 dB) 65%
Table 1. Configuration Selection
DS172PP5 11
CS61583
ter will output a maximum of 50 mA-rms, as required by European specification BS6450.
RECEIVER
The receiver extracts data and clock from the
T1/E1 signal on the line interface and outputs
clock and synchronized data to the system. The
signal is detected differentially across the receive
transformer and can be recovered over the entire
range of short haul cable lengths. The transmit
and receive transfomer specifications are identical
and are presented in the Applications section.
As shown in Table 1, the receiver slicing level is
set at 65% for DS1/DSX-1 short-haul and at
50% for all other applications.
The clock recovery circuit is a second-order
phase locked loop that can tolerate up to 0.4 UI
of jitter from 10 kHz to 100 kHz without generating errors (Figure 8). The clock and data
recovery circuit is tolerant of long strings of consecutive zeros and will successfully recover a
1-in-175 jitter-free line input signal.
Recovered data at RPOS and RNEG (or
RDATA) is stable and may be sampled using the
recovered clock RCLK. The CLKE input determines the clock polarity for which output data is
stable and valid as shown in Table 2. When
CS61583
300
138
100
PEAK-TO-PEAK
JITTER
(unit intervals)
Figure 8. Minimum Input Jitter Tolerance of Receiver
28
10
.4
.1
(Clock Recovery Circuit and Jitter Attenuator)
1
AT&T 62411
(1990 Version)
Performance
10 1k 10k1 100 100k700
300
JITTER FREQUENCY (Hz)
CLKE is low, RPOS and RNEG (or RDATA) are
valid on the rising edge of RCLK. When CLKE
is high, RPOS and RNEG (or RDATA) are valid
on the falling edge of RCLK.
CLKE DATA CLOCK Clock Edge
for Valid Data
LOW RPOS, RNEG
or RDATA
HIGH RPOS, RNEG
or RDATA
Table 2. Re covere d Data /Cloc k Optio ns
RCLK
RCLK
RCLK
RCLK
Rising
Rising
Falling
Falling
JITTER ATTENUATOR
The jitter attenuator can be switched into either
the receive or transmit paths. Alternatively, it can
also be removed from both paths to reduce the
propagation delay.
The location of the attenuators for both channels
is controlled by the ATTEN0 and ATTEN1 pins.
Table 3 shows how these pins are decoded.
ATTEN1 ATTEN0 Locatio n of
Jitter Attenuator
00 Receiver
0 1 Disabled
1 0 Transmitter
11 Reserved
Table 3. Jitter Attenuation Control
The attenuator consists of a 64-bit FIFO, a narrow-band monolithic PLL, and control logic.
Signal jitter is absorbed in the FIFO which is designed to neither overflow nor underflow. If
overflow or underflow is imminent, the jitter
transfer function is altered to insure that no biterrors occur. Under this condition, jitter gain
may occur and jitter should be attenuated externally in a frame buffer. The jitter attenuator will
typically tolerate 43 UIs before the overflow/underflow mechanism occurs. If the jitter
attenuator has not had time to "lock" to the aver-
12 DS172PP5
CS61583
age incoming frequency (e.g. following a device
reset) the attenuator will tolerate a minimum of
22 UIs before the overflow/underflow mechanism occurs.
For T1/E1 line cards used in high-speed mutiplexers (e.g., SONET and SDH), the jitter
attenuator is typically used in the transmit path.
The attenuator can accept a transmit clock with
gaps ≤ 28 UIs and a transmit clock burst rate of
≤ 8 MHz.
When the jitter attenuator is in th e receive path and
loss of signal occurs, the frequency of the last recovered signal is held. When the jitter attenuator is
not in the receive path, the last recovered frequency
is not held and the output frequency becomes the
frequency of the reference clock.
A typical jitter attenuation curve is shown in Figure 9.
jittered transmit clock, the reference clock
should not be tied to the transmit clock and a
separate external oscillator should drive the reference clock input. Any jitter present on the
reference clock will not be filtered by the jitter
attenuator.
POWER-UP RESET
On power-up, the device is held in a static state
until the power supply achieves approximately
60% of the power supply voltage. When this
threshold is crossed, the device waits another 10
ms to allow the power supply to reach operating
voltage and then calibrates the transmit and receive circuitry. This initial calibration takes less
than 20 ms but can occur only if REFCLK and
TCLK are present. The power-up reset performs
the same functions as the RESET pin.
LINE CONTROL AND MONITORING
0
10
20
30
b) Maximum
40
Attenuation
Attenuation in dB
Limit
50
60
1 10 100 1 k 10 k
Figure 9. Typical Jitter Transfer Function
a) Minimum Attenuation Limit
62411 (1990 Version)
Requirements
CS61583 Performance
Frequency in Hz
REFERENCE CLOCK
The CS61583 requires a reference clock with a
minimum accuracy of ±100 ppm for T1 and E1
applications. This clock can be either a 1X clock
(i.e., 1.544 MHz or 2.048 MHz), or can be a 8X
clock (i.e., 12.352 MHz or 16.384 MHz) as selected by the 1XCLK pin. In systems with a
Line control and monitoring of the CS61583 is
achieved using the control pins. The controls and
indications available on the CS61583 are detailed below.
Line Code Encoder/Decoder
Coding may be transparent, AMI, B8ZS, or
HDB3 and is selected using the CODER1,
CODER2, AMI1, and AMI2 pins. In the coder
mode, AMI, B8ZS, and HDB3 line codes are
available. The input data to the encoder is on
TDATA and the output data from the decoder is
in NRZ format on RDATA. See Table 4.
CODER[2:1]=0 CODER[2:1]=1
AMI[2:1]=0
Transparent Mode
Enabled
and
AMI[2:1] Pin(s)
Disabled
Table 4. Coder Mode Options
B8ZS/HDB3
Encoder/Decoder
Enabled
AMI[2:1]=1
AMI
Encoder/Decoder
Enabled
DS172PP5 13
CS61583
Alarm Indication Signal
In coder mode, the TNEG pin becomes the
alarm indication signal (AIS) output controlled
by the receiver. The receiver detects the AIS
condition on observation of 99.9% ones density
in a 5.3 ms period (< 9 zeros in 8192 bits) and
sets the AIS pin high. The AIS condition is ex-
ited when ≥ 9 zeros are detected in 8192 bits.
Bipolar Violation Detection
In coder mode, the RNEG pin becomes the bipolar violation (BPV) strobe output controlled by
the receiver. The BPV pin goes high for one
RCLK period when a bipolar violation is detected in the received signal. Note that B8ZS or
HDB3 zero substitutions are not flagged as bipolar violations when the decoder is enabled.
Loss of Signal
The loss of signal (LOS) indication is detected
by the receiver and reported when the LOS pin
is high. Loss of signal is indicated when 175±15
consecutive zeros are received. The LOS condition is exited according to the ANSI
T1.231-1993 criteria that requires 12.5% ones
density over 175±75 bit periods with no more
than 100 consecutive zeros. Note that bit errors
may occur at RPOS and RNEG (or RDATA)
prior to the LOS indication if the analog input
level falls below the receiver sensitivity.
The LOS pin is set high when the device is reset
or in powered up and returns low when data is
recovered by the receiver.
Transmit All Ones
Transmit all ones is selected by setting the
TAOS pin high. Selecting TAOS causes continuous ones to be transmitted to the line interface
on TTIP and TRING at the frequency of
REFCLK. In this mode, the transmit data inputs
TPOS and TNEG (or TDATA) are ignored. A
TAOS overrides the data transmitted to the line
interface during local and remote loopbacks.
Local Loopback
A local loopback is selected by setting the
LLOOP pin high. Selecting LLOOP causes the
TCLK, TPOS, and TNEG (or TDATA) inputs to
be looped back through the jitter attenuator (if
enabled) to the RCLK, RPOS, and RNEG (or
RDATA) outputs. Data received at the li ne interface is ignored, but data at TPOS and TNEG (or
TDATA) continues to be transmitted to the line
interface at TTIP and TRING.
A TAOS request overrides the data transmitted to
the line interface during local loopback. Note
that simultaneous selection of local and remote
loopback modes is not valid.
Remote Loopback
A remote loopback is selected by setting the
RLOOP pin high. Selecting RLOOP causes the
data received from the line interface at RTIP and
RRING to be looped back through the jitter attenuator (if enabled) and retransmitted on TTIP
and TRING. Data transmitted at TPOS and
TNEG (or TDATA) is ignored, but data recovered from RTIP and RRING continues to be
transmitted on RPOS and RNEG (or RDATA).
Remote loopback is functional if TCLK is absent. A TAOS request overrides the data
transmitted to the line interface during a remote
loopback. Note that simultaneous selection of local and remote loopback modes is not valid.
Reset Pin
The CS61583 is continuously calibrated during
operation to insure the performance of the device
over power supply and temperature. The continuous calibration function eliminates the need
to reset the line interface during operation.
A device reset may be selected by setting the
RESET pin high for a minimum of 200 ns. The
reset function initiates on the falling edge of RESET and takes less than 20 ms to complete. The
control logic is initialized and the transmit and
14 DS172PP5
CS61583
receive circuitry is calibrated if REFCLK and
TCLK are present.
JTAG BOUNDARY SCAN
Board testing is supported through JTAG boundary scan. Using boundary scan, the integrity of
the digital paths between devices on a circuit
board can be verified. This verification is supported by the ability to externally set the signals
on the digital output pins of the CS61583, and to
externally read the signals present on the input
pins of the CS61583. Additionally, the manufacturer ID, part number and revision of the
CS61583 can be read during board test using
JTAG boundary scan.
As shown in Figure 10, the JTAG hardware consists of data and instruction registers plus a Test
Access Port (TAP ) controller. Control of the TAP
is achieved through signals applied to the Test
Mode Select (J-TMS) and Test Clock ( J-TCK)
input pins. Data is shifted into the registers via
the Test Data Input (J-TDI) pin, and shifted out
of the registers via the Test Data Output (J-TDO)
pin. Both J-TDI and J-TDO are clocked at a rate
determined by J-TCK. The Instruction register
defines which data register is accessed in the
shift operation. Note that if J-TDI is floating,
an internal pull-up resistor forces the pin high.
JTAG Data Registers (DR)
The test data registers are the Boundary-Scan
Register (BSR), the Device Identification Register (DIR), and the Bypass Register (BR).
Boundary Scan Register: The BSR is connected
in parallel to all the digital I/O pins, and provides the mechanism for applying/reading test
patterns to/from the board traces. The BSR is 67
bits long and is initialized and read using the instruction SAMPLE/PRELOAD. The bit ordering
for the BSR is the same as the top-view package
pin out, beginning with the LOS1 pin and moving counter-clockwise to end with the CODER1
pin as shown in Table 5. Note that the analog,
oscillator, power, ground, CLKE, and ATTEN0
pins are not included as part of the boundaryscan register.
The input pins require one bit in the BSR and
only one J-TCK cycle is required to load test
data for each input pin.
The output pins have two bits in the BSR to define output high, output low, or high impedance.
Digital output pins Digital i nput pins
parallel latched
output
Boundary Sc an D at a Reg i st er
Device ID Data Register
J-TDI
Bypass Data Register
J-TCK
J-TMS
Figure 10. Block Diagram of JTAG Circuitry
DS172PP5 15
Instructi on (shift) Register
parallel latched
output
TAP
Controller
JTAG Block
MUX
J-TDO
CS61583
The first bit (shifted in first) selects between an
output-enabled state (bit set to 1) or high-impedance state (bit set to 0). The second bit shifted in
contains the test data that may be output on the
pin. Therefore, two J-TCK cycles are required to
load test data for each output pin.
BSR bits Pin Name Pad Type
0-2 LOS1 bi-direc tional
3-5 TNEG1/AIS1 bi-dir ectional
6 TPOS1/TDATA1 input
7 TCLK1 input
8-9 RNEG1/BP V1 output
10-11 RPOS1/RDATA1 output
12-13 RCLK1 output
14-16 ATTEN1 bi-directional
17-19 RLOOP1 bi-directional
20 LLOOP 1 input
21-23 LLOOP2 bi-directional
24-26 TAOS1 bi-directional
27-29 TAOS2 bi-directional
30-32 CO N01 bi-directional
33-35 CO N02 bi-directional
36-38 CON11 bi-directional
39-41 CO N12 bi-directional
42-44 CO N21 bi-directional
45 CON22 input
46-48 AMI1 bi-directional
49-50 RCLK2 output
51-52 RPOS2/RDATA2 output
53-54 RNEG2/BPV2 output
55 TCLK2 input
56 TPOS2/TDATA2 input
57-59 TNEG2/AIS2 bi-directional
60-62 LOS2 bi-directional
63 AMI2 input
64 CODER2 input
65 RLOOP2 input
66 CODER1 input
1. Configure pad as an input.
2. Configure pad as an output.
2
1
1
1
1
1
1
1
1
1
1
1
2
The bi-directional pins have three bits in the
BSR to define input, output high, output low, or
high impedance. The first bit shifted into the
BSR configures the output driver as high-impedance (bit set to 0) or active (bit set to 1). The
second bit shifted into the BSR sets the output
value when the first bit is 1. The third bit captures the value of the pin. This pin may have its
value set externally as an input (if the first bit is
0) or set internally as an output (if the first bit is
1). To configure a pad as an input, the J-TDI
pattern is 0X0. To configure a pad as an output,
the J-TDI pattern is 1X1. Therefore, three J-TCK
cycles are required to load test data for each bidirectional pin.
Device Identification Register: The DIR provides
the manufacturer, part number, and version of the
CS61583. This information can be used to verify
that the proper version or revision number has
been used in the system under test. The DIR is 32
bits long and is partitioned as shown in figure 11.
MSB LSB
31 28 27 1211 1 0
00000000000000000011000011001001
(4 bits) (16 bits) (11 bits)
BIT #(s) FUNCTION Total Bits
31-28 Version number 4
27-12 Part Number 16
11- 1 Manufacturer Number 11
0 Constant Logic ’1’ 1
Figure 11. Device Identification Register
Data from the DIR is shifted out to J-TDO LSB
first.
Bypass Register: The Bypass register consists of
a single bit, and provides a serial path between
J-TDI and J-TDO, bypassing the BSR. This allows bypassing specific devices during certain
board-level tests. This also reduces test access
times by reducing the total number of shifts required from J-TDI to J-TDO.
Table 5. Boundary Scan Register
16 DS172PP5
CS61583
JTAG Instructions and Instruction Register (IR)
The instruction register (2 bits) allows the instruction to be shifted into the JTAG circuit. The
instruction selects the test to be performed or the
data register to be accessed or both. The valid
instructions are shifted in LS B first and are listed
below:
IR CODE INSTRUCTION
00 EX TEST
01 SA MPLE/PRELOAD
10 IDCODE
11 BYPASS
EXTEST Instruction: The EXTEST instruction
allows testing of off-chip circuitry and boardlevel interconnect. EXTEST connects the BSR to
the J-TDI and J-TDO pins. The normal path between the CS61583 logic and I/O pins is broken.
The signals on the output pins are loaded from
the BSR and the signals on the input pins are
loaded into the BSR.
SAMPLE/PRELOAD Instruction: The SAMPLE/PRELOAD instructions allows scanning of
the boundary-scan register without interfering
with the operation of the CS61583. This instruction connects the BSR to the J-TDI and J-TDO
pins. The normal path between the CS61583
logic and its I/O pins is maintained. The signals
on the I/O pins are loaded into the BSR. Additionally, this instruction can be used to latch
values into the digital output pins.
Internal Testing Considerations
Note that the INTEST instruction is not supported because of the difficulty in performing
significant internal tests using JTAG.
The one test that could be easily performed using an arbitrary clock rate on TCLK and
REFCLK is a local loopback with jitter attenuator disabled. However, this test provides limited
fault coverage and is only useful in determining
if the device had been catastrophically destroyed.
Alternatively, catastrophic destruction of the device and/or surrounding board traces can be
detected using EXTEST. Therefore, the INTEST
instruction provides limited testing capability
and was not included in the CS61583.
JTAG TAP Controller
Figure 12 shows the state diagram for the TAP
state machine. A description of each state follows. Note that the figure contains two main
branches to access either the data or instruction
registers. The value shown next to each state
transition in this figure is the value present at
J-TMS at each rising edge of J-TCK.
Test-Logic-Reset State
In this state, the test logic is disabled to continue
normal operation of the device. During initialization, the CS61583 initializes the instruction
register with the IDCODE instruction.
IDCODE Instruction: The IDCODE instruction
connects the device identification register to the
J-TDO pin. The IDCODE instruction is forced
into the instruction register during the TestLogic-Reset controller state.The default
instruction is IDCODE after a device reset.
Regardless of the original state of the cont roller,
the controller enters the Test-Logic-Reset state
when the J-TMS input is held high for at least
five rising edges of J-TCK. The controller remains in this state while J-TMS is high. The
CS61583 processor automatically enters this
state at power-up.
BYPASS Instruction: The BYPASS instruction
connects the minimum length bypass register between the J-TDI and J-TDO pins and allows data
to be shifted in the Shift-DR controll er state.
Run-Test/Idle State
This is a controller state between scan operations. Once in this state, the controller remains
in the state as long as J-TMS is held low. The
DS172PP5 17
CS61583
instruction register and all test data registers retain their previous state. When J-TMS is high
and a rising edge is applied to J-TCK, the controller moves to the Select-DR state.
Select-DR-Scan State
This is a temporary controller state. The test
data register selected by the current instruction
retains its previous state. If J-TMS is held low
and a rising edge is applied to J-TCK when in
this state, the controller moves into t he CaptureDR state and a scan sequence for the selected
test data register is initiated. If J-TMS is held
high and a rising edge applied to J-TCK, the
controller moves to the Select-IR-Scan state.
The instruction does not change in this state.
Capture-DR State
In this state, the Boundary Scan Register captures input pin data if the current instruction is
EXTEST or SAMPLE/PRELOAD. The other
test data registers, which do not have parallel input, are not changed.
The instruction does not change in this state.
When the TAP controller is in this state and a
rising edge is applied to J-TCK, the controller
enters the Exit1-DR state if J-TMS is high or the
Shift-DR state if J-T MS is low.
Shift-DR State
In this controller state, the test data register connected between J-TDI and J-TDO as a result of
the current instruction shifts data on stage toward its serial output on each rising edge of
J-TCK.
The instruction does not change in this state.
When the TAP controller is in this state and a
rising edge is applied to J-TCK, the controller
enters the Exit1-DR state if J-TMS is high or remains in the Shift-DR state if J-TMS is low.
Exit1-DR State
This is a temporary state. While in t his state, if
J-TMS is held high, a rising edge applied to JTCK causes the controller to enter the
Update-DR state, which terminates the scanning
process. If J-TMS is held low and a rising edge
is applied to J-TCK, the controller enters the
Pause-DR state.
Test-Logic-Reset
1
0
0
Run-Test/Idle
1
Select-DR-Scan
1
0
10
0
Capture-DR
0
Shift-DR
1
Exit1-DR
0
Pause-DR
1
Exit2-DR
1
Update-DR
1
0
1
0
Select-IR-Scan
1
0
10
0
Capture-IR
0
Shift- IR
1
Exit1-IR
0
Pause-IR
1
Exit2-IR
1
Update-IR
1
0
1
0
Figure 12. TAP Controller State Diagram
18 DS172PP5
CS61583
The test data register selected by the current instruction retains its previous value during this
state. The instruction does not change in this
state.
Pause-DR State
The pause state allows the test controller to temporarily halt the shifting of data through the test
data regist er in the serial path between J-TDI and
J-TDO. For example, this state could be used to
allow the tester to reload its pin memory from
disk during application of a long test sequence.
The test data register selected by the current instruction retains its previous value during this
state. The instruction does not change in this
state.
The controller remains in this state as long as
J-TMS is low. When J-TMS goes high and a
rising edge is applied to J-TCK, the controller
moves to the Exit2-DR state.
parallel output of this register from the shift-register path on the falling edge of J-TCK. The
data held at the latched parallel output changes
only in this state.
All shift-register stages in the test data register
selected by the current instruction retains their
previous value during this state. The instructions
does not change in this state.
Select-IR-Scan State
This is a temporary controller state. The test
data register selected by the current instruction
retains its previous state. If J-TMS is held low
and a rising edge is applied to J-TCK when in
this state, the controller moves into t he CaptureIR state, and a scan sequence for the instruction
register is initiated. If J-TMS is held high and a
rising edge is applied to J-TCK, the controller
moves to the Test-Logic-Reset state. The instruction does not change in this state.
Exit2-DR State
This is a temporary state. While in t his state, if
J-TMS is held high, a rising edge applied to JTCK causes the controller to enter the
Update-DR state, which terminates the scanning
process. If J-TMS is held low and a rising edge
is applied to J-TCK, the controller enters the
Shift-DR state.
The test data register selected by the current instruction retains its previous value during this
state. The instruction does not change in this
state.
Update-DR State
The Boundary Scan Register is provided with a
latched parallel output to prevent changes while
data is shifted in response to the EXTEST and
SAMPLE/PRELOAD instructions. When the
TAP controller is in this state and the Boundary
Scan Register is selected, data is latched into the
Capture-IR State
In this controller state, the shift register contained in the instruction register loads a fixed
value of "01" on the rising edge of J-TCK. This
supports fault-isolation of the board-level serial
test data path.
Data registers selected by the current instruction
retain their value during this state. The instructions does not change in this state.
When the controller is in this state and a rising
edge is applied to J-TCK, the controller enters
the Exit1-IR state if J-TMS is held high, or the
Shift-IR state if J-TMS is held low.
Shift-IR State
In this state, the shift register contained in the
instruction register is connected between J-TDI
and J-TDO and shifts data one stage towards its
serial output on each rising edge of J-TCK.
DS172PP5 19
CS61583
The test data register selected by the current instruction retains its previous value during this
state. The instruction does not change in this
state.
When the controller is in this state and a rising
edge is applied to J-TCK, the controller enters
the Exit1-IR state if J-TMS is held high, or remains in the Shift-IR state if J-TMS is held low.
Exit1-IR State
This is a temporary state. While in t his state, if
J-TMS is held high, a rising edge applied to JTCK causes the controller to enter the Updat e-IR
state, which terminates the scanning process. If
J-TMS is held low and a rising edge is applied
to J-TCK, the controller enters the Pause-IR
state.
The test data register selected by the current instruction retains its previous value during this state.
The instruction does not change in this state.
J-TMS is held low and a rising edge is applied
to J-TCK, the controller enters the Shift-IR state.
The test data register selected by the current instruction retains its previous value during this
state. The instruction does not change in this
state.
Update-IR State
The instruction shifted into the instruction register is latched into the parallel output from the
shift-register path on the falling edge of J-TCK.
When the new instruction has been latched, it
becomes the current instruction.
Test data registers selected by the current instruction retain their previous value.
JTAG Application Examples
Figures 13 and 14 illustrate examples of updating the instruction and data registers during
JTAG operation.
Pause-IR State
The pause state allows the test controller to temporarily halt the shifting of data through the
instruction register.
The test data register selected by the current instruction retains its previous value during this
state. The instruction does not change in this
state.
The controller remains in this state as long as
J-TMS is low. When J-TMS goes high and a
rising edge is applied to J-TCK, the controller
moves to the Exit2-IR state.
Exit2-IR State
This is a temporary state. While in t his state, if
J-TMS is held high, a rising edge applied to JTCK causes the controller to enter the Updat e-IR
state, which terminates the scanning process. If
20 DS172PP5
TCK
TMS
Controller state
TDI
Parallel Input to IR
IR shift-register
Test-Logic-Reset
CS61583
Shift-IR
Exit1-IR
Select-DR-Scan
Select-IR-Scan
Capture-IR
Run-Test/Idle
Pouse-IR
Exit2-IR
Shift-IR
Exit1-IR
Update-IR
Run-Test/Idle
Parallel out put of IR
Parallel I n put t o TDR
Parallel output of TDR
TDR shift-register
Register selecte d
TDO enable
TDO
IDCODE New Instruction
Old data
Instruction register
Inactive ActiveInactive Inactive
Act
= Don't care or undef i ned
Figure 13. JTAG Instruction Register Update
DS172PP5 21
TCK
TMS
Controller state
TDI
Parallel Input to IR
IR shift- regi s te r
CS61583
Shift-DR
Exit1-DR
Run-Test/Idle
Select-DR-Scan
Capture-DR
Pouse-DR
Exit2-DR
Shift-DR
Exit1-DR
Update-DR
Run-Test/Idle
Select-DR-Scan
Select-IR-Scan
Test-Logic-Reset
Parallel output of IR
Parallel Input to TDR
TDR shift-register
Parallel output of TDR
Register Selected
TDO enable
TDO
Inactive ActiveInactive InactiveActive
= Don't care or undefined
Figure 14. JTAG Data Register Update
Old data
IDCODEInstruction
New data
Test data register
22 DS172PP5
PIN DESCRIPTIONS
DGND1
CON01
TAOS2
TAOS1
LLOOP2
LLOOP1
RLOOP1
ATTEN1
not used
RCLK1
RPOS1/RDATA1
RNEG1/BPV1
TCLK1
TPOS1/TDATA1
TNEG1/AIS1
LOS1
J-TDO
DGND2
J-TDI
TTIP1
TV+1
TGND1
TRING1
CODER1
ATTEN0
not used
RTIP1
RRING1
RV+1
RGND1
AGND1
BGREF
AGND2
AV+
11
13
15
17
19
21
23
25
13579 67656361
CS61583
68-Pin PLCC
Top View
3533312927 37 39 41 43
59
57
55
53
51
49
47
45
CS61583
DV+
DGND3
CON02
CON11
CON12
CON21
CON22
AMI1
not used
RCLK2
RPOS2/RDATA2
RNEG2/BPV2
TCLK2
TPOS2/TDATA2
TNEG2/AIS2
LOS2
AMI2
J-TCK
J-TMS
TTIP2
TV+2
TGND2
TRING2
CODER2
CLKE
not used
RTIP2
RRING2
RV+2
RGND2
1XCLK
RLOOP2
REFCLK
RESET
Note: Pins labeled as "not used" should be tied to ground.
DS172PP5 23
CS61583
DGND1
CON01
TAOS2
TAOS1
LLOOP2
LLOOP1
RLOOP1
ATTEN1
RCLK1
RPOS1/RDATA1
RNEG1/BPV1
TCLK1
TPOS1/TDATA1
TNEG1/AIS1
LOS1
J-TDO
DGND2
J-TDI
TTIP1
TV+1
TGND1
TRING1
CODER1
ATTEN0
RTIP1
RRING1
RV+1
RGND1
AGND1
BGREF
AGND2
AV+
64 62 60 58 56 54 52 50
1
2
4
6
8
10
12
14
16
18 20 22 24 26 28 30 32
CS61583
64-Pin TQFP
Top View
48
46
44
42
40
38
36
34
DV+
DGND3
CON02
CON11
CON12
CON21
CON22
AMI1
RCLK2
RPOS2/RDATA2
RNEG2/BPV2
TCLK2
TPOS2/TDATA2
TNEG2/AIS2
LOS2
AMI2
J-TCK
J-TMS
TTIP2
TV+2
TGND2
TRING2
CODER2
CLKE
RTIP2
RRING2
RV+2
RGND2
1XCLK
RLOOP2
REFCLK
RESET
24 DS172PP5
CS61583
Power Supplies
AGND1, AGND2 : Analog Ground (PLCC pins 31, 33; TQFP pins 21, 23)
Analog supply ground pins.
AV+ : Analog Power Supply (PLCC pin 34; TQFP pin 24)
Analog supply pin for the internal bandgap reference and timing generation circuits.
BGREF : Bandgap Reference (PLCC pin 32; TQFP pin 22)
This pin is used by the internal bandgap reference and must be connected to ground
by a 4.99kΩ ±1% resistor to provide an internal current reference.
DGND1, DGND2, DGND3 : Digital Ground (PLCC pins 1, 18, 67; TQFP pins 57, 9, 55)
Power supply ground pins for the digital circuitry of both channels.
DV+ : Power Supply (PLCC pin 68; TQFP pin 56)
Power supply pin for the digital circuitry of both channels.
RGND1, RGND2 : Receiver Ground (PLCC pins 30, 39; TQFP pins 20, 29)
Power supply ground pins for the receiver circuitry.
RV+1, RV+2 : Receiver Power Supply (PLCC pins 29, 40; TQFP pins 19, 30)
Power supply pins for the analog receiver circuitry.
TGND1, TGND2 : Transmit Ground (PLCC pins 22, 47; TQFP pins 13, 36)
Power supply ground pins for the transmitter circuitry.
TV+1, TV+2 : Transmit Power Supply (PLCC pins 21, 48; TQFP pins 12, 37)
Power supply pins for the analog transmitter circuitry.
T1/E1 Data
RCLK1, RCLK2 : Receive Clock (PLCC pins 10, 59; TQFP pins 1, 48)
RPOS1, RPOS2 : Receive Positive Data (PLCC pins 11, 58; TQFP pins 2, 47)
RNEG1, RNEG2 : Receive Negative Data (PLCC pins 12, 57; TQFP pins 3, 46)
The receiver recovered clock and NRZ digital data from RTIP and RRING is output on these
pins. The CLKE pin determines the clock edge on which RPOS and RNEG are stable and
valid. A positive pulse (with respect to ground) received on RTIP generates a logic 1 on RPOS,
and a positive pulse received on RRING generates a logic 1 on RNEG.
RDATA1, RDATA2 : Receive Data (PLCC pins 11, 58; TQFP pins 2, 47)
In coder mode (CODER = 1), the decoded digital data stream from RTIP and RRING is output
on RDATA in NRZ format. The CLKE pin determines the clock edge on which RDATA is
stable and valid.
RTIP1, RTIP2 : Receive Tip (PLCC pins 27, 42; TQFP pins 17, 32)
RRING1, RRING2 : Receive Ring (PLCC pins 28, 41; TQFP pins 18, 31)
The receive AMI signal from the line interface is input on these pins. The recovered clock and
data are output on RCLK, RPOS, and RNEG (or RDATA).
DS172PP5 25
TCLK1, TCLK2 : Transmit Clock (PLCC pins 13, 56; TQFP pins 4, 45)
TPOS1, TPOS2 : Transmit Positive Data (PLCC pins 14, 55; TQFP pins 5, 44)
TNEG1, TNEG2 : Transmit Negative Data (PLCC pins 15, 54; TQFP pins 6, 43)
The transmit clock and data are input to these pins. The signal is driven to the line interface at
TTIP and TRING. Data at TPOS and TNEG are sampled on the falling edge of TCLK. An
input at TPOS causes a positive pulse to be transmitted at TTIP and TRING, while an input at
TNEG causes a negative pulse to be transmitted at TTIP and TRING.
TDATA1, TDATA2 : Transmit Positive Data (PLCC pins 14, 55; TQFP pins 5, 44)
In coder mode (CODER = 1), the un-encoded digital data stream is input on TDATA in NRZ
format. Data at TDATA is sampled on the falling edge of TCLK.
TTIP1, TTIP2 : Transmit Tip (PLCC pins 20, 49; TQFP pins 11, 38)
TRING1, TRING2 : Transmit Ring (PLCC pins 23, 46; TQFP pins 14, 35)
The transmit AMI signal to the line interface is output on these pins. The transmit clock and
data are input from TCLK, TPOS, and TNEG (or TDATA).
Oscillator
1XCLK : One-times Clock Frequency Select (PLCC pin 38; TQFP pin 28)
When 1XCLK is set high, REFCLK must be a 1X clock (i.e., 1.544 MHz for T1 or 2.048 MHz
for E1 applications). When 1XCLK is set low, REFCLK must be an 8X clock (i.e., 12.352
MHz for T1 or 16.384 MHz for E1 applications).
CS61583
REFCLK : External Reference Clock Input (PLCC pin 36, TQFP pin 26)
Input reference clock for the receive and jitter attenuator circuits. When 1XCLK is high,
REFCLK must be a 1X clock (i.e., 1.544 MHz ±100 ppm for T1 applications or 2.048 MHz
±100 ppm for E1 applications). When 1XCLK is set low, REFCLK must be an 8X clock (i.e.,
12.352 MHz ±100 ppm for T1 applications or 16.384 MHz ±100 ppm for E1 applications). The
REFCLK input also determines the transmission rate when TAOS is asserted.
Control
AMI1, AMI2 : Encoder/Decoder Select (PLCC pins 61, 52; TQFP pins 49, 41)
Setting AMI low enables the B8ZS or HDB3 zero substitution in the transmitter encoders and
receiver decoders. Setting AMI high enables AMI encoders and decoders. The AMI pins are
enabled by setting the corresponding CODER pin high.
ATTEN0, ATTEN1 : Jitter Attenuator Select (PLCC pins 25, 8; TQFP pins 16, 64)
Selects the jitter attenuation path for both channels (transmi t/receive/neither).
CLKE : Clock Edge (PLCC pin 44; TQFP pin 33)
Controls the polarity of the recovered clock RCLK. When CLKE is high, RPOS and RNEG are
valid on the falling edge of RCLK. When CLKE is low, RPOS and RNEG are valid on the
rising edge of RCLK.
26 DS172PP5
CS61583
CODER1, CODER2 : Coder Mode Configuration (PLCC pins 24, 45; TQFP pins 15, 34)
Setting CODER high causes the Coder Mode to be enabled. In Coder Mode, the transmit and
receive data appears in NRZ format on TDATA and RDATA, respectively. These pins also
enable the corresponding AMI pin.
CON01, CON11, CON21, : Configuration Selection
CON02, CON12, CON22 : (PLCC pins 2, 65, 63, 66, 64, 62; TQFP pins 58, 53, 51, 54, 52, 50)
These pins configure the transmitter (pulse shape, pulse width, pulse amplitude, and driver
impedance) receiver (slicing level), and coder (HDB3 vs B8ZS). The CONx1 pins control
channel 1 and the CONx2 pins control channel 2. Both channels must be configured to operate
at the same data rate on the line interface (both T1 or both E1).
LLOOP1, LLOOP2 : Local Loopback (PLCC pins 6, 5; TQFP pins 62, 61)
A local loopback is enabled when LLOOP is high. During local loopback, the TCLK,
TPOS/TNEG (or TDATA) inputs are looped back through the jitter attenuator (if enabled) to the
RCLK, RPOS/RNEG (or RDATA) outputs. The data at TPOS/TNEG continues to be
transmitted to the line interface unless overridden by a TAOS request. The inputs at RTIP and
RRING are ignored.
RESET : Reset (PLCC pin 35; TQFP pin 25)
A device reset is selected by setting the RESET pin high for a minimum of 200 ns. The reset
function initiates on the falling edge of RESET and requires less than 20 ms to complete. The
control logic is initialized and LOS is set high.
RLOOP1, RLOOP2 : Remote Loopback (PLCC pins 7, 37; TQFP pins 63, 27)
A remote loopback is selected when RLOOP is high. The data received from the line interface
at RTIP and RRING is looped back through the jitter attenuator (if enabled) and retransmitted
on TTIP and TRING. Data recovered from RTIP and RRING continues to be transmitted on
RPOS/RNEG (or RDATA). Data input on TPOS/TNEG (or TDATA) is ignored. A TAOS
request overrides the data transmitted at TTIP and TRING.
TAOS1, TAOS2 : Transmit All Ones Select (PLCC pins 4, 3; TQFP pins 60, 59)
Setting TAOS high causes continuous ones to be transmitted at the line interface on TTIP and
TRING at the frequency determined by REFCLK.
Status
AIS1, AIS2 : Alarm Indication Signal (PLCC pins 15, 54; TQFP pins 6, 43)
The AIS indication goes high when the receiver detects 99.9% ones density in a 5.3 ms period
(< 9 zeros in 8192 bits). The AIS indication returns low when the receiver detects ≥ 9 zeros in
8192 bits.
BPV1, BPV2 : Bipolar Violation (PLCC pins 12, 57; TQFP pins 3, 46)
The BPV indication goes high for one RCLK bit period when a bipolar violation is detected in
the received signal. Bipolar violations caused by B8ZS (or HDB3) zero substitutions are not
flagged by the BPV pin if the coder mode is enabled.
DS172PP5 27
LOS1, LOS2 : Loss of Signal (PLCC pins 16, 53; TQFP pins 7, 42)
The LOS indication goes high when 175 ± 15 consecutive zeros are received on the line
interface. The LOS indication returns low when a minimum 12.5% ones density signal over
175 ± 75 bit periods with no more than 100 consecutive zeros is received.
Test
J-TCK : JTAG Test Clock (PLCC pin 51; TQFP pin 40)
Data on pins J-TDI and J-TDO is valid on the rising edge of J-TCK. When J-TCK is stopped
low, all JTAG registers remain unchanged.
J-TMS : JTAG Test Mode Select (PLCC pin 50; TQFP pin 39)
An active high signal on J-TMS enables the JTAG serial port. This pin has an internal pull-up
resistor.
J-TDI : JTAG Test Data In (PLCC pin 19; TQFP pin 10)
JTAG data is shifted into the device on this pin. This pin has an internal pull-up resistor. Data
must be stable on the rising edge of J-TCK.
J-TDO : JTAG Test Data Out (PLCC pin 17; TQFP pin 8)
JTAG data is shifted out of the device on this pin. This pin is active only when JTAG testing is
in progress. J-TDO will be updated on the falling edge of J-TCK.
CS61583
28 DS172PP5
PHYSICAL DIMENSIONS
68 pin PLCC
MILLIMETERS INCHES
DIM
A
A
B
D
D
E
E
e
2.29 .090
1
24.79 25.30 .976 .996
24.13 24.38 .950 .960
1
24.79 25.30 .976 .996
24.13 24.38 .950 .960
1
1.27 .050
MAXMIN MAXMIN
5.084.20 .200.165
3.30 .130
0.530.38 .021.015
68 pin
PLCC
CS61583
1
EE
u
x
y
z
23.37 23.62 .920 .930
1.067 .042
1.219 .048
.51 .020
.51 x 45° x 3 .02 x 45° x 3
x
D
1
D
z
A
y
1
A
e
u
B
DS172PP5 29
CS61583
D
D
1
64-Pin
TQFP
MILLIMETERS INCHES
DIM
E
E
1
64
1
MIN
A
A
B
C
D
D
E
E
e
L
∝∝
-
0.00
1
0.14
0.077
11.70
10.00
1
11.70
10.00
1
0.40
0.35
0° 12° 0° 12°
MAX
1.66
-
0.26
0.177
12.30
10.00
12.30
10.00
0.60
0.70
MIN
-
0.00
0.006
0.003
0.461
0.394
0.461
0.394
0.016
0.014
MAX
0.068
-
0.010
0.007
0.484
0.394
0.484
0.394
0.024
0.028
A
A
C
B
e
1
Terminal
Detail 1
∝∝
L
30 DS172PP5
APPLICATIONS
CS61583
Framer
Framer
CLKE TAOS1
ATTEN2
REFCLK 1XCLK
Clock Generator
TCLK1
TPOS1 (TDATA1)
TNEG1 (AIS1)
RCLK1
RPOS1 (RDATA1)
RNEG1 (BPV1)
TCLK2
TPOS2 (TDATA2)
TNEG2 (AIS2)
RCLK2
RPOS2 (RDATA2)
RNEG2 (BPV2)
AV+ AGND1:2 BGREF TV+1 TGND1 RV+1 RGND1 DV+ DGND1:3
0.1 µF
V
+
CC
1 µF
RESET
TV+2TGND2 RV+2RGND2
2
R3
4.99k
Ω
F 0.1 µF0.1 µF
0.1
µ
CON11
CON01
CON21
Hardware Control
Channel 1
Channel 2
Power Supply
0.1 µF
+
22 µF
Figure A1. Typical Connection Diagram
Data Rate (MHz) REFCLK Frequency (MHz)
1XCLK = 1 1XCLK = 0
1.544 1.544 12.352 100 38.3 220
2.048 2.048 16.384 75 28.7 470
RLOOP1
LLOOP1
AMI2AMI1
CODER2CODER1ATTEN1
CON02
CON12
TAOS2
CON22
Cable (Ω)R1-R4 (
RLOOP2
LLOOP2
TTIP1
TRING1
RTIP1
RRING1
TTIP2
TRING2
RTIP2
RRING2
0.01 µF
0.47µF
R1
0.47
R2
0.47µF
R3
0.47
R4
3
Ω
)
C1
C2
120 45.3 220
1:1.15
T1
T2
1:1.15
F
µ
T3
1:1.15
T4
1:1.15
F
µ
C1-C2 (pF)
transmit
receive
transmit
receive
Table A1. CS61583 External Components
Line Interface
In the receive line interface circuitry, resistors R1-
R4 provide receive impedance matching and
Figure A1 illustrates a typical connection diagram
and Table A1 lists the external components that
are required in T1 and E1 applications.
In the transmit line interface circuitry, capacitors
receiver return loss. The 0.47 µF capacitor to
ground provides the necessary differential input
voltage reference for the receiver.
Power Supply
C1 and C2 provide transmitter return loss. The
0.47 µF capacitor in series with the transformer
primary prevents output stage imbalances from
producing a DC current through the transformer
that might saturate the transformer and result in
an output level offset.
As shown in Figure A1, the CS61583 operates
from a 5.0 Volt supply. Separate analog and digi-
tal power supply and ground pins provide internal
isolation. The TGND, RGND, and DGND ground
pins must not be more negative than AGND. It is
recommended that all of the supply pins be con-
nected together at the device. A 4.99kΩ ±1%
DS172PP5 31
CS61583
resistor must be connected from BGREF to
ground to provide an internal current reference.
De-coupling and filtering of the power supplies is
crucial for the proper operation of the analog circuits. A capacitor should be connected between
each supply and its respective ground. For capaci-
tors smaller than 1 µF, use mylar or ceramic
capacitors and place them as close as possible to
their respective power supply pins. Wire-wrap
bread boarding of the line interface is not recommended because lead resistance and inductance
defeat the function of the de-coupling capacitors.
Crystal Oscillator Specifications
When a reference clock signal is not available, a
CMOS crystal oscillator operating at either the
1X or 8X rate can be connected at the REFCLK
pin. The oscillator must have a minimum symme-
try of 40-60% and minimum stability of ±100
ppm for T1 and E1 applications. Based on these
specifications, some suggested crystal oscillators
for use with the CS61583 are shown in Table A2.
Turns Ratio 1:1.15 step-up transmit
1:1.15 step-down receive
Primary inductance 1.5 mH min at 772 kHz
Primary leakage
inductance
Secondary leakage
0.3 µH max at 772 kHz
with secondary shorted
0.4 µH max at 772 kHz
inductance
Interwinding
capacitance
ET-constant
Table A3. Transformer Specifications
18 pF max, primary to
secondary
16 V-µs min
Designing for AT&T 62411
For additional information on the requirements of
AT&T 62411 and the design of an appropriate
system synchronizer, refer to the Crystal Semiconductor Application Notes "AT&T 62411
Design Considerations - Jitter and Synchronization" and "Jitter Testing Procedures for
Compliance with AT&T 62411."
Manufacturer Part Number Contact Number
Comclok CT31CH (800) 333-9825
CTS CXO-65HG-5-I (815) 786-8411
M-tron MH26TAD (800) 762-8800
SaRonix NTH250A (800) 227-8974
Notes:
Frequency tolerances are ±32 ppm with a -40 to +85 °C
operating tempera ture range.
All are 8-pin DIP packages and can be tristated.
Table A2. Suggested Crystal Oscillators
Transformers
Recommended transformer specifications are
shown in Table A3. Based on these specifications,
the transformers recommended for use with the
CS61583 are listed in Table A4.
Line Protection
Secondary protection components can be added
to the line interface circuitry to provide lightning
surge and AC power-cross immunity. For additional information on the different electrical
safety standards and specific application circuit
recommendations, refer to the Crystal Semiconductor Application Note "Secondary Line
Protection for T1 and E1 Line Cards."
32 DS172PP5
CS61583
Turns Ratio Manufacturer Part Number Package Type
PE-65388 1.5 kV through-hole, single
PE-65770 1.5 kV through-hole, single
extended temperature
PE-65838 3.0 kV through-hole, single
1:1.15 Pulse Engineering
extended temperature
PE-68674 1.5 kV surface-mount, dual
extended temperature
PE-65870 1.5 kV surface-mount, dual
Schott 67124840 1.5 kV through-hole, single
extended temperature
Valor ST5112 2.0 kV surface mount, dual
Schematic & Layout Review Service
Confirm Optimum
Schematic & Layout
Before Building Your Board.
For Our Free Review Service
Call Applications Engineering.
Call:(512)445-7222
DS172PP5 33
CDB61583
Dual Line Interface Evaluat ion Board
Features
Socketed CS61 583 Dual Line In terface
••
All Required Components for CS61583
••
Evaluation
Locations to Evaluate P rotection Circuitry
••
LED Status Indications for Alarm
••
Conditions
Control of Enhanced Hardware Options
••
TCLK1
TPOS1
(TDATA1)
TNEG1
CHANNEL 1
RCLK1
+5V 0V
General Description
The evaluation board includes a socketed CS61583
dual line interface device and all support components
necessary for evaluation. The board is powered by
an external +5 Volt supply.
The board may be configured for 100Ω twisted-pair
T1, 75Ω coax E1, or 120Ω twisted-pair E1 operation.
Binding posts and bantam jacks are provided for line
interface connections. Several BNC connectors provide clock and data I/O at the system interface.
Reference timing may be derived from a crystal osc illator or an external reference clock. Four LED
indicators monitor device alarm conditions.
ORDERING INFORMATION: CDB61583
TTIP1
TRING1
RTIP1
CHANNEL 1
RPOS1
{
(RDATA1)
RNEG1
(BPV1)
+5V
Hardware Control
and Mode Circuit
LED Status
Indicators
TCLK2
TPOS2
(TDATA2)
TNEG2
CHANNEL 2
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445-7222 FAX: (512) 445 7581
RCLK2
RPOS2
{
(RDATA2)
RNEG2
(BPV2)
RESET
CIRCUIT
}
RRING1
Circuit
TTIP2
TRING2
RTIP2
REFCLK
CHANNEL 2
CS61583
Oscillator
}
RRING2
Copyright Crystal Semiconductor Corporation 1995
(All Rights Reserved)
DEC ’95
DB172PP1
34
CDB61583
POWER SUPPLY
As shown on the evaluation board schematic in
Figures 1-5, power is supplied to the board from
an external +5 Volt supply connected to the two
binding posts labeled V+ and GND. Zener diode
Z1 protects the components on the board from
reversed supply connections and over-voltage
damage. Capacitor C16 provides power supply
decoupling and ferrite bead L1 isolates the
CS61583 and buffer supplies. Both sides of the
evaluation board contain extensive areas of
ground plane to insure optimum performance.
Capacitors C3, C5-C8, C13, C18, and C38
provide power supply decoupling for the
CS61583. The BGREF pin is pulled down
through resistor R10 to provide an internal
current reference. The buffers are decoupled
using capacitors C9, C15, and C19. Ferrite beads
L2-L4 help reduce the power supply noise that is
coupled from the buffers to the power supply.
BOARD CONFIGURATION
The evaluation board is based on the CDB61584
used to evaluate the CS61584 dual LIU
optimized for Host mode applications. Because
the CS61583 is optimized for Hardware mode
applications, slide switch SW6 must be placed in
the "HW" position to set the AGND1 pin of the
CS61583 to a logic 0. In addition, the host
processor interface appearing at J26 is not used
on the CDB61583.
The evaluation board is configured using DIP
switches SW2, SW3, and SW4. Because the
evaluation board is based on the CDB61584
design, switches SW2, SW3, and SW4 are
relabeled with white stickers. These switches
establish the digital control inputs for both line
interface channels. Closing a DIP switch towards
the label sets the CS61583 control pin of the
same name to a logic 1. All switch inputs are
pulled-down using resistor networks RP2-RP5.
The CDB61583 switch functions are listed
below:
• TAOS1, TAOS2: transmit all ones;
• LLOOP1, LLOOP2: local loopback;
• RLOOP1, RLOOP2: remote loopback;
• CODER1, CODER2: encoder/decoder control;
• ATTEN0, ATTEN1: jitter attenuator selection;
• CLKE: RCLK edge polarity;
• 1XCLK: clock frequency selection;
• AMI1, AMI2: encoder/decoder control;
• CONx1, CONx2: line configuration settings.
A jumper must be installed on header J10 to
enable RLOOP2 functionality.
Alarm Indications
The LOS1 and LOS2 LED indicators illuminate
when the line interface receiver has detected a
loss of signal. Headers J7 and J13 must be
jumpered in the "TNEG" position to provide
connectivity to the BNC input when the coder
mode is disabled (CODER(1,2) = 0).
The AIS alarm condition is provided when the
coder mode is enabled (CODER(1,2) = 1) and
headers J7 and J13 are jumpered in the "AIS"
position. The AIS1 and AIS2 LED indicators
illuminate when the line interface receiver has
detected the all-ones receive input signal.
Resistors R26 and R27 pull-down the
TNEG(1,2) inputs when coder mode is disabled
but headers J7 and J13 are jumpered in the
"AIS" position.
Manual Reset
A momentary contact switch SW1 provides a
manual reset by forcing the RESET pin of the
CS61583 to a logic 1. Although the transmit and
receive circuitry are continuously calibrated, the
DB172PP1 35
CDB61583
reset can be used to initialize the control logic.
Both channels are powered up after exiting reset.
TRANSMIT CIRCUIT
The transmit clock and data signals are supplied
on BNC inputs labeled TCLK(1,2), TPOS(1,2),
and TNEG(1,2). When the coder mode is
disabled, data is supplied on the TPOS(1,2) and
TNEG(1,2) BNC inputs in RZ format. When the
coder mode enabled, data is supplied on the
TDATA(1,2) BNC input in NRZ format and the
TNEG(1,2) BNC input may be used to indicate
the AIS alarm condition as described in the
Board Configuration section.
The transmitter output is transformer coupled to
the line interface through 1:1.15 step-up
transformers T1 and T4. The signal is available
at either the TTIP(1,2) and TRING(1,2) binding
posts or the TX(1,2) bantam jacks.
Capacitors C2 and C11 prevent output stage
imbalances from producing a DC current that
may saturate the transformer and result in an
output level offset. Capacitors C1 and C12
provide transmitter return loss and are socketed
so the value may be changed according to the
application. A 220 pF capacitor is required for
100Ω twisted-pair T1 or 120Ω twisted-pair E1
applications. A 470 pF capacitor is required for
75Ω coax E1 applications. These capacitors are
included with the evaluation board.
Optional diode locations D6-D9 and D10-D13
and optional resistor locations R8-R9 and
R18-R19 provide test locations to evaluate
transmit line interface protection circuitry.
RECEIVE CIRCUIT
transformer coupled to the CS61583 through
1:1.15 step-down transformers T2 and T3.
The receive line is terminated by resistors R3-R4
and R14-R15 to provide impedance matching
and receiver return loss. They are socketed so
the values may be changed according to the
application. The evaluation board is supplied
from the factory with 38.3Ω resistors for
terminating 100Ω twisted-pair T1 lines, 45.3Ω
resistors for terminating 120Ω twisted-pair E1
lines, and 28.7Ω resistors for terminating 75Ω
coaxial E1 lines. Capacitors C4 and C10 provide
a differential input voltage reference.
Optional resistor locations R1-R2, R12-R13,
R16-R17, and R24-R25 provide test locations to
evaluate receive line interface protection
circuitry.
The recovered clock and data signals are
available on BNC outputs labeled RCLK(1,2),
RPOS(1,2), and RNEG(1,2). When the coder
mode is disabled, data is available on the
RPOS(1,2) and RNEG(1,2) BNC outputs in RZ
format. When the coder mode is enabled, data is
available on the RDATA(1,2) BNC output in
NRZ format and bipolar violations are reported
on BPV(1,2).
REFERENCE CLOCK
The CDB61583 requires a T1 or E1 reference
clock for operation. This clock may operate at
either a 1-X rate (1.544 MHz or 2.048 MHz) or
an 8-X rate (12.352 MHz or 16.384 MHz) and
can be supplied by either a crystal oscillator or
an external reference. The evaluation board is
supplied from the factory with two crystal
oscillators for T1 and E1 operation.
The receive signal is input at either the
RTIP(1,2) and RRING(1,2) binding posts or the
RX(1,2) bantam jacks. The receive signal is
36 DB172PP1
CDB61583
Crystal Oscillator
A crystal oscillator may be inserted at socket U4
in the orientation indicated by the silkscreen.
Header J14 must be jumpered in the "OSC"
position to provide connectivity to the REFCLK
pin of the CS61583. The SW2 switch position
labeled "1XCLK" must be open (logic 0) for 8-X
clock operation or closed (logic 1) for 1-X clock
operation.
External Reference
An external reference may be provided at the
REFCLK BNC input. Header J14 must be
jumpered in the "REFCLK" position to provide
connectivity to the REFCLK pin of the
CS61583. The SW2 switch position labeled
"1XCLK" must be open (logic 0) for 8-X clock
operation or closed (logic 1) for 1-X clock
operation.
transformers installed at locations T1-T4. They
are socketed to permit the evaluation of other
transformers.
LINE PROTECTION EVALUATION
Several optional resistor and diode locations on
the transmit and receive line interface allow for
the installation and evaluation of various types
of protection circuitry. Each location is drilled
with 60 mil vias to permit the installation of
sockets. These sockets can be obtained from
McKenzie at (510) 651-2700 by requesting part
#PPC-SIP-1X32-620C and are identical to the
socket type installed at various resistor locations
on the board. They allow the line protection
circuitry to be easily changed during testing.
Note that the traces forming shorts between the
socket locations on the line interface may need
to be cut prior to protection circuitry installation.
BUFFERING
Buffers U2 and U3 provide additional drive
capability for the BNC inputs and outputs. The
buffer outputs are filtered with an RC network to
reduce the transients caused by buffer switching.
JTAG ACCESS
The CS61583 implements JTAG boundary scan
to support board-level testing. Interface port J56
provides access to the four JTAG pins on the
CS61583. The J-TMS pin of the CS61583 is
pulled-down by resistor R28 to disable boundary
scan unless the pin is externally pulled high
using the interface port.
TRANSFORMER SELECTION
The evaluation board is supplied from the
factory with Pulse Engineering PE-65388
PROTOTYPING AREA
Four prototyping areas with power supply and
ground connections are provided on the
evaluation board. These areas can be used to
develop and test a variety of additional circuits
such as framer devices, system synchronizer
PLLs, or specialized interface logic.
EVALUATION HINTS
1. The orientation of pin 1 for the CS61583 is
labeled "1" on the left side of the socket U7.
2. A jumper must be placed on header J10 when
using the CDB61583.
3. Component locations R3-R4, R14-R15, C1,
and C12 must have the correct values installed
according to the application. All the necessary
components are included with the evaluation
board.
DB172PP1 37
4. Closing a DIP switch on SW2, SW3, and
SW4 towards the label sets the CS61583 control
pin of the same name to logic 1.
5. When performing a manual loopback of the
recovered signal to the transmit signal at the
BNC connectors, the recovered data must be
valid on the falling edge of RCLK to properly
latch the data in the transmit direction. To
accomplish this, the SW2 switch position labeled
"CLKE" must be closed (logic 1).
6. Jumpers can be placed on headers J9 and J12
to provide a ground reference on TRING for
75Ω coax E1 applications.
7. Properly terminate TTIP/TRING when
evaluating the transmit output pulse shape. For
more information concerning pulse shape
evaluation, refer to the Crystal application note
entitled "Measurement and Evaluation of Pulse
Shapes in T1/E1 Transmission Systems."
CDB61583
38 DB172PP1
CDB61583
RCLK1
RPOS1
(RDATA1)
RNEG1
(BPV 1)
TCLK1
TPOS
(TDAT A1 )
TNEG
TTIP1
TRING1
RTIP1
RRING1
J31
J32
J33
J34
J1
J2
J3
J4
J5
J6
AIS1
LOS1
R29
51.1
R30
51.1
R31
51.1
D1
LED
D2
LED
R
R
L4
3
5
7
4
6
8
R6
470
R7
470
J8A
T
J8B
T
C26
100pF
C27
100pF
C28
100pF
U2
100pF
U2
100pF
U2
100pF
VA+
Q1
Q2
1
4
6
9
U2
U2
U2
C29
C30
C31
3
1
3
1
17
15
13
16
14
12
VA+
J9
2
2
R8
R9
R24
R25
R5
51.1
1
2
4
3
J7
R26
47K
T1
2
1
3
6
5
1.15:1
PE -65388
T2
2
1
3
6
5
1.15:1
PE -65388
R38
R39
VD+
C3
.1
CODER1
ATTEN0
VD+
D10
VD+
D12
R4
µ
F
D11
D13
J-TD O
J-TDI
R3
51.1
51.1
R1
R2
C1
C2
.47
VCC
1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
20
U2
10
GND
RCLK1
RPOS1
RNEG1
TCLK1
TPOS1
TNEG1
LOS1
J-TDO
DGND2
J-TDI
TTIP1
TV+1
TGND1
TRING1
CODER1
ATTEN0
N/C-1
19
CHANNEL 1
RTIP1
27
C9
µ
.1
F
F
µ
VA+
ENA
ENA
U7
CS61583
RRING 1
28
TV+1
C4
F
µ
.47
Notes: Com ponents R3, R4, and C1 are socketed to permit value changes
to the ap p lication .
Com ponent locations R1, R2, R8, R9, R24, R25, and D10-D13 provide
areas for evaluating protection circuitry.
Figure 1. Channel 1 Circuitry
DB172PP1 39
CDB61583
VA+
ENA
ENA
U7
CS61583
CHANNEL 2
TV+1
C38
22
F
µ
L2
41
VCC
1
U3
19
GND
N/C-3
RCLK2
RPOS2
RNEG2
TCLK2
TPOS2
TNEG2
LOS2
AMI2
J-TCK
J-TMS
TTIP2
TV+2
TGND2
TRING2
CODER2
CLKE
RTIP2
RRING2
42
43
J16
U3
U3
U3
Q4
3
1
R21
470
6
9
1
4
6
4
2
VA+
Q3
J11B
J11A
R41
51.1
R42
51.1
R43
51.1
R20
470
LED
D4
T
R
T
R
LED
LOS2
D3
J17
J18
J19
J20
J21
AIS2
J27
J28
J29
J30
RCLK2
RPOS2
(RDATA2)
RNEG2
(BPV2)
TCLK2
TPOS2
(TDATA2)
TNEG2
TTIP2
TRING2
RTIP2
RRING2
U3
U3
U3
100pF
2
R18
R19
R16
R17
9
C32
100pF
7
C33
100pF
5
C34
100pF
14
C35
16
C36
18
C37
100pF
2
VA+
3
1
J12
100pF
11
13
20
10
N/C-2
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
.47
C15
.1
µ
F
R50
R51
10K
CLKE
C12
C11
F
µ
R12
R13
R14
AMI2
J-TCK
J-TMS
R28
C13
.1
CODER2
VD+
VD+
D7
D8
D9
R15
C10
.47
F
µ
µ
D6
51.1
51.1
VD+
F
1
3
J13
T4
261
1:1.15
PE-65388
T3
261
1:1.15
PE-65388
2
4
R27
47K
15
R22
51.1
3
5
3
5
Notes: Components R14, R15, and C12 are socketed to permit value changes according
to th e application.
Component locations R 12, R13, R16-R19, and D6-D9 provide areas for evaluating
pro tec tion c ircuitry.
Figure 2. Channel 2 Circuitry
40 DB172PP1
CDB61583
VD+
SW2
1 24 TAOS2
2 23 TAOS1
3 22 LLOOP2
4 21 LLOOP1
520RLOOP1
619CODER1
718CODER2
817ATTEN0
916ATTEN1
10 15 CLKE
11 14 1XCLK
12 13
RLOOP2
VD+
J24
R55
3.92k
CS
SD1
765432 8765432
8
11
RP4
47k
RP5
47k
SD0
INT
SCLK
GNDGND
100pF
C20
R57
51.1
25
23
21
19
17
15
13
11
9
7
5
3
1
6
U6
J26
CODER1
CODER2
ATTEN0
CLKE
1XCLK
RLOOP2
14
C23
2
18
26
24
22
20
18
16
14
12
10
8
6
4
2
U6
9
100
pF
R58
8
7
R40
51.1
4
16
51.1
6
U6
U6
C24
100pF
5
100 pF
C25
9
GND
11
9
5
R
51.1
2
4
3
R56
51.1
100 pF
7
C39
U6
GND
13
RP2
47k
23456
VD+
.01µF
C18
1
68676665646362
J56
2
RP3
1
4
3
6
5
8
7
VD+
SW3
81CON01
72CON11
63CON21
54AMI1
SW4
81CON02
72CON12
63CON22
54AMI2
23456
47k
1
J-TD0
J-TD1
J-TMS
T-TCK
1
AMI2
61
N/C-4
ATTEN1
TAOS1
LLOO P1
LLOO P2
RLOOP1
CONTROL CIRCUITRY
TAOS2
CON01
CS61584
DGND1
U7
DV+
CON02
CON11
DGND3
AMI1
CON12
CON21
CON22
Note: T he Host interface at J26 is not used on the CDB61583.
Figure 3. Control Circuitry
DB172PP1 41
TIMING CIRCUITRY
RV+1
RGND1
AGND1
30
313233
29
U7
CS61583
BGREF
AGND2
343536
AV+
RESET
REFCLK
RLOOP2
37
38
CDB61583
1XCLK
RGND2
RV+2
39
40
SW6
R23
VD+
VD+
C14
.1µF
C5
.1µF
47K
VA+
C6
C7
SW1
VCC
GND
R10
.1µF
1.0
U4
4.99k
µ
F
VD+
1
2
VD+
R11
8
J14
Y1
10K
42
13
1XCL K
C8
.1µF
VD+
J 10
(must be jumpered)
RLOOP2
REFCLK
J15
Notes: A crystal oscillator at U4 or external reference supplied at J15 m ust be provided .
A quartz crystal cannot be used with the CS6 1583
Figure 4. Timing Circuitry
42 DB172PP1
CDB61583
J22
VA+
V+
C16
47µF
Z1
L1
Prototyping Area
GND
J23
VD+
VD+
Figure 5. Common Circuitry
DB172PP1 43
Smart
Analog
TM
is a Trademark of Crystal Semiconductor Corporation
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