Cirrus Logic CS61582-IQ5 Datasheet

Dual T1/E1 Line Interface

CS61582

Features

Dual T1/E1 Line Interface Optimized for

•

Mutiplexer Applications
Low Power Consumption

•

(Typically 220mW per Line Interface)
Transmit Driver Performance Monitors

•

Jitter Attenuation in the Transmit Path

•

Matched Impedance Transmit Drivers

•

Supports JTAG Boundary Scan

•

Hardware Mode Derivative of the CS61584

•

RESETCLKE TAOS1 LLOOP1 RLOOP1 CON01 CON11 CON21 RLOOP2LLOOP2TAOS2 CON02 CON12 CON22

TCLK1
TPOS1
TNEG1
RCLK1
RPOS1
RNEG1

TCLK2
TPOS2
TNEG2
RCLK2
RPOS2
RNEG2

R
E
M
O
T
E

L
O
O
P
B
A
C
K

R
E
M
O
T
E

L
O
O
P
B
A
C
K

JITTER

ATTENUATOR

JITTER

ATTENUATOR

L
O
C
A

L

L
O
O
P
B
A
C
K

1

L
O
C
A

L

L
O
O
P
B
A
C
K

1

General Description

The CS61582 is a dual line interface optimized for
highly-integrated T1/E1 asynchronous or synchronous
multiplexer applications such as SONET and SDH.
Each channel features individual control and status
pins which eliminates the need for external microproc­essor support. The matched impedance drivers reduce
power consumption and provide substantial return loss
to insure superior T1/E1 pulse quality.

The CS61582 provides two transmitter driver perform­ance monitor circuits and JTAG boundary scan to
enhance system testability and reliability. The CS61582
is a 5 volt device that is a hardware mode derivative of
the CS61584.

ORDERING INFORMATION

CS61582-IQ5, 64-pin TQFP, -40 to +85 °C

CONTROL

PULSE

TAOS

LOS

DETECT

TAOS

LOS

DETECT

SHAPING

CIRCUITRY

CLOCK &

DATA

RECOVERY

PULSE

SHAPING

CIRCUITRY

CLOCK &

DATA

RECOVERY

DRIVER

DRIVER
PERFORMANCE
MONITOR

RECEIVER

DRIVER

DRIVER
PERFORMANCE
MONITOR

RECEIVER

TTIP1
TRING1

MTIP1
MRING1

RTIP1
RRING1

TTIP2
TRING2

MTIP2
MRING2

RTIP2
RRING2

JTAG

4

CLOCK GENERATOR

REFCLK 1XCLK T V+ T GN D RV + RGN D D V + DGN D AV + AG ND

Crystal Semiconductor Corporation

P. O. Box 17847, Austin, Texas, 78760
[phone] FAX:[phone]

LOS1 LOS2

2 2 2 2 3 2

DPM1 DPM2

Copyright  Crystal Semiconductor Corporation 1996

(All Rights Reserved)

BGREF

JULY ’96

DS224PP1

1

Table of Contents

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Specifications

Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . 3

Recommended Operating Conditions. . . . . . . . . . . . . . . . . . 3

Digital Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Analog Specifications

Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Jitter Attenuator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Switching Characteristics

T1 Clock/Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

E1 Clock/Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

JTAG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

General Description

Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Jitter Attenuator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Power-Up Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Line Control and Monitoring . . . . . . . . . . . . . . . . . . . . . . . . 12

Driver Performance Monitor . . . . . . . . . . . . . . . . . . 12

Loss of Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Transmit All Ones . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Local Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Remote Loopback. . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

JTAG Boundary Scan. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Physical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

2 DS224PP1

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Min Max Units

DC Supply (TV+1, TV+2, RV+1, RV+ 2, AV+, DV+) (Note 1) - 6.0 V
Input Voltage (Any Pin) V
Input Current (Any Pin) (Note 2) I
Ambient Operating Temperature T
Storage Temperature T

in

in

A

stg

RGND - 0.3 (RV+) + 0.3 V

-10 10 mA

-40 85 °C

-65 150 °C

WARNING: Operations at or beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes.

Notes: 1. Referenced to RGND1, RGND2, TGND1, TGND2, AGND, DGND at 0V.

2. Transient currents of up to 100 mA will not cause SCR latch-up.

RECOMMENDED OPERATING CONDITIONS

Parameter Symbol Min Typ Max Units

DC Supply (TV+1, TV+2, RV+1, RV+ 2, AV+, DV+) (Note 3) 4.75 5.0 5.25 V
Ambient Operating Temperature T

A

Power Consumption T1 (Notes 4 and 5)
(Each Channel) T1 (Notes 4 and 6)

E1, 75Ω (Notes 4 and 5)

P

C

E1, 120Ω (Notes 4 and 5)

REFCLK Frequency

T1 1XCLK = 1

T1 1XCLK = 0

E1 1XCLK = 1

E1 1XCLK = 0

Notes: 3. TV+1, TV+2, AV+, DV+, RV+1, RV+2 should be connected together. TGND1, TGND2, RGND1,

RGND2, DGND1, DGND2, DGND3 should be connected together.

4. Power consumption while driving line load over operating temperature range. Includes IC and load.
Digital input levels are within 10% of the supply rails and digital outputs are driving a 50 pF
capacitive load.

5. Assumes 100% ones density and maximum line length at 5.25V.

6. Assumes 50% ones density and 300ft. line length at 5.0V.

-40 25 85 °C

-

-

-

-

1.544 -

100 ppm

12.352 -

100 ppm

2.048 -

100 ppm

16.384 -

100 ppm

310
220
275
275

1.544

12.352

2.048

16.384

-

-

-

-

1.544 +

100 ppm

12.352 +
100 ppm

2.048 +

100 ppm

16.384 +
100 ppm

MHz

MHz

MHz

MHz

mW
mW
mW
mW

DS224PP1 3

DIGITAL CHARACTERISTICS (T

Parameter Symbol Min Typ Max Units

= -40 to 85 °C; power supply pins within ±5% of nominal)

A

High-Level Input Voltage (Note 7) V
Low-Level Input Voltage (Note 7) V
High-Level Output Voltage (Note 8)

(Digital pins) I

OUT

= -40 µA

Low-Level Output Voltage (Note 8)
(Digital pins) I

OUT

= 1.6 mA

V

V

Input Leakage Current
(Digital pins except J-TMS, and J-TDI)

(DV+)-0.5 - - V

IH
IL

OH

OL

--0.5V

(DV+)-0.3 - - V

--0.3V

--

±10 µA

Notes: 7. Digital inputs are designed for CMOS logic levels.

8. Digital outputs are TTL compatible and drive CMOS levels into a CMOS load.

ANALOG SPECIFICATIONS (T

= -40 to 85 °C; power supply pins within ±5% of nominal)

A

Parameter Min Typ Max Units

Receiver

RTIP/RRING Differential Input Impedance

- 20k ­Sensitivity Below DSX-1 (0 dB = 2.4 V) -13.6 - - dB
Loss of Signal Threshold - 0.3 - V
Data Decision Threshold T1, DSX-1 (Note 9)

(Note 10)

E1 (Note 11)

(Note 12)

60
55
45
40

65
50

70

-

-

75
55
60

% of

Peak

Allowable Consecutive Zeros before LOS 160 175 190 bits
Receiver Input Jitter 10 Hz and below (Note 13)

Tolerance (DSX-1, E1) 2 kHz

10 kHz - 100 kHz

Receiver Return Loss 51 kHz - 102 kHz (Notes 14,

102 kHz - 2.048 MHz 21, and 22)

2.048 MHz - 3.072 MHz

300

6.0

0.4
12

18
14

-

-

-

-

-

-

-

-

-

-

-

-

dB
dB
dB

Jitter Attenuator

Jitter Attenuation Curve T1 (Notes 14 and 15)
Corner Frequency E1

-

-

4

5.5

-

-

Hz

Hz
Attenuation at 10 kHz Jitter Frequency (Notes 14 and 15) - 60 - dB
Attenuator Input Jitter Tolerance (Note 14)

(Before Onset of FIFO Overflow or Underflow Protection)

Notes: 9. For input amplitude of 1.2 Vpk to 4.14 V

pk

10. For input amplitude of 0.5 Vpk to 1.2 Vpk, and 4.14 Vpk to 5.0 V

28 43 - UI

pk

11. For input amplitude of 1.07 Vpk to 4.14 Vpk,

12. For input amplitude of 4.14 V

to 5.0 Vpk,

pk

13. Jitter tolerance increases at lower frequencies. Refer to the Receiver section.

14. Not production tested. Parameters guaranteed by design and characterization.

15. Attenuation measured with sinusoidal input jitter equal to 3/4 of measured jitter tolerance.
Circuit attenuates jitter at 20 dB/decade above the corner frequency. Output jitter
can increase significantly when more than 28 UI’s are input to the attenuator. Refer to the
Jitter Attenuator section.

Ω

UI
UI
UI

pk-pk

4 DS224PP1

ANALOG SPECIFICATIONS (T

= -40 to 85 °C; power supply pins within ±5% of nominal)

A

Parameter Min Typ Max Units

Transmitter

AMI Output Pulse Amplitudes (Note 16)

E1, 75Ω (Note 17)
E1, 120Ω (Note 18)
T1, DSX-1 (Note 19)

2.14

2.7

2.4

2.37

3.0

3.0

2.6

3.3

3.6

Recommended Transmitter Output Load (Note 16)

T1
E1, 75Ω
E1, 120Ω

Jitter Added During 10 Hz - 8 kHz
Remote Loopback 8 kHz - 40 kHz

10 Hz - 40 kHz
Broad Band (Note 20)

Power in 2 kHz band about 772 kHz (Notes 14 and 21)

(DSX-1 only)

Power in 2 kHz band about 1.544 MHz (Notes 14 and 21))
(referenced to power in 2 kHz band at 772 kHz) (DSX-1 only)

-

-

-

-

-

-

-

76.6

57.4

90.6

0.005

0.008

0.010

0.015

-

-

-

-

-

-

-

12.6 15 17.9 dBm

-29 -38 - dB

Positive to Negative Pulse Imbalance (Notes 14 and 21)

T1, DSX-1
E1, amplitude at center of pulse interval
E1, width at 50% of nominal amplitude

-

-5

-5

0.2

-

-

0.5
+5
+5

Transmitter Return Loss (Notes 14, 21, and 22)

51 kHz - 102 kHz
102 kHz - 2.048 MHz

2.048 MHz - 3.072 MHz

18
14
10

25
18
12

-

-

­E1 Short Circuit Current (Note 23) - - 50 mA
E1 and DSX-1 Output Pulse Rise/Fall Times (Note 24) - 25 - ns
E1 Pulse Width (at 50% of peak amplitude) - 244 - ns
E1 Pulse Amplitude E1, 75Ω

for a space E1, 120Ω

-0.237

-0.3

-

-

0.237

0.3

Notes: 16. Using a transformer that meets the specifications in the A pplications section.

17. Measured across 75 Ω at the output of the transmit transformer for CON2/1/0 = 0/0/0.

18. Measured across 120 Ω at the output of the transmit transformer for CON2/1/0 = 0/0/1.

19. Measured at the DSX-1 cross-connect for line length settings CON2/1/0 = 0/1/0, 0/1/1,
1/0/0, 1/0/1, and 1/1/0 after the appropriate length of #22 ABA M cable specified in Table 1.

20. Input signal to RTIP/RRING is jitter free. Values will reduce slightly if jitter free clock is input to TCLK.

21. Typical performance using the line interface circuitry recommended in the Applications section.

22. Return loss = 20 log

=cable impedance.

z

0

ABS((z1+z0)/(z1-z0)) where z1=impedance of the transmitter or receiver, and

10

23. Transformer secondary shorted with 0.5 Ω resistor during the transmission of 100% ones.

24. At transformer secondary and measured from 10% to 90% of amplitude.

V
V
V

Ω
Ω
Ω

UI
UI
UI
UI

dB

%
%

dB
dB
dB

rms

V
V

DS224PP1 5

SWITCHING CHARACTERISTICS - T1 CLOCK/DATA (T

= -40 to 85 °C; power supply

A

pins within ±5% of nominal; Inputs: Logic 0 = 0V, Logic 1 = DV+) (See Figures 1, 2, and 3)

Parameter Symbol Min Typ Max Units

TCLK Frequency (Note 25) f
TCLK Duty Cycle t
RCLK Duty Cycle t

pwh2/tpw2
pwh1/tpw1

Rise Time (All Digital Outputs) (Note 26) t
Fall Time (All Digital Outputs) (Note 26) t
RPOS/RNEG to RCLK Rising Setup Time t
RCLK Rising to RPOS/RNEG Hold Time t
TPOS/TNEG to TCLK Falling Setup Time t
TCLK Falling to TPOS/TNEG Hold Time t

tclk

r
f

su1

h1

su2

h2

- 1.544 - MHz
30 50 70 %
45 50 55 %

- - 65 ns

- - 65 ns

- 274 - ns

- 274 - ns
25 - - ns
25 - - ns

Notes: 25. The maximum burst rate of a gapped TCLK input clock is 8.192 MHz. The maximum gap siz e

that can be tolerated on TCLK is 28 UIp-p.

26. At max load of 50 pF.

SWITCHING CHARACTERISTICS - E1 CLOCK/DATA (T

= -40 to 85 °C; power supply

A

pins within ±5% of nominal; Inputs: Logic 0 = 0V, Logic 1 = DV+) (See Figures 1, 2, and 3)

Parameter Symbol Min Typ Max Units

TCLK Frequency (Note 25) f
TCLK Duty Cycle t
RCLK Duty Cycle t

pwh2/tpw2
pwh1/tpw1

Rise Time (All Digital Outputs) (Note 26) t
Fall Time (All Digital Outputs) (Note 26) t
RPOS/RNEG to RCLK Rising Setup Time t
RCLK Rising to RPOS/RNEG Hold Time t
TPOS/TNEG to TCLK Falling Setup Time t
TCLK Falling to TPOS/TNEG Hold Time t

tclk

r
f

su1

h1

su2

h2

- 2.048 - MHz
30 50 70 %
45 50 55 %

- - 65 ns

- - 65 ns

- 194 - ns

- 194 - ns
25 - - ns
25 - - ns

6 DS224PP1

t

r

t

f

RCLK
(CLKE = 1)

RPOS
RNEG

Any Digital Output

Figure 1. Signal Rise and Fall Characteristics

t

pwl1

t

su1

90% 90%

10% 10%

t

pw1

t

pwh1

t

h1

RCLK
(CLKE =0)

Figure 2. Recovered Clock and Data Sw itching Characterist ics

t

pw2

t

pwh2

TCLK

t

su2

t

h2

TPOS
TNEG

Figure 3. Transmit Clock and Data Switching Characteristics

DS224PP1 7

SWITCHING CHARACTERISTICS - JTAG

TV+, RV+ = nominal ±0.3V; Inputs: Logic 0 = 0V, Logic 1 = RV+) (See Figure 4)

Parameter S ymbol Min Typ Max Units

(TA = - 40 ° to 85 ° C;

Cycle Time t
J-TMS/J-TDI to J-TCK rising setup time t
J-TCK rising to J-TMS/J-TDI hold time t
J-TCK falling to J-TDO valid t

t

cyc

J-TCK

t

su

t

h

J-TMS
J-TDI

J-TDO

cyc

su

dv

200 - - ns

50 - - ns

h

50 - - ns

- - 50 ns

t

dv

Figure 4. JAG Switching Characte ristics

8 DS224PP1

OVERVIEW

The CS61582 is a dual line interface optimized
for highly-integrated T1/E1 asynchronous or
synchronous multiplexer applications such as
SONET or SDH. One board design can support
all T1/E1 short-haul modes by only changing
component values in the receive and transmit
paths (if REFCLK and TCLK are externally t ied
together).

The line receiver contains all the necessary clock
and data recovery circuits.

The jitter attenuator meets AT&T 62411 require­ments when using a 1X or 8X reference clock
supplied by either a crystal oscillator or external
reference at the REFCLK input pin.

TRANSMITTER

All control of the device is achieved via external
pins, eliminating the need for microprocessor
support. The following pin control options are
available on a per channel basis: line length se­lection, transmit all ones, local loopback, and
remote loopback.

The line driver generates waveforms compatible
with E1 (CCITT G.703), T1 short haul (DSX-1)
and T1 FCC Part 68 Option A (DS1). A single
transformer turns ratio is used for all waveform
types. The driver internally matches the imped­ance of the load, providing excellent return loss
to insure superior T1/E1 pulse quality. An addi­tional benefit of the internal impedance matching
is a 50 percent reduction in power consumption
compared to implementing return loss using ex­ternal resistors that causes the transmitter to
drive the equivalent of two line loads.

The transmitter accepts data from a T1 or E1
system and outputs pulses of appropriate shape
to the line. The transmit clock (TCLK) and
transmit data (TPOS and TNEG) are supplied
synchronously. Data is sampled on the falling
edge of the TCLK input.

The configuration pins CON[2:0] control trans­mitted pulse shapes, transmitter source
impedance, and receiver slicing level as shown in
Table 1. Typical output pulses are shown in Figures
5 and 6. These pulse shapes are fully pre-defined
by circuitry in the CS61582, and are fully compli­ant with appropriate standards when used with our
application guidelines in standard installations.
Both channels must be operated at the same line rate
(both T1 or both E1).

Note that the pulse width for Part 68 Option A
(324 ns) is narrower than the optimal pulse
width for DSX-1 (350 ns). The CS61582 auto-

C

C

C

Transmit Pulse

O

O

O

Width at 50%

N

N

N

2

1

0

000001244 ns (50%)

0 1 0 324 ns ( 50%) DS1: FCC Part 68 Option A (0 dB) 65%
0 1 1 350 ns ( 54%) DSX-1: 0-133 ft. / or DS1 FCC Part 68 Option A with undershoot 65%
1 0 0 350 ns ( 54%) DSX-1: 133-266 ft. 65%
1 0 1 350 ns ( 54%) DSX-1: 266-399 ft. 65%
1 1 0 350 ns ( 54%) DSX-1: 399-533 ft. 65%
1 1 1 350 ns ( 54%) DSX-1: 533-655 ft. 65%

DS224PP1 9

Amplitude

244 ns (50%)

Transmit Pulse Shape

E1: square, 2.37 Volts into 75 Ω
E1: square, 3.00 Volts into 120 Ω

Table 1. Configuration Selection

Receiver

Slicing

Level

50%
50%

NORMALIZED
AMPLITUDE

1.0
ANSI T1.102

SPECIFICATIO N

0.5

0

CS61582

OUTPUT

PULSE SHAPE

-0.5

0 250 750 1000

500

TIME (nanoseconds)

Figure 5. Typical Pulse Shape at DSX-1 Cross Connect

matically adjusts the pulse width based on the
configuration selection.

120
110
100

-10

-20

Percent of
nominal
peak
voltage

90
80

50

10

0

269 ns

244 ns

194 ns

G.703
SPECIFICATION

Nominal Pulse

219 ns

488 ns

The transmitter impedance changes with the line
length options in order to match the load imped-

ance (75Ω for E1 coax, 100Ω for T1, 120Ω for
E1 shielded twisted pair), providing a minimum
of 14 dB return loss for T1 and E1 frequencies
during the transmission of both marks and
spaces. This improves signal quality by minimiz­ing reflections from the transmitter. Impedance
matching also reduces load power consumption
by a factor of two when compared to the return
loss achieved by using external resistors.

The CS61582 driver will automatically detect an
inactive TLCK input (i.e., no valid data is being
clocked to the driver). When this condition is de­tected, the driver is forced low (except during
remote loopback) to output spaces and prevent
TTIP and TRING from entering a constant trans­mit-mark state.

When the transmit configuration established by
CON[2:0], TAOS, or LLOOP changes state, the
transmitter stabilizes within 22 TCLK bit peri­ods. The transmitter takes longer to stabilize
when RLOOP1 or RLOOP2 is selected because

Figure 6. Pulse Mask at the 2048 kbps Interface

the timing circuitry must adjust to the new fre­quency from RCLK.

When the transmitter transformer secondaries are
shorted through a 0.5 ohm resistor, the transmit­ter will output a maximum of 50 mA-rms, as

required by European specification BS6450.

RECEIVER

The receiver extracts data and clock from the
T1/E1 signal on the line interface and outputs
clock and synchronized data to the system. The
signal is detected differentially across the receive
transformer and can be recovered over the entire
range of short haul cable lengths. The transmit
and receive transfomer specifications are identical
and are presented in the Applications section.

As shown in Table 1, the receiver slicing level is
set at 65% for DS1/DSX-1 short-haul and at
50% for all other applications.

10 DS224PP1