Cirrus Logic CS61577-IP1, CS61577-IL1 Datasheet

T1/E1 Line Interface

CS61577

Features

Provides Analog Transmission Line

•

Interface for T1 and E1 Applications

Drop-in Replacement for CS61574 with

•

the Following Enhancements:

- Lower Power Consumption

- Transmitter Short-Circuit

Current Limiting

- Greater Transmitter Immunity

to Line Reflections

- Software Selection Between 75Ω and

120Ω E1 Output Options

- Internally Controlled E1 Pulse Width

- B8ZS/HDB3/AMI Encoder/Decoder

General Description

The CS61577 is a drop-in replacement for the
CS61574, and combines the complete analog transmit
and receive line interface for T1 or E1 applications in a
low power, 28-pin device operating from a +5V supply.
The CS61577 supports processor-based or stand­alone operation and interfaces with industry standard
T1 and E1 framers.

The receiver uses a digital Delay-Locked-Loop which is
continuously calibrated from a crystal reference to pro­vide excellent stability and jitt er tolerance. The receiver
includes a jitter attenuator optimized for minimum delay
in switching and transmission applications. The trans­mitter provides internal pulse shaping to insure
compliance with T1 and E1 pulse template specifica­tions.

Applications

• Interfacing Network Equipment such as DACS and

Channel Banks to a DSX-1 Cross Connect

• Building Channel Service Units

ORDERING INFORMATION
CS61577-IP1 28 Pin Plastic DIP
CS61577-IL1 28 Pin Plastic PLCC

TCLK

TPOS

[TDATA]

TNEG

[TCODE]

RCLK

RPOS

[RDATA]

RNEG

[BPV]

( ) = Pin Function in
[ ] = Pin Function in

2

3

4

AMI,

B8ZS,

HDB3,

8

CODER

7

6

RLOOP

(CS)

Host Mode

Extended Hardware Mode

R
E
M
O
T
E

L
O
O
P
B
A
C
K

26

XTALIN

JITTER

ATTENUATOR

9

XTALOUT10ACLKI

Preliminary Product Information

Crystal Semiconductor Corporation

P. O. Box 17847, Austin, Texas, 78760
[phone] FAX:[phone]

MODE

L
O
C
A

L

L
O
O
P
B
A
C
K

1

LLOOP
(SCLK)

(CLKE)

TAOS

5

CONTROL

27

(INT)

LEN0

28 23

CLOCK &

DATA

RECOVERY

SIGNAL

QUALITY

MONITOR

12 21

LOS

(SDI)

(SDO)

LEN1

LEN2

2524

PULSE

SHAPER

LINE RECEIVER

RV+22RGND

TGND

14

LINE DRIVER

DRIVER

MONITOR

TV+

15

13

16

19

20
17

18

11

TTIP

TRING

RTIP

RRING
MTIP

[RCODE]
MRING

[PCS]
DPM
[AIS]

This document contains information for a new product. Crystal
Semiconductor re ser ve s th e rig ht to modify this product wit hout n otic e.

Copyright  Crystal Semiconductor Corporation 1996

(All Rights Reserved)

MAY ’96

DS155PP2

1

CS61577

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Min Max Units

DC Supply (referenced to RGND=TGND=0V) RV+

TV+
Input Voltage, Any Pin (Note 1) V
Input Current, Any Pin (Note 2) I
Ambient Operating Temperature T
Storage Temperature T

in

in

A

stg

-

-

6.0

(RV+) + 0.3

RGND-0.3 (RV+) + 0.3 V

-10 10 mA

-40 85

-65 150

WARNIN G: O perat ions at or beyond these l imits may resul t in perma nent da mage to t he devi ce.

Normal operation is not guaranteed at these extremes.

Notes: 1. Excluding RTIP, RRING, whic h must stay wit hin -6V to (RV+ ) + 0.3V.

2. Transient currents of up to 1 00 mA will not cause SCR la tch-up. Also TTIP, TRING, TV+ and TGND
can withstand a continuous current of 100 mA.

RECOMMENDED OPERATING CONDITIONS

Parameter Symbol Min Typ Max Units

DC Supply (Note 3) RV+, TV+ 4.75 5.0 5.25 V
Ambient Operating Temperature T
Power Consumption (Notes 4,5) P
Power Consumption (Notes 4,6) P

Notes: 3. TV+ must not exceed RV+ by more than 0.3V.

4. Power consumption while driving line load over operating temperature range. Includes IC and load.
Digital input levels are within 10% of the supply rails and digital outputs are driving a 50 pF
capacitive load.

5. Assumes 100% ones density and maximum line length at 5.25V.

6. Assumes 50% ones density and 300ft. line length at 5.0V.

A
C
C

-40 25 85

-400500mW

-230-mW

V
V

°C
°C

°C

DIGITAL CHARACTERISTICS (TA = -4 0°C to 85°C; T V+, RV+ = 5.0V ± 5%; GND = 0V)

Parameter Symbol Min Typ Ma x Units

High-Level Input Voltage (Notes 7, 8)

V

IH

PINS 1-4 , 17, 18 , 23-28

Low-Level Input Voltage (Notes 7, 8)

V

IL

PINS 1-4 , 17, 18 , 23-28
High-Level Output Voltage (Notes 7, 8, 9)
I

= -40 µA PINS 6-8, 11, 12, 25

OUT
Low-Level Output Voltage (Notes 7, 8, 9)
I

= 1.6 mA PINS 6-8, 11, 12, 23, 25

OUT

V

OH

V

OL

Input Leakage Current (Except Pin 5) - ­Low-Level Input Voltage, PIN 5 V
High-Level Input Voltage, PIN 5 V
Mid-Level Input Voltage, PIN 5 (Note 10) V

IL
IH
IM

Notes: 7. In Extended Hardware Mode, pins 17 and 18 are digital inputs. In Host Mode, pin 23 is

an open drain output and pin 25 is a tristate output.

8. This specification guarantees TTL compatibility (V

= 2.4V @ I

OH

9. Output drivers will drive CMOS logic levels into a CMOS load.

10. As a n a lter nat ive t o suppl yin g a 2.3- to -2.7 V in put, th is pin may b e le ft flo ati ng.

2 DS155PP2

2.0 - - V

--0.8V

4.0 - - V

--0.4V

±10 µA

--0.2V

(RV+) - 0.2 - - V

2.3 - 2.7 V

= -40µA).

OUT

CS61577

ANALOG SPECIFICATIONS (TA = -40°C to 85°C; TV+, RV+ = 5. 0V ±5%; GND = 0V)

Parameter Min Typ Max Units

Transmitter

AMI Output Pulse Amplitudes (Note 11)

E1, 75 Ω (Note 12)
E1, 120 Ω (Note 13)
T1, (FCC Part 68) (Note 14)

T1, DSX-1 (Note 15)
Load Presented To Transmitter Output (Note 11) - 25 ­Jitter Added During Remote Loopback (Note 16)

10Hz - 8kHz

8kHz - 40k Hz

10Hz - 40k Hz

Broad Band
Power in 2kHz band about 772kHz (Notes 11, 17) 12.6 15 17.9 dBm
Power in 2kHz band about 1.544MHz (Notes 11, 17)

(referenced to power in 2kHz band at 772kHz)
Positive to Negative Pulse Imbalance (Notes 11, 17) - 0.2 0.5 dB
Transmitter Output Impedance (Notes 17, 18) - - 10
Transmitter Short Circuit Current (Notes 11, 19) - - 50 mA RMS

Notes: 11. Usi ng a 0.47 µF capacitor in series with the primary of a transformer recommended

in the Applications Section.

12. Pulse amplitude measured at the output of the transformer across a 75 Ω load for line length
settings LEN2/1/0 = 0/0/1 and 0/0/0. For LEN2/1/0 = 0/0/0 only, a 4.4 Ω resistor is required
in series with the transformer primary.

13. Pulse amplitude measured at the output of the transformer across a 120 Ω load for line length
setting LEN2/1/0 = 0/0/0.

14. Pulse amplitude measured at the output of the transformer across a 100 Ω load for line length
setting LEN2/1/0 = 0/1/0.

15. Pulse amplitude measured at the DSX-1 Cross-Connect for all line length settings from
LEN2/1/0 = 0/1/1 to LEN2/1/0 = 1/1/1.

16. Input signal to RTIP/RRING is jitter free. Values will reduce slightly if jitter free clock is input to TCLK.

17. Not production tested. Parameters guaranteed by design and characterization.

18. Measured between the TTIP and TRING pins at 772 kHz during marks and spaces.

19. Measured broadband through a 0.5 Ω resistor across the secondary of the transmitter transformer
during the transmission of an all ones data pattern with LEN2/1/0 = 0/0/0 or 0/0/1.

2.14

2.7

2.7

2.4

-

-

-

-

-29 -38 - dB

2.37

3.0

3.0

3.0

0.005

0.008

0.010

0.015

2.6

3.3

3.3

3.6

-

-

-

-

V
V
V
V

Ω

UI
UI
UI
UI

Ω

DS155PP2 3

CS61577

ANALOG SPECIFICATIONS (TA = -40°C to 85°C; TV+, RV+ = 5. 0V ±5%; GND = 0V)

Parameter Min Typ Max Units

Receiver

RTIP/RRING Input Impedance - 50k ­Sensitivity Below DSX (0dB = 2.4V) -13.6

500
Loss of Signal Threshold - 0.30 - V
Data Decision Threshold

T1, DSX-1 (Note 20)
T1, DSX-1 (Note 21)
T1, (FCC Part 68) and E1 (Note 22)

60
53

45
Allowable Consecutive Zeros before LOS 160 175 190 bits
Receiver Input Jitter Tolerance (Note 23)

10kHz - 100kHz
2kHz
10Hz and below

0.4

6.0

300

Jitter Attenuator

Jitter Attenuation Curve Corner Frequency (Notes 17, 24) - 6 - Hz
Attenuation at 10kHz Jitter Frequency (Notes 17, 24) - 50 - dB
Attenuator Input Jitter Tolerance (Before Onset

12 23 - UI
of FIFO Overflow or Underflow Protection) (Notes 17, 24)

Notes: 20. For input amplitude of 1.2 V

21. For input amplitude of 0.5 V

22. For input amplitude of 1.05 V

to 4. 14 Vpk.

pk

to 1.2 Vpk and from 4. 14 Vpk to RV+.

pk

to 3.3 Vpk.

pk

23. Jitter tolerance increases at lower frequencies. See Figure 11.

24. Attenuation measured with input jitter equal to 3/4 of measured jitter tolerance. Circuit attenuates
jitter at 20 dB/decade above the corner frequency. See Figure 12. Output jitter can increase

significantly when more than 12 UI’s are input to the attenuator. See discussion in the text section.

65
65
50

-

-

-

-

-

70
77
55

-

-

dB

mV

% of peak
% of peak
% of peak

-

-

-

UI
UI
UI

Ω

4 DS155PP2

CS61577

T1 SWITCHING CHARACTERISTICS (TA = -40°C to 85°C; TV+, RV+ = 5.0V ±5%;

GND = 0V; Inputs: Logic 0 = 0V, Logic 1 = RV+; See Figures 1, 2, & 3)

Parameter Symbol Min Typ Max Units

Crystal Frequency (Note 25) f
TCLK Frequency f
ACLKI Frequency (Note 26) f
RCLK Duty Cycle (Note 27) t
Rise Time, All Digital Outputs (Note 28) t
Fall Time, All Digital Outputs (Note 28) t
TPOS/TNEG (TDATA) to TCLK Falling Setup Time t
TCLK Falling to TPOS/TNEG (TDATA) Hold Time t
RPOS/RNEG Valid Before RCLK Falling (Note 29) t
RDATA Valid Before RCLK Falling (Note 30) t
RPOS/RNEG Valid Before RCLK Rising (Note 31) t
RPOS/RNEG Valid After RCLK Falling (Note 29) t
RDATA Valid After RCLK Falling (Note 30) t
RPOS/RNEG Valid After RCLK Rising (Note 31) t

c

tclk

aclki

pwh1/tpw1

r
f

su2

h2
su1
su1
su1

h1

h1

h1

Notes: 25. Crystal must meet specifications described in CXT6176/CXT8192 data sheet.

26. ACLKI provided by an external source or TCLK.

27. RCLK duty cycle will be 62.5% o r 37.5% when jitte r attenuator limit s are reach ed.

28. At max load of 1.6 mA and 50 pF.

29. Host Mode (CLKE = 1).

30. Extended Hardware Mode.

31. Hardware Mode, or Host Mode (CLKE = 0)

32. The transmitted pulse width does not depend on the TCLK duty cycle.

- 6.176000 - MHz

-1.544-MHz

-1.544-MHz

45 50 55 %

- - 85 ns

- - 85 ns
25 - - ns
25 - - ns

150 274 - n s
150 274 - n s
150 274 - n s
150 274 - n s
150 274 - n s
150 274 - n s

E1 SWITCHING CHARACTERISTICS (TA = -4 0°C to 85 °C; TV+, RV+ = 5.0V ±5%;

GND = 0V; Inputs: Logic 0 = 0V, Logic 1 = RV+; See Figures 1, 2, & 3)

Parameter Symbol Min Typ Max Units

Crystal Frequency (Note 25) f
TCLK Frequency f
TCLK Duty Cycle for LEN2/1/0 = 0/0/0 (Note 32) t
ACLKI Frequency (Note 26) f
RCLK Duty Cycle (Note 27) t
Rise Time, All Digital Outputs (Note 28) t
Fall Time, All Digital Outputs (Note 28) t
TPOS/TNEG (TDATA) to TCLK Falling Setup Time t
TCLK Falling to TPOS/TNEG (TDATA) Hold Time t
RPOS/RNEG Valid Before RCLK Falling (Note 29) t
RDATA Valid Before RCLK Falling (Note 30) t
RPOS/RNEG Valid Before RCLK Rising (Note 31) t
RPOS/RNEG Valid After RCLK Falling (Note 29) t
RDATA Valid After RCLK Falling (Note 30) t
RPOS/RNEG Valid After RCLK Rising (Note 31) t

c

tclk

pwh2/tpw2

aclki

pwh1/tpw1

r
f

su2

h2
su1
su1
su1

h1

h1

h1

DS155PP2 5

- 8.192000 - MHz

-2.048-MHz

40 50 60 %

-2.048-MHz

45 50 55 %

- - 85 ns

- - 85 ns
25 - - ns
25 - - ns

100 194 - n s
100 194 - n s
100 194 - n s
100 194 - n s
100 194 - n s
100 194 - n s

SWITCHING CHARACTERISTICS (TA = -40 ° to 85°C; TV +, RV+ = ±5% ;

Inputs: Logic 0 = 0V, Logic 1 = RV+)

Parameter Symbol Min Typ Max Un its

SDI to SCLK Setup Time t
SCLK to SDI Hold Time t
SCLK Low Time t
SCLK High Time t
SCLK Rise and Fall Time t
CS to SCLK Setup Time t
SCLK to CS Hold Time t
CS Inactive Time t
SCLK to SDO Valid (Note 33) t
CS to SDO High Z t
Input Valid To PCS Falling Setup Time t
PCS Rising to Input Invalid Hold Time t
PCS Active Low Time t

Notes: 33. Output load capacitance = 50pF

dc

cdh

cl

ch

, t

r

cc
cch
cwh
cdv
cdz
su4

h4

pcsl

f

50 - - ns

50 - - ns
240 - - ns
240 - - ns

- - 50 ns
50 - - ns
50 - - ns

250 - - ns

- - 200 ns

- 100 - ns
50 - - ns
50 - - ns

250 - - ns

CS61577

RCLK

RPOS
RNEG
RDATA

BPV

RCLK

Any Digital Output

Figure 1. Signal Rise and Fall Characteristics

t

t

pwl1

tt

su1

pw1

t

r

90% 90%

10%

t

pwh1

h1

10%

t

f

EXTENDED
HARDWARE
MODE OR
HOST MODE
(CLKE = 1)

HARDWARE
MODE OR

HOST MODE
(CLKE = 0)

Figure 2. Recovered Clock and Data Switching Characteristics

6 DS155PP2

t

pwh2

t

pw2

CS61577

CS

SCLK

SDI

TCLK

t

su2

t

h2

TPOS/TNEG

Figure 3. Transmit Clock and Data Switching Characteristics

t

t

cc

t

dc

LSB LSB

ch

CONTROL BYTE DATA BYTE

t

cl

t

cdh

Figure 4. Serial Port Write Timing Diagram

t

cdh

MSB

t

cch

t

cwh

CS

SCLK

SDO

CLKE = 1

t

cdv

Figure 5. Seria l Port R ead Timi ng Di agra m

PCS

t

h4

LEN0/1/2 , T A OS,
RLOOP, LLOOP,

RLOOP, LLOOP,

t

su4

t

pcsl

VALID INPUT DATA

RCODE, TCODE

Figure 6. Exte nded Ha rdwa re Mo de Par allel Chip Select Timin g Dia gram

t

cdz

HIGH Z

DS155PP2 7

CS61577

THEORY OF OPERATION

CS61577 Enhancement s Relative to CS61 574

Existing design s using the CS61574 can be con­verted to th e higher perform ance, pin-co mpatible
CS61577 with no changes to the PCB, external
component or system software.

The CS61577 provides higher performance and
more features than the CS61574 including:

• Selection of 75 Ω or 120 Ω E1 outpu t op-

tions under software or hardware control,

• 50 mA

transmitter short-ci rcuit current

RMS

limiting for E1 (per OFTEL OTR-001),

• internally co ntrolled puls e width for E1

output options,

• 35% lower power consumption,

• Increased transmit ter immunity to signal re-

flections for improved signal qu ality,

• Optional AMI, B8ZS, HDB3 enc oder/de-

coder or external line coding support,

• Receiver AIS (unframed all on es) detect ion,

• Improved receiver Loss of Signal handling

(LOS set at power-up, reset upon receipt of
3 ones in 32 bit pe riods with no more t han
15 consecutive zeros),

• Transmitter TTIP and TRING ou tputs are

forced low when TCLK is static,

• The Driver Performan ce Monitor op erates

over a wider range of input signal levels.

Introduction to Op erating Modes

The CS61577 supports three operating modes
which are selected by the level of the MODE pin
as shown in Tables 1 and 2, Figure 7, and Figures
A1-A3 of the Applications section.

The modes are Har dware Mode, Extended Hard­ware Mode, and Host Mode. In Hardware and
Extended Hardware Modes, discret e pins are used
to configure and monitor the device. The Ex­tended Hardware Mode provides a parallel chip
select input which latches the control inputs al-

lowing individual ICs to be configured using a
common set of control lines. In the Host Mode,
an external processor monito rs and configures the
device through a serial interface. There are thir­teen multi-function pins whose functionality is
determined by the operating mode. (see Table 2).

Hardware

Mode

Control

Method

MODE

Pin

Level

Line

Coding

AIS

Detection

Driver

Performance

Monitor

Table 1. Diff erences Betwe en Operati ng Modes

FUNCTION PIN HARDWARE

TRANSMITTER

RECEIVER/DPM

CONTROL

Control

Pins

<0.2 V Floating or

External Internal-

No Yes No

Yes No Yes

3TPOS TDATA TPOS
4TNEG
6 RNEG B PV RNEG
7RPOS RDATA RPOS

11 DPM AIS DPM
17 MTIP
18 MRING - MRING
18 ­23 LEN0 LEN0
24 LEN1 LEN1 SDI
25 LEN2 LEN2 SDO
26 RLOOP RLOOP
27 LLOOP LLOOP SCLK
28 TAOS TAOS CLKE

Table 2. Pin Definitions

Extended

Hardware

Mode

Control Pins

with Parallel

Chip Select

2.5 V

AMI, B8ZS,

or HDB3

MODE

EXTENDED

HARDWARE HOST

TCODE TNEG

RCODE MTIP

PCS -

Host

Mode

Serial

Interface

>(R V+)-0.2 V

External

INT

CS

8 DS155PP2

CS62180B
FRAMER
CIRCUIT

TNEG

RPOS
RNEG

CS61577

JITTER

ATTENUATOR

EXTENDED HARDWARE MODE

HARDWARE MODE

RLOOP LEN0/1/2LLOOPTAOS

CONTROL

LINE DRIVER

DRIVER MONITOR

LINE RECEIVER

MRING
MTIP

TTIPTPOS
TRING

DPM
RTIP

RRING

CS61577

TRANSMIT

TRANSFORMER

RECEIVE

TRANSFORMER

T1 or E1

REPEATER

OR

MUX

CONTROL

CS62180B

FRAMER
CIRCUIT

TDATA

CODER

RDATA

BPV AIS

µ

P SERIAL POR T

5

TPOS
TNEG

RPOS
RNEG

RCODETCODE

AMI

B8ZS,

HDB3,

CS61577

JITTER

ATTENUATOR

CS61577

AIS

DETECT

CLKE

CONTROL

RLOOP PCS LEN0/1/2LLOOPTAOS

CONTROL

JITTER

ATTENUATOR

HOST MODE

LINE DRIVER

DRIVER MONITOR

LINE RECEIVER

LINE DRIVER

RECEIVER

LINE

MRING

MTIP

TTIP
TRING

RTIP
RRING

TTIP
TRING

DPM
RTIP

RRING

TRANSMIT

TRANSFORMER

RECEIVE

TRANSFORMER

TRANSMIT

TRANSFORMER

RECEIVE

TRANSFORMER

Figure 7. Overv iew of Op eratin g Mode s

DS155PP2 9

CS61577

Transmitter

The transmitter takes digita l T1 or E1 input data
and drives appropriately shaped bipolar pulses
onto a transmission line through a 1:2 trans­former. The transmit data (TPOS & TNEG or
TDATA) is supplied synchronously and sampled
on the falling edge of the input clock, TCLK.

Either T1 (DSX-1 or Network Interface) or E1
CCITT G.703 pulse shapes may be selected.
Pulse shaping and signal level are controlled by
"line length selec t" inputs as shown in Table 3.

For T1 DSX-1 applications, line lengths from 0 to
655 feet (a s measured from t he transmitter to the
DSX-1 cross conne ct) may be selected. The five
partition arrangement in Table 3 meets ANSI
T1.102 and AT&T CB-119 requirements when
using #22 ABAM cable. A typica l outpu t pulse is
shown in Figure 8. The se pulse settings can also
be used to meet CCITT pul se shape require ments
for 1.544 MHz operation.

For T1 Network In terface applicat ions, two add i­tional opti ons are provided. Not e that the o ptimal
pulse width for Part 68 (324 ns) is narrower than
the optimal pu lse width for DSX-1 (350 ns ). The
CS61577 automatically adjusts the pulse width
based upon the "line length" selection made.

NORMALIZED

AMPLITUDE

1.0

0.5

0

OUTPUT

PULSE SHAPE

-0.5

0

Figure 8. Typical Pulse Shape at DSX-1 Cross Connect

250 750 1000

500

TIME (nanoseconds)

ANSI T1.102,
AT&T CB 119

SPECIFICATIONS

The E1 G.703 p ulse shape is supported wi th line
length selections LEN2/1/0=0/0/0 or
LEN2/1/0=0/0/1. As with the CS61574,

LEN2/1/0=0/0 /0 supports the 120 Ω, 3 V o utput
option without external series resistors, but will

also support the 75 Ω, 2.37 V output optio n with
an external 4.4 Ω resistor in series with TTIP or

TRING. The new LEN2/1/0=0/0 /1 code supports
the 75 Ω, 2.37 V outpu t option without external

series resistors allowing for software selection be­tween the two E1 output opti ons. The pulse width
will meet th e G.703 pulse shape template shown
in Figure 9, and specified in Table 4.

The CS61577 wi ll detect a static TCL K, and will
force TTIP and TRING low to prevent trans mis-

LEN2 LEN1 LEN0 Option Selected Application

0 1 1 0-133 FEET
100 133-266 FEET
101 266-399 FEET
110 399-533 FEET
111 533-655 FEET
000

001

0 1 0 FCC PART 68, OPT. A NETWORK
011 ANSI T1.403

Table 3. Line Length Selection

10 DS155PP2

75 Ω (with 4.4 Ω

resistor) & 120 Ω

75 Ω (without

4.4 Ω resistor)

DSX-1
ABAM

(AT&T 600B

or 600C)

E1

CCITT G.703

INTERFACE

sion when data is not present. When any transmit
control pin (TAOS, LEN0-2 or LLOOP) is tog­gled, the transmitter outputs will require
approximately 22 bit periods to stabilize. The
transmitter will take longer to stabilize when
RLOOP is selected because the timing circuitry
must adjust to the new frequency.

CS61577

Percent of
nominal
peak
voltage

120

110

100

90

80

50

10

0

-10

-20

Figure 9. Mask of the Pulse at the 2048 kbps Interface

269 ns

244 ns

194 ns

Nominal Pulse

219 ns
488 ns

Transmit All Ones Select

The transmitter provides for all ones insertion at
the frequency of TCLK. Transmit all ones is se­lected when TAOS goes high, and causes
continuous ones to be transmitted on the line
(TTIP and T RING). In this mode , the TPOS and
TNEG (or TDATA) inputs are ignore d. If Remote
Loopback is in effect, any TAOS request will be
ignored.

Receiver

The receiver extracts dat a an d cl ock fro m an AMI
(Alternate Mark Inversion) coded signal and out­puts clock an d synchronized data. The receiver is
sensitive to signals over the entire range of
ABAM cable lengths and requires no equalizati on
or ALBO (Automatic Line Build Out) circuits.
The signal is received on both ends of a center­tapped, center-grounded transformer. The
transformer is center tapped on the IC side. The
clock and dat a recovery circuit exceeds the jitter
tolerance specifications of Publications 43802,
43801, AT&T 62411, TR-TSY-000170, and
CCITT REC. G.823.

A block diagram of the rec eiver is shown in Fig­ure 10. The two leads of the transformer (RTIP
and RRING) have oppos ite polarity allowing the
receiver to treat RTIP and RRING as unipolar sig­nals. Comparators are used to detect pulses on
RTIP and RRING. The co mparator th resholds are
dynamically established a t a percent of the peak
level (50% of peak for E1, 65% of peak for T1;
with the slicing level selected by LEN2/1/0 in­puts).

The leading ed ge of an incoming data pul se trig­gers the clo ck phase selector. The phase selector
chooses o ne of the 13 available ph ases which the
delay line pr oduces for each bit period. T he out-

For coaxial cable,
75Ω load and
transformer specified

in Application Section.
Nominal peak voltage of a mark (pulse) 2.37 V 3 V
Pea k voltage of a space (no pulse)
Nominal puls e wi dt h 244 ns
Ratio of the amplitudes of positive and negative

pulses at the center of the pulse interval
Ratio of the widths of positive and negative

pulses at the nomi nal half amplitude

* When configured with a 0.47 µF nonpolarized capacitor in series with the TX transformer

primary as shown in Figures A1, A2 and A3.

Table 4. CCITT G.703 S pecificati ons

DS155PP2 11

0 ±0.237 V 0 ±0.30 V

0.95 to 1.05*

0.95 to 1.05*

For shielded twisted
pair, 120Ω load and
transformer specified
in Application Section.

CS61577

RTIP

1 : 2

RRING

Data
Level
Slicer

Edge

Detector

Figure 1 0. Re cei ver Bl oc k Di agr am

put from the phase selector feeds the clock and
data recovery circuits which generate the recov­ered clock and sample the incoming signal at
appropriate intervals to recover the data.

Data sampling will continue at the periods se­lected by the phase selector until an incoming
pulse deviates enou gh to cause a new phase to be
selected for da ta sampling. The phases of the d e­lay line are selected and updated to allow as much
as 0.4 UI of jitter from 10 kHz to 100 kHz, with­out error. The jitter tolerance of the receiver
exceeds that shown in Figure 11. Additionally,
this method o f clock and d ata recovery is tol erant
of long strings of consecutive zeros. The data

Minimum
Performance

PEAK-TO-PEAK

JITTER

(unit intervals)

300
138

100

AT&T 62411

28
10

Data

Sampling

& Clock

Extraction

Clock

Phase

Selector

Continuously

Calibrated

Delay Line

Jitter

Attenuator

RPOS
RNEG
RCLK

sampler will continuously sample data based on
its last input until a new pulse arrives to update
the clock phase selector.

The delay line is continuously calibrated using
the crystal oscillator reference clock. The delay
line produces 13 phases for eac h cycle of the ref­erence clock. In effect, the 13 phases are
analogous to a 20 MHz clock when the reference
clock is 1.544 MHz. This implementation utilizes
the benefits of a 2 0 MHz clo ck for cl ock recovery
without actually having the clock present to im­pede analog circuit performance.

In the Hardware Mode, d ata at RPOS and RNEG
should be sampled on th e rising edge of RCLK,
the recovered clock. In the Extended Hardware
Mode, data at RDATA shou ld be sampled on the
falling edge of RCLK. In the Host Mode, CLKE
determines the clock polarity for which output
data should be sampled as s hown in Table 5.

1

.4

.1

1

10 1k 10k

100 100k700

300

JITTER FREQUENCY (Hz)

Figure 11. Minimum Input Jitter Tolerance of Receiver

(Clock Reco very C ircui t and Jitt er Atte nua tor)

12 DS155PP2

CS61577

MODE

(pin 5)

LOW

(<0.2V)

HIGH

(>(V+) - 0.2V)

HIGH

(>(V+) - 0.2V)

MIDDLE

(2.5V)

X = Don’t Care

Table 5. Data Ou tput/Clock Relatio nship

CLKE

(pin 28) DATA CLOCK

RPOS

X

RNEG

LOW

HIGH

RPOS
RNEG

SDO

RPOS
RNEG

SDO

X RDATA RCLK Falling

RCLK
RCLK

RCLK
RCLK

SCLK

RCLK
RCLK

SCLK

Clock Edge for

Valid Data

Rising
Rising

Rising
Rising

Falli ng
Falli ng

Falli ng
Rising

Loss of Signal

The receiver will indicate loss of signal after
power-up, reset or upon receiving 175 consecu­tive zeros. A digital counter counts received
zeros, base d on RCLK cycles. A zero is received
when the RTIP and RRING inputs are below the
input comparator slicing threshold level estab­lished by the peak detector. After the signal is
removed for a period of time the data slicing
threshold level decays to approximately
300 mV

peak

.

The receiver reports loss of s ignal by setting the
Loss of Signal p in, LOS, high. If the serial inter­face is used, the LOS bit will be set and an
interrupt will be issued on
LOS will return low (asserting the

INT (unless disabled).

INT pin again
in Host Mode) upon receipt of 3 ones in 32 bit
periods with no more t han 15 consecutive zeros.
Note that in the Host Mode, LOS is simultane­ously available from both the register and pin 12.
RPOS/RNEG or RDATA are forced low during
LOS unless the jitter attenuator is dis abled. (See
"Jitter Attenuator" section)

If ACLKI is present during the LOS st ate, ACLKI
is switched int o the input of the jitter attenua tor,
resulting in RCLK matching the frequency of
ACLKI. The jitter attenuator buffers any inst anta­neous changes in phase between the last
recovered clock and the ACLKI reference clock.

This means that RCLK will smoothly transition
to the new frequency. If ACLKI is not present,
then the crysta l osci lla tor of the jit ter atte nua tor is
forced t o its center frequ ency. Table 6 shows the
status of RCLK upon LOS.

Crystal

present?

No Yes ACLKI

Yes No Center ed Crysta l
Yes Yes

ACLKI

present?

Table 6. RC LK Stat us at L OS

Source of RCLK

ACLKI via t he

Jitter Attenuator

Jitter Attenuator

The jitter at tenuator reduces wander and jitte r in
the recovered cl ock signal. It consists of a 32-bit
FIFO, a crystal os cillator, a set o f load ca pacitors
for the crystal, and control log ic. The jitter attenu­ator exceeds the jit ter attenu ation requi rements of
Publication s 43802 and REC. G.742.

The jitter attenu ator works in the following man­ner. The recovered clock and data are in put to t he
FIFO with the recovered clock controlling the

FIFO’s write pointer. The crystal oscillator con­trols the FIFO’s read pointer which reads data out
of the FIFO and presents it at RPOS and RNEG
(or RDATA). The u pdate rate of the read p ointer
is analogous to RCLK. By chang ing the load ca­pacitance that the IC presents to the crystal, the
oscillation frequency is adjusted to the average
frequency of the recovered signal. Logic deter­mines the phase relationship between the read and
write pointe rs and decid es how to adjust the lo ad
capacitance of the crystal. Thus th e jitter attenu­ator behaves as a first-order phase lock loop. Jitter
is absorbed in the FIFO according to the jitter
transfer ch ar acteristic s h own in Figure 12.

DS155PP2 13

CS61577

0

a) Minimum Attenuati on Limit

10

20

30

b) Maximum

40

Attenuation in dB

Attenuation
Limit

50

60

110

Figure 12. Typ ical Jitte r Tr ansf er Fun ction

62411 Requirements

Measured Performance

100
Frequency in Hz

1 k 10 k

The FIFO in the jitter attenuator is designed to
prevent overflow and underflow. If the jitter am­plitude becomes very large, the read and write
pointers may get very clos e together. Should they

attempt to cross, the oscillator’s divide by four
circuit adjusts by performing a divide by 3 1/2 or
divide by 4 1/2 to prevent the overflow or under­flow. During this activity, data will never be lost.

Local Loopback

Local loopbac k is selected by taking LLOOP, pin
27, high or by setting the LLOOP register bit via
the serial interface.

The local loopback mode takes clock and data
presented on TCLK, TPOS, and TNEG (or
TDATA), sends it through the j itter a tte nuator a nd
outputs it at RCLK, RPOS and RNEG (or
RDATA). If the jitter attenuator is disabled, it is
bypassed. Inputs to the tr ansmitter are still trans­mitted on TTIP and TRING, unless TAOS has
been selec ted in which case, AMI-coded conti nu­ous ones are tra nsmitted at the TCLK freq uency.
The receiver RT IP and RRING inp uts are igno red
when local loopback is in effect.

Remote Loopback

Remote loopback is selected by taking RLOOP,
pin 26, high o r by settin g the RLOOP register bit
via the serial interface.

The 32-bit FIFO in the CS61577 attenuator al­lows it to absorb jitter with minimum dat a d elay
in T1 and E1 switching or transmission applica­tions. Like the CS61574, the CS61577 will
tolerate large amplitude jitter (>23 UIpp) by
tracking rather than attenuating it, preventing data
errors so that the jitter may be absorbed in exter­nal frame buffers.

The jitter at tenuator may be bypass ed by pulling
XTALIN to RV+ through a 1 kΩ resistor and pro-

viding a 1.544 MHz (or 2.048 MHz) clock on
ACLKI. RCLK may exhibit quantiza tion jitter of
approximately 1/13 UIpp and a duty cycle of ap­proximately 30% (70%) when the attenuator is
disabled.

In remote loopbac k, the re covered clock and da ta
input on RTIP and RRING are sent through the
jitter attenuato r and back ou t on the lin e via TTIP
and TRING. Selecting remote loo pback overrides
any TAOS request (see Table 6). The recovered
incoming signals are also sent to RCLK, RPOS
and RNEG (or RDATA). A remote loopbac k oc­curs in response to RLOOP going high.

RLOOP

Input

Signal

Notes: 1. X = Don’t Care. The identified All Ones Select

TAOS

Input

Signal
00 TDATA TCLK
0 1 all 1s TCLK
1 X RTIP & RRING RTIP & RRING (RCLK)

input is ignored when the indicated loopback is
in effect.

2. Logic 1 indicates that Loopback or All Ones
option i s sele ct ed.

Table 7. Interaction of RLOOP wi th TAOS

Source of

Data for

TTIP & TRING

Source of

Clock for

TTIP & TRING

14 DS155PP2