Cirrus Logic CS61535A-IP1, CS61535A-IL1 Datasheet

T1/E1 Line Interface

CS61535A

Features

Provides Analog PCM Line Interface

•

for T1 and E1 Applications Provides Line Driver, and Data and

•

Clock Recovery Functions Transmit Side Jitter Attenuation

•

Starting at 6 Hz, with > 300 UI of Jitter Tolerance

Low Power Consumption

•

(typically 175 mW) B8ZS/HDB3/AMI Encoders/Decoders

•

14 dB of Transmitter Return Loss

•

Compatible with SONET, M13 , CCITT

•

G.742, and Other Asynchronous Muxes

General Description

The CS61535A combines the complete analog transmit and receive line interface for T1 or E1 applications in a low power, 28-pi n dev i ce operating from a +5V su ppl y .

The device features a transmitter jitter attenuator making it ideal for use in asynchro nous multiplexor s ystems with gapped transmit clocks. The CS61535A provides a matched, constant impedance output stage to insure signal qualit y on m ism atched, poorly term inated lines.

Both ICs use a digital Delay-Locked-Loop clock and data recovery circuit which is continuously calibrated from a crystal reference to provide excellent stability and jitter tolerance.

Applications

• Interfacing network transmission equipment such as

SONET multiplexor and M13 to a DSX-1 cross connect.

• Interfacing customer premis es equipment to a CSU.

• Interfacing to E1 links.

Ordering Information

CS61535A-IP1 28 Pin Plastic DIP CS61535A-IL1 28 Pin PLCC (j-leads)

[ ] = Pin Function in ( ) = Pin Function in

TCLK

TPOS

[TDATA]

TNEG

[TCODE]

RCLK

RPOS

[RDATA]

RNEG

[BPV]

B8ZS, HDB3

CODER

Extended Hardware Mode

Host Mode

AMI,

LOOP BACK

(CS)

LLOOP (SCLK)

RLOOP

Crystal Semiconductor Corporation

P.O. Box 17847, Austin, TX 78760 (512) 445-7222 FAX: (512) 445-7581

XTALIN

XTALOUT

JITTER

ATTENUATOR

(INT)

(SDI)

(CLKE)

MODE

CONTROL

ACLKI

LEN0

TAOS

28 23

CLOCK &

DATA

RECOVERY

SIGNAL

QUALITY

MONITOR

12 21

LOS

(SDO)

LEN1

LEN2

PULSE

SHAPER

RV+22RGND

TGND

2524

LINE DRIVER

LINE RECEIVER

MONITOR

DRIVER

TV+

20 17

MAY ’96

TTIP

TRING

RTIP

RRING MTIP

[RCODE] MRING [PCS] DPM [AIS]

DS40F2

CS61535A

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Min Max Units

DC Supply (referenced to RGND,TGND=0V) RV+

TV+ Input Voltage, Any Pin (Note 1) V Input Current, Any Pin (Note 2) I Ambient Operating Temperature T Storage Temperature T

stg

6.0

(RV+) + 0.3

RGND-0.3 (RV+) + 0.3 V

-10 10 mA

-40 85

-65 150

WARNIN G: O perat ions at or beyond these l imits may resul t in perma nent da mage to t he devi ce.

Normal operation is not guaranteed at these extremes.

Notes: 1. Excluding RTIP, RRING, whic h must stay wit hin -6V to (RV+ ) + 0.3V.

2. Transient currents of up to 1 00 mA will not cause SCR la tch-up. Also TTIP, TRING, TV+ and TGND can withstand a continuous current of 100 mA.

RECOMMENDED OPERATING CONDITIONS

Parameter Symbol Min Typ Max Units

DC Supply (Note 3) RV+, TV+ 4.75 5.0 5.25 V Ambient Operating Temperature T Power Consumption (Notes 4, 5) P Power Consumption (Notes 4, 6) P

Notes: 3. TV+ must not exceed RV+ by more than 0.3V.

4. Power consumption while driving line load over operating temperature range. Includes IC and load. Digital input levels are within 10% of the supply rails and digital outputs are driving a 50 pF load.

5. Assumes 100% ones density and maximum line length at 5.25V.

6. Assumes 50% ones density and 300ft. line length at 5.0V.

A C C

-40 25 85

-290350mW

-175-mW

V V

°C °C

°C

2 DS40F2

CS61535A

DIGITAL CHARACTERISTICS (TA = -40°C to 8 5°C; TV+, RV + = 5.0V ±5%; GND = 0V)

Parameter Symbol Min Typ Ma x Units

High-Level Input Voltage

Pins 1-4 , 17, 18 , 23-28 (No tes 7, 8, 9) V

Low-Level Input Voltage

Pins 1-4 , 17, 18 , 23-28 (No tes 7, 8, 9) V

High-Level Output Voltage (I

Pins 6-8 , 11, 12 , 25 (Notes 7, 8, 10)

Low-Level Output Voltage (I

Pins 6-8 , 11, 12 , 23, 25 (Notes 7, 8, 10) V

OUT

= -40 µA)

= 1.6 mA)

Input Leakage Current (Except Pin 5) - Low-Level Input Voltage, Pin 5 V High-Level Input Voltage, Pin 5 V Mid-Level Input Voltage, Pin 5 (Note 11) V

Notes: 7. This specification guarantees TTL compatibility (V

IL IH IM

= 2.4V @ I

8. In Host Mode, pin 23 is an open drain output and pin 25 is a tristate output.

9. Pins 17 and 18 of the CS61535A are digital inputs in the Extended Hardware Mode.

10. Output drivers will drive CMOS logic levels int o a CMOS load.

11. As a n a lter nat ive t o suppl yin g a 2.3- to -2.7 V in put, th is pin may b e le ft flo ati ng.

2.0 - - V

--0.8V

4.0 - - V

--0.4V ±10 µA

--0.2V

(RV+) - 0.2 - - V

2.3 - 2.7 V = -40µA).

OUT

ANALOG SPECIFICATIONS (TA = -40°C to 85°C; TV+, RV+ = 5. 0V ±5%; GND = 0V)

Parameter Min Typ Max Units

Jitter Attenuator

Jitter Attenuation Curve Corner Frequency (Note 12) - 6 - Hz T1 Jitter Attenuation in Remote Loopback (Note 13)

Jitter Freq. [Hz] Amplitude [UIpp] 10 10 100 10 500 10 1k 5 10k, 40 k 0.3

E1 Jitter Attenuation in Remote Loopback (Note 14)

Jitter Freq. [Hz] Amplitude [UIpp] 10 1.5 100 1.5 400 1.5 1k 1. 5 10k, 100k 0.2

Attenuator Input Jitter Tolerance (Note 15) 12 23 - UI

Notes: 12. Not production tested. Parameters guaranteed by design and characterization.

13. At tenuation measured at the demodulator output of an HP3785B with input jitter equal to 3/4 of measured jitter tolerance using a measurement bandwidth of 1 Hz (10<f<100Hz), 4Hz (100<f<1000 Hz) and 10 Hz (f> 1kHz) centered around the jitter frequency. With a 2 Crystal must meet specifcations in CXT6176/8192 datasheet.

14. J itter measured at the demodulator output of an HP3785A using a measurement bandwidth not to exceed 20 Hz centered around the jitter frequency. With a 2 Crystal must meet specifications in CXT6176/8192 datasheet.

15. Output jitter increases significantly when attenuator input jitter tolerance is exceeded.

3.0 20 35 40 40

3.0 20 30 35 35

6.0 30 35 50 50

6.0 32 43 50 50

-1 PRBS data pattern.

dB dB dB dB dB

DS40F2 3

CS61535A

ANALOG SPECIFICATIONS (TA = -40°C to 85°C; TV+, RV+ = 5. 0V ±5%; GND = 0V)

Parameter Min Typ Max Units

Transmitter

AMI Output Pulse Amplitudes (Note 16)

E1, 75 Ω (Note 17) E1, 120 Ω (Note 18) T1, FCC Part 68 (Note 19) T1, DSX-1 (Note 20)

E1 Zero (space ) level (LE N2/1/0 = 0 /0/0)

75Ω application (Note 17)

120Ω application (Note 18) Recommended Output Load at TTIP and TRING - 75 Jitter Added During Remote Loopback (Note 21)

10Hz - 8kHz

8kHz - 40k Hz

10Hz - 40k Hz

Broad Band Power in 2kHz band about 772kHz (Notes 12, 16) 12.6 15 17.9 dBm Power in 2kHz band about 1.544MHz (Notes 12, 16)

(referenced to power in 2kHz band at 772kHz) Positive to Negative Pulse Imbalance (Notes 12, 16)

T1, DSX-1

E1 amplitude at center of pulse

E1 pulse width at 50% of nominal amplitude Transmitter Return Loss (Notes 12, 16, 22)

51 kHz to 102 kHz

102 kHz to 2.048 MHz

2.048 MHz to 3.072 MHz

Transmitter Short Circuit Current (Notes 12, 23) - - 50 mA RMS

Notes: 16. Usi ng a 0.47 µF capacitor in series with the primary of a transformer recommended

in the Applications Section.

17. Amplitude measured at the transformer (CS61535A-1:1 or 1:1.26) output across a 75 Ω load for line length settin g LEN2/1/0 = 0 /0/0.

18. Amplitude measured at the transformer (CS61535A-1:1.26) output across a 120 Ω load for line length setting LEN2/1/0 = 0/0/0.

19. Amplitude measured at the transformer (CS61535A-1:1.15) output across a 100 Ω load for line length setting LEN2/1/0 = 0/1/0.

20. Amplitude measured across a 100 Ω load at the DSX-1 cross-connect for line length settings LEN2/1/0 = 0/1/1, 1/0/0, 1/0/1, 1/1/0 and 1/1/1 after the length of #22 AWG ABAM equivalent cable specified in Table 3. The CS61535A requires a 1:1.15 transformer.

21. Input signal to RTIP/RRING is jitter free. Values will reduce slightly if jitter free clock is input to TCLK.

22. Return loss = 20 log z0 = imped anc e of lin e loa d. Mea sur ed wi th a re pea ting 101 0 da ta p att ern wit h LEN 2/1 /0 = 0/ 0/0 and a 1:1 transformer terminated with a 75Ω load, or a 1:1.26 transformer terminated with a 120Ω load.

23. Measured broadband through a 0.5 Ω resistor across the secondary of a 1:1.26 transformer during the transmission of an all ones data pattern for LEN2/1/0 = 0/0/0.

ABS((z1 +z0)/(z1-z0)) wher e z1 = impedance of the transmitter, and

2.14

2.7

2.4

-0.237

-0.3

-29 -3 8 - dB

-5

8 14 10

2.37

3.0

0.005

0.008

0.010

0.015

0.2

2.6

3.3

3.6

0.237

0.3

0.02

0.025

0.05

0.5 5 5

V V V V

V V

Ω

UI UI UI UI

% %

dB dB dB

4 DS40F2

CS61535A

ANALOG SPECIFICATIONS (TA = -40°C to 85°C; TV+, RV+ = 5. 0V ±5%; GND = 0V)

Parameter Min Typ Max Units

Driver Performance Monitor

MTIP/MRING Sensitivity: Differential Voltage Required for Detection

Receiver

RTIP/RRING Input Impedance - 50k Sensitivity Below DSX (0dB = 2.4V) -13.6 - - dB Data Decision Threshold

T1, DSX-1 (Note 24) T1, DSX-1 (Note 25) T1, FCC Part 68 and E1 (Note 26)

Data Decision Threshold T1

E1 Allowable Consecutive Zeros before LOS 160 175 190 bits Receiver Input Jitter Tolerance (Note 27)

10kHz - 100kHz 2kHz 10Hz and below

Loss of Signal Threshold (Note 28) 0.25 0.30 0.50 V

Notes: 24. For input amplitude of 1.2 V

25. For input amplitude of 0.5 Vpk to 1.2 Vpk and from 4. 14 Vpk to RV+.

26. For input amplitude of 1.05 Vpk to 3.3 Vpk.

27. J itter tolerance increases at lower frequencies. See Figure 11.

28. LOS goes high after 160 to 190 consecutive zeros are received. A zero is output on RPOS and RNEG (or RDATA) for each bit period where the input signal amplitude remains below the data decision threshold. The analog input squelch circuit operates when the input signal amplitude above ground on the RTIP and RRING pins falls within the squelch range long enough for the internal slicing threshold to decay within this range. Operation of the squelch causes zeros to be output on RPOS and RNEG as long as the input amplitude remains below 0.25V. During receive LOS, pulses greater than 0.25V in amplitude may be output on RPOS and RNEG. LOS returns low after the ones density reaches 12.5% (based upon 175 bit periods starting with a one and containing less than 100 consecutive zeros) as prescribed in ANSI T1.231-1993.

to 4. 14 Vpk.

-0.60-V

60 53 45

0.4

6.0

300

65 65 50

65 50

70 77 55

% of peak % of peak % of peak

% of peak % of peak

UI UI UI

Ω

DS40F2 5

CS61535A

T1 SWITCHING CHARACTERISTICS (TA = -40°C to 85°C; TV+, RV+ = 5.0V ±5%;

GND = 0V; Inputs: Logic 0 = 0V, Logic 1 = RV+; See Figures 1, 2, & 3)

Parameter Symbol Min Typ Max Units

Crystal Frequency (Note 29) f ACLKI Duty Cycle t ACLKI Frequency (Note 30) f RCLK Duty Cycle (Notes 31, 32) t

RCLK Cycle Width (Note 32) t

Rise Time, All Digital Outputs (Note 33) t Fall Time, All Digital Outputs (Note 33) t TPOS/TNEG (TDATA) to TCLK Falling Setup Time t TCLK Falling to TPOS/TNEG (TDATA) Hold Time t RPOS/RNEG Valid Before RCLK Falling (Note 34) t RDATA Valid Before RCLK Falling (Note 35) t RPOS/RNEG Valid Before RCLK Rising (Note 31) t RPOS/RNEG Valid After RCLK Falling (Note 34) t RDATA Valid After RCLK Falling (Note 35) t RPOS/RNEG Valid After RCLK Rising (Note 31) t TCLK Frequency f TCLK Pulse Width (Notes 12, 31, 34, 36, 37)

pwh3/tpw3

aclki

pwh1/tpw1

pw1

pwh1

pwl1

r f

su2

h2 su1 su1 su1

h1 tclk

pwh2

(Notes 35, 36, 37)

Notes: 29. Cr ystal must meet specifications described in CXT6176/CXT8192 data sheet.

30. ACLKI provided by an external source or TCLK, but

not

RCLK.

31. Hardware Mode, or Host Mode (CLKE = 0).

32. RCLK cycle width will vary wit h extent by which p ulses displaced b y jitter. Specifie d under worst case jitter conditions: 0.4 UI AMI data displacement for T1 and 0.2 UI AMI data displacement for E1.

33. At max load of 1.6 mA and 50 pF.

34. Host Mode (CLKE = 1).

35. Extended Hardware Mode.

36. The maximum TCLK burs t rate is 5 MHz and t

(min) = 200 ns. The maximum gap size that can

pw2

be tolerated on TCLK is 12 VI.

37. The transmitted pulse width does not depend on the TCLK duty cycle.

pw1

RCLK

RPOS RNEG RDATA

BPV

RCLK

pwl1

su1

pwh1

- 6.176000 - MHz

40 - 60 %

-1.544-MHz

320 130 100

78 29

648 190 458

980 240 850

- - 85 ns

- - 85 ns 25 - - ns 25 - - ns

150 274 - ns 150 274 - ns 150 274 - ns 150 274 - ns 150 274 - ns 150 274 - ns

-1.544-MHz 80

150

EXTENDED HARDWARE MODE OR HOST MODE (CLKE = 1)

HARDWARE MODE OR

HOST MODE

(CLKE = 0)

500 500

% %

ns ns ns

ns ns

Figure 1. Recovered Clock and Data Switching Characteristics

6 DS40F2

CS61535A

E1 SWITCHING CHARACTERISTICS (TA = -4 0°C to 85 °C; TV+, RV+ = 5.0V ±5%;

GND = 0V; Inputs: Logic 0 = 0V, Logic 1 = RV+; See Figures 1, 2, & 3)

Parameter Symbol Min Typ Max Units

Crystal Frequency (Note 29) f ACLKI Duty Cycle t

pwh3/tpw3

ACLKI Frequency (Note 30) f RCLK Duty Cycle (Notes 31, 32) t

pwh1/tpw1

RCLK Cycle Width (Note 32) t

pwh1

RCLK Cycle Width (Note 32) t

pwh1

t Rise Time, All Digital Outputs (Note 33) t Fall Time, All Digital Outputs (Note 33) t TPOS/TNEG (TDATA) to TCLK Falling Setup Time t TCLK Falling to TPOS/TNEG (TDATA) Hold Time t RPOS/RNEG Valid Before RCLK Falling (Note 34) t RDATA Valid Before RCLK Falling (Note 35) t RPOS/RNEG Valid Before RCLK Rising (Note 31) t RPOS/RNEG Valid After RCLK Falling (Note 34) t RDATA Valid After RCLK Falling (Note 35) t RPOS/RNEG Valid After RCLK Rising (Note 31) t TCLK Frequency f TCLK Pulse Width (Notes 31, 34, 36, 37)

pwh2

(Notes 35, 36, 37)

aclki

pw1

pwl1

pw1

pwl1

r f

su2

h2 su1 su1 su1

h1 tclk

- 8.192000 - MHz

40 - 60 %

-2.048-MHz

-29-%

310

120 320

100

488 140 348

488 348 140

670 190 500

670

- - 85 ns

- - 85 ns 25 - - ns 25 - - ns

100 194 - ns 100 194 - ns 100 194 - ns 100 194 - ns 100 194 - ns 100 194 - ns

-2.048-MHz 80

150

340 340

ns ns ns

ns ns

Any Digital Output

90% 90%

10%

Figure 2. Signal Rise and Fall Characteristics

pw2

pwh2

TCLK

TPOS/TNEG

su2

Figure 3a. Transmit Clock and Data Switching

ACLKI

Figure 3b. Alternate External Clock Characteristics

pwh3

pw3

Charact er ist ic s

DS40F2 7

SWITCHING CHARACTERISTICS (TA = -40 ° to 85°C; TV +, RV+ = ±5% ;

Inputs: Logic 0 = 0V, Logic 1 = RV+)

Parameter Symbol Min Typ Max Units

SDI to SCLK Setup Time t SCLK to SDI Hold Time t SCLK Low Time t SCLK High Time t SCLK Rise and Fall Time t CS to SCLK Setup Time t SCLK to CS Hold Time (Note 38) t CS Inactive Time t SCLK to SDO Valid (Note 39) t CS to SDO High Z t Input Valid To PCS Falling Setup Time t PCS Rising to Input Invalid Hold Time t PCS Active Low Time t

Notes: 38. For CLKE = 0,

CS must remain low at least 50 ns after the 16th falling edge of SCLK.

39. Output load capacitance = 50pF.

cdh

, t

cch

cwh

cdv cdz su4

pcsl

50 - - ns

50 - - ns 240 - - ns 240 - - ns

- - 50 ns 50 - - ns 50 - - ns

250 - - ns

- - 200 ns

- 100 - ns 50 - - ns 50 - - ns

250 - - ns

CS61535A

SCLK

SDI

LSB

cdh

LSB

CONTROL BYTE DATA BYTE

Figure 4. Serial Port Write Timing Diagram

cdh

MSB

cch

cwh

8 DS40F2

SCLK

cdv

CS61535A

cdz

SDO

CLKE = 1

Figure 5. Seria l Port R ead Timi ng Di agra m

PCS

su4

LEN0/1/2, TAOS, RLOOP, LLOOP,

RCODE, TCODE

Figure 6. Exte nded Ha rdwa re Mo de Par allel Chip Select Timin g Dia gram

VALID INPUT DATA

pcsl

HIGH Z

DS40F2 9

CS61535A

THEORY OF OPERATION

Enhancement s in CS61535 A

The CS61535A provides higher performance and more features than the CS61535 including:

• 50% lower power consumption,

• Internally matched transmitter output imped-

ance for improved signal quality,

• Optional AMI, B8ZS, HDB3 enc oder/de cod er

or external line coding support,

• Receiver AIS (unframed all ones) detection,

• ANSI T1.231-1993 compliant receiver Loss

of Signal (LOS) handling,

• Transmitter TTIP and TRING outputs are

forced low when TCLK is static,

• The Driver Performance Monitor operates

over a wider range of input signal levels.

• Elimination of the requirement that a refer-

ence clock be input on the ACLKI pin.

Existing designs using the CS61535 can be converted to the higher performance, pin-compatible CS61535A if the transmit transformer is repl aced by a pin-compatible transform er with a new turns ratio and th e 4.4

Ω resistor use d in E1 75 Ω applications is shorted.

Introduction to Op erating Modes

The CS61535A supports three operating modes which are se lected by th e level o f the MODE pi n

MODE

HARDWARE

MODE-PIN

INPUT LEVEL

CONTROL

METHOD

LINE CODE

ENCODER &

DECODER

AIS DETECTION NO YES NO

DRIVER

PERFORM-

ANCE MONITOR

<0.2V

INDIVIDUAL

CONTROL

LINES

NONE

YES NO YES

EXTENDED

HARDWARE

FLOAT, or

2.5V

INDIVIDUAL

CONTROL

LINES &

P ARALLEL

CHIP

SELECT

AMI,

B8ZS,

HDB3

HOST

>(RV+) - 0.2V

SERIAL

µ-PROCESSOR

PORT

NONE

as shown in Ta bles 1 and 2, Figure 7, and Figures A1-A3 of the Applications section.

The CS61535A modes are Hardware Mode, Extended Hardware Mode, and Host Mode. In Hardware and Extended Hardware Modes, discrete pins are used to configure and monitor the device. The Extended Hardware Mode provides a parallel chip select input which latches the control inputs allowing individual ICs to be configured using a common set of control lines. In the Host Mode, an external processor monitors and configures the device through a serial interface. There are thirteen multi-function pins whose functionality is determined by the operatin g mode (se e Table 2).

Transmitter

The transmitter takes data from a T1 (or E1 ) terminal, attenuates jitter, and produces pulses of appropriate shape. The transmit clock, TCLK, and transmit data, TPOS & TNEG or TDATA, are supplied synchronously. Data is sampled on the falling edge of the input clock, TCLK.

Either T1 (DSX-1 or Network Interface) or E1 G.703 pulse shapes may be selected. Pulse sh aping and signal level are determined by "line length select" inputs as shown in Table 3. The

MODE

FUNCTION PIN HARDWARE

TRANSMITTER

RECEIVER/DPM

CONTROL

3TPOS TDATATPOS 4TNEG 6 RNEG BPV RNEG 7 RPOS RDATA RPOS

11 DPM AIS DPM 17 MTIP 18 MRING - MRING 18 23 LEN0 LEN0 24 LEN1 LEN1 SDI 25 LEN2 LEN2 SDO 26 RLOOP RLOOP 27 LLOOP L LOO P SCLK 28 TAOS TAOS CLKE

EXTENDED

HARDWARE

TCODE TNEG

RCODE MTIP

PCS -

HOST

INT

Table 1. Dif feren ces in Operat ing Mode s

Table 2. Pin Definitions

10 DS40F2

CS62180B FRAMER CIRCUIT

TNEG

RPOS RNEG

JITTER

ATTENUATOR

CS61535A

EXTENDED HARDWARE MODE

HARDWARE MODE

RLOOP LEN0/1/2LLOOPTAOS

CONTROL

LINE DRIVER

DRIVER MONITOR

LINE RECEIVER

MRING

MTIP

TTIPTPOS

TRING

DPM RTIP

RRING

CS61535A

TRANSMIT

TRANSFORMER

RECEIVE

TRANSFORMER

HIGH

SPEED

MUX

(e.g., M13)

CONTROL

CS62180B

FRAMER

CIRCUIT

TDATA

RDATA

BPV AIS

P SERIAL PORT

TPOS TNEG

RPOS RNEG

RCODETCODE

AMI B8ZS, HDB3,

CODER

JITTER

ATTENUATOR

CS61535A

JITTER

ATTENUATOR

CS61535A

AIS

DETECT

CLKE

CONTROL

RLOOP PCS LEN0/1/2LLOOPTAOS

CONTROL

HOST MODE

LINE DRIVER

DRIVER MONITOR

LINE RECEIVER

LINE DRIVER

LINE RECEIVER

MRING

MTIP

TTIP TRING

RTIP

RRING

TTIP TRING

DPM RTIP

RRING

TRANSMIT

TRANSFORMER

RECEIVE

TRANSFORMER

TRANSMIT

TRANSFORMER

RECEIVE

TRANSFORMER

Figure 7. Overv iew of Op eratin g Mode s

DS40F2 11

CS61535A

LEN2 LEN1 LEN0 OPTION SELECTED APPLICATION

0 1 1 0-133 FEET 100 133-266 FEET 101 266-399 FEET 110 399-533 FEET 111 533-655 FEET

001 0 0 0 CCITT G.703 2. 048 MHz E1

0 1 0 FCC Part 68, Option A CSU NETWORK 0 1 1 ANSI T1.403

AT&T C B113

(CS61535A only)

DSX-1 ABAM

(AT&T 600B

or 600C)

REPEATER

INTERFACE

Table 3. Line Length Selection

CS61535A line driver is desig ned to drive a 75 Ω equivalent lo ad.

For T1 DSX-1 applications, line lengths from 0 to 655 feet (a s measured from t he transmitter to the DSX-1 cross connect) are selectable. The five partition arrangement meets ANSI T1.102-1993 requirements when using ABAM ca ble. A typical output pulse is shown in Figure 8. These pulse settings can also be used to meet CCITT pulse shape requirements for 1.544 MHz operation.

width will meet the G.703 pulse shape template shown in Fi gu r e 9, a n d specified in Table 4.

For E1 applications, the CS61535A driver provides 14 dB of return loss during the transmission of both marks and spaces. This improves signal quality by minimizing reflections off the transmitter. Similar levels of ret urn loss are provided for T1 applications.

The CS61535A transmitter will detect a failed TCLK, and will force the TTIP and TRING outputs low.

NORMALIZED AMPLITUDE

1.0

0.5

AT&T CB 119 SPECIFICATION

For T1 Network Inte rface app lications , additi onal options are provided. No te that the op timal pulse width for Part 68 (324 ns) is narrower than the optimal pulse width for DSX-1 (350 ns). The CS61535A automatically adjusts the pulse width based upon the "line length " se lection made.

The E1 G.703 pu lse shape is supported wit h line length selection LEN2/1/0=0/0/0. The pulse

Nominal peak voltage of a mark (pulse) 2.37 V 3 V Peak voltage of a spac e (n o pulse) Nominal puls e wi dt h 244 ns Ratio of the amplitudes of positive and negative

pulses at the center of the pulse interval Ratio of the widths of positive and negative

pulses at the nomi nal half amplitude

* When configured with a 0.47 µF nonpolarized capacitor in series with the TX transformer

primary as shown in Figures A1, A2 and A3.

CS61535A

OUTPUT

PULSE SHA PE

-0.5 0 250 750 1000

500

TIME (nanoseconds)

Figure 8. Typical Pulse Shape at DSX-1 Cross Connect

For coaxial cable, 75Ω load and transformer specified in Application Section.

For shielded twisted pair, 120Ω load and transformer specified in Application Section.

0 ±0.237 V 0 ±0.30 V

0.95 to 1.05*

Table 4. CCITT G.703 S pecificati ons

12 DS40F2

CS61535A

Percent of nominal peak

voltage 120 110 100

90 80

-10

-20

Figure 9 . Mask of the Pulse at the 2048 kbps Interface

269 ns

244 ns 194 ns

Nominal Pulse

219 ns 488 ns

When any transmit control pin (TAOS, LEN0-2 or LLOOP) is toggled, the transmitter stabilizes within 22 bit periods. The transmitter will take longer to stabilize when RLOOP is selected because the timi ng circuitry must adj ust to the new frequency.

Jitter Attenuato r

The jitter attenu ator is designed to redu ce wander and jitter i n the transmit clock signal. It c onsists of a 32 bit FIFO, a cr ystal osci llator, a set of loa d capacitors for the crystal, and cont rol logic. The jitter attenuator exceeds the jitter attenuation requirements of Publications 43802 and REC. G.742. A typical jitter attenuation curve is shown in Figure 10.

The jitter attenuato r works in the following manner. Data on TPOS and TNEG (or TDATA) are

written into the jitter attenuator’s FIFO by TCLK. The rate at which data is r ead out of th e F I FO and transmitted is determined b y the oscillato r. Logic circuits adju st the ca pacitive loadin g on the crys-

Attenuation in dB

b) Maximum Attenuation Limit

1 10 100 1 k 10 k

Figure 10. Typical Jitter Attenuation Curve

a) Minimum Attenuation Limit

AT&T 62 41 1

Requirem ents

Measure d P er formance

Frequenc y in H z

tal to set its oscillation frequency to the average of the TCLK freque ncy. Signal jit ter is absorbed in the FIFO.

Jitter Tolera nce of Jitter Attenuator

The FIFO in the jitter attenuator is designed to neither overflow nor underflow. If the jitter amplitude becomes very large, the read and write pointers may get very close together. Should the pointers attempt to cross, the oscillator’s divide by four circuit adj usts by performing a divide by 3 1/2 or divide by 4 1/2 to pre vent the overflow or underflow. When a divide by 3 1/2 or 4 1/2 occurs, the data bit will be driven on to the line either an eighth bit period early or an eighth bit period late.

When the T CLK frequency is close to th e center frequency of the crystal oscillator, the high frequency jitt er tolerance is 23 UI before the divide by 3 1/2 or 4 1/2 circuitry is activated. As the center frequency of the oscillator and the TCLK frequency deviat e from one anoth er, the jitter tolerance is reduced. As this frequency deviation becomes large, the maximum jitter tolerance at high frequencies is reduced to 12 UI before the underflow/overflow circuitry is activated. In application, it is unlikely that the oscillator center frequency will be precisely aligned with the

DS40F2 13

CS61535A

1 : 2

RTIP

Data Level Slicer

RRING

Edge

Detector

Figure 1 1. Re cei ver Bl oc k Di agr am

TCLK frequency due to allowable TCLK tolerance, part to part variations, crystal to crystal variations, and crystal temperature drift. The oscillator tends to trac k l ow freque ncy ji tter s o jitt er tolerance increases as ji tter frequency decreases.

The crystal frequ ency must be 4 times the nominal signal frequen cy: 6.176 MHz for 1.544 MHz operation; 8.192 MHz for 2.048 MHz applications. Internal capacitors load the crystal, controlling the oscillation frequency. The crystal must be des igned so that ove r operating temperature, the oscillator frequency range exceeds the system frequ ency tole rance. Cry stal Semicondu ctor offers the CXT6176 & CXT8192 crystals, which yield optimum performance with the CS61535A.

Transmit All Ones Select

The transmitter provides for all ones insertion a t the frequency of ACLKI. Transmit all ones is selected when TAOS goes high, and causes continuous ones to be transmitted on the line (TTIP and TRING). In this mode , the TPOS and TNEG (or TDATA) inputs are ignored. A TAOS request will be ignored if remote loopback is in effect. ACLKI jitte r will be attenuated. TAOS is

Data

Sampling

Clock

Extraction

Clock

Phase

Selector

Continuously

Calibrated

Delay Line

RPOS RNEG RCLK

ACLKI or Oscillator in Jitter Attenuator

not available on the CS61535A when ACLKI is grounded.

Receiver

The recei ver extracts da ta and clock f r om an AMI (Alternate Mark Inversion) coded signal and outputs clock an d synchronize d data. The re ceiver is sensitive to sign als over the entire range of cable lengths and requires no equalization or ALBO (Automatic L ine Build Out) c ircuits. The signal is received on bot h ends of a center-tapped, centergrounded transformer. The transformer is center-tapped on t he IC side. The clock and data recovery cir cuit ex ceeds th e jitte r toleran ce specifications of Publications 43802, 43801, 62411 amended, TR-TSY-000170, and CCITT REC. G.823.

A block diagram of the rec eiver is shown in Figure 11. The two leads of the transformer (RTIP and RRING) have oppo site polarity allowing the receiver to treat RTIP and RRING as unipolar signals. Comparators are used to detect pulses on RTIP and RRING. The compara tor threshold s are dynamically established at a percent of the peak level (50% of peak for E1, 6 5% of peak for T1; with the slicing level selected by LEN2/1/0).

14 DS40F2

CS61535A

The receiver us es an e dge detec tor and a con tinuously calibrated delay line to generate the recovered clock. The delay line div ides its refer-

ence clock, ACLKI or the jitter attenuator’s oscillator, into 13 equal divisions or phases . Continuous calib ration assures ti ming accuracy, even if temperature or power supply voltage fluctuate.

The leading edge of an incoming data pulse triggers the clock ph ase selector. The phase selector chooses one of the 13 avail able phases which th e delay line pro duces for each bit perio d. The output from the phase selector feeds the clock and data recovery circuits which generate the recovered clock and sample the incoming signal at appropriate intervals to recover the data. The jitter tolerance of the receiver exceeds that shown in Figure 12.

300

100

PEAK

JITTER

(unit intervals)

Figure 12 . In put J itt er Tol eran ce of Receiv er

10 1k 10k0 100 100k700

JITTER FREQUENCY (Hz)

300

the Host Mode, CLKE determines the clock polarity for which output data is stable and valid as shown in Table 5.

MODE

(pin 5)

LOW

(<0.2V)

HIGH

(>(V+) - 0.2V)

HIGH

(>(V+) - 0.2V)

MIDDLE

(2.5V)

X = Don’t care

Table 5. Data Ou tput/Cl ock Relati onship

CLKE

(pin 28)

XRPOS

LOW RPOS

HIGH RPOS

X RDA TA RCLK Falling

DATA CLOCK Clock Edge for

RNEG

SDO

RNEG

SDO

RCLK RCLK

RCLK RCLK SCLK

Valid Data

Rising Rising

Falling Falling

Falling

Rising

Jitter and R ecovered Clock

The CS61535A are designed for error free clock and data recovery from an AMI encoded data stream in the presence of m o re than 0.4 unit intervals of jitter at high frequency. The clock recovery circuit is also tolerant of long strings of zeros. The edge of an incoming data bit causes the circui try to choose a phase from the delay line which most closely corresponds with the arrival time of the data edge, and that clock phase triggers a pulse whi ch is typ ically 1 40 ns in d urat ion. This phase of the delay line will continue to be selected unt il a data bit a rrives which is clo ser to another of the 13 phases, causin g a new phase to be selected. The largest jump allowed along the delay line is six phases.

The CS61535A outputs a clock immediately upon power-up. The clock recovery circuit is calibrated, and the device will lock onto the AMI data input immediately. If loss of signal occurs, the RCLK frequency will equal the ACLKI frequency.

In the Hardware Mode , data at RPOS and RNEG is stable and may be sampled on the rising edge of the recovered clock. In the Exte nded Hardware Mode, data at RDATA is stable an d may be sampled on the fallin g edg e of the recov ered clock . In

When an i nput signal is jitter free, the phase selection will occasionally jump between two adjacent p hases resulting in RCLK jitte r with an amplitude of 1/13 UIpp . These single phase jumps are due to differences in frequ ency of the incoming data and the calibration clock input to ACLKI. For T1 operation of the CS61535A, the instantaneou s period can be 14/1 3 * 648 ns = 698 ns (1,662,769 Hz) or 12/13 * 648 ns = 598 ns (1,425,231 Hz) when adjacent clock phases are chosen. As long as the s ame phase is c hosen, the

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