Interface for T1 and E1 Applications
Provides Line Driver, Jitter Attenuator
••
and Clock Recovery Functions
Transmit Side Jitter Attenuation
••
Starting at 3 Hz, with > 300 UI of Jitter
Tolerance
B8ZS/HDB3/AMI Encoders/Decoders
••
Compatible with SONET, M13 , CCITT
••
G.742, and Other Asynchronous Muxes
50 mA Transmitter Short-Circuit
••
Current Limiting
General Description
The CS61305A combines the complete analog transmit
and receive line interface for T1 or E1 applications in a
low power, 28-pin device operating from a +5V supply.
The CS61305A is a pin-compatible replacement for the
LXT305A in most applications.
The CS61305A provides a transmitter jitter attenuator
making it ideal for use in asynchronous multiplexor
systems with gapped transmit clocks. The transmitter
features internal pulse shaping and a low impedance
output stage allowing the use of external resistors for
transmitter impedance matching. The receiver uses a
digital Delay-Locked-Loop clock and data recovery circuit which is continuously calibrated from a crystal
reference to provide excellent stability and jitter tolerance.
Applications
•
Interfacing network transmission equipment such as
SONET multiplexor and M13 to a DSX-1 cross connect.
TV+
Input Voltage, Any Pin(Note 1)V
Input Current, Any Pin(Note 2)I
Ambient Operating TemperatureT
Storage TemperatureT
in
in
A
stg
-
-
6.0
(RV+) + 0.3
RGND-0.3(RV+) + 0.3V
-1010mA
-4085
-65150
WARNING: Operations at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
Notes: 1. Excluding RTIP, RRING, which must stay within -6V to (RV+) + 0.3V.
2. Transient currents of up to 100 mA will not cause SCR latch-up. Also TTIP, TRING, TV+ and TGND
can withstand a continuous current of 100 mA.
RECOMMENDED OPERATING CONDITIONS
ParameterSymbolMinTypMaxUnits
DC Supply(Note 3) RV+, TV+4.755.05.25V
Ambient Operating TemperatureT
Power Consumption(Notes 4,5)P
Notes: 3. TV+ must not exceed RV+ by mor e than 0.3V.
4. Power consumption while driving line load over oper ating temperature range. Includes IC and load.
Digital input levels are within 10% of the supply rails and digital outputs are driving a 50 pF
capacitive load.
5. Assumes 100% ones density and maximum line length at 5.25V.
A
C
-402585
--350mW
V
V
°C
°C
°C
DIGITAL CHARACTERISTICS (TA = -40°C to 85°C; TV+, RV+ = 5.0V ±5%; GND = 0V)
1:1.26 transformer and 120Ω load
Load Presented To Transmitter Output(Note 10)-75Jitter Added by the Transmitter(Note 15)
10Hz - 8kHz
8kHz - 40kHz
10Hz - 40kHz
Broad Band
Power in 2kHz band about 772kHz(Notes 10, 16)12.61517.9dBm
Power in 2kHz band about 1.544MHz(Notes 10, 16)
(referenced to power in 2kHz band at 772kHz)
Positive to Negative Pulse Imbalance(Notes 10, 16)
T1, DSX-1
E1 amplitude at center of pulse
E1 pulse width at 50% of nominal amplitude
E1 Transmitter Return Loss(Notes 10, 16, 17)
51 kHz to 102 kHz
102 kHz to 2.048 MHz
2.048 MHz to 3.072 MHz
E1 Transmitter Short Circuit Current(Notes 10, 18)--50mA RMS
Notes: 10. Using a 0.47 µF capacitor in series with the primary of a tr ansformer recommended
in the Applications Section.
11. Pulse amplitude measured at the output of a 1:1 tr ansformer across a 75 Ω load for
line length setting LEN2/1/0 = 0/0/0.
12. Pulse amplitude measured at the output of a 1:1.26 tr ansformer across a 120 Ω load for line length
setting LEN2/1/0 = 0/0/0 or at the output of a 1:1 transformer across a 120 Ω load for LEN2/1/0 = 001.
13. Pulse amplitude measured at the output of a 1:1.15 tr ansformer across a 100 Ω load for
line length setting LEN2/1/0 = 0/1/0.
14. Pulse amplitude measured at the DSX-1 Cross -Connect across a 100 Ω load for all line length
settings from LEN2/1/0 = 0/1/1 to LEN2/1/0 = 1/1/1 using a 1:1.5 transformer.
15. Input signal to RTIP/RRING is jitter free. Values will reduce slightly if jitter free clock is input to TCLK.
16. Not production tested. Parameters guaranteed by design and characterization.
17. Return loss = 20 log
= impedance of line load. Measured with a repeating 1010 data pattern with LEN2/1/0 = 0/0/0
z
0
and a 1:2 transformer with two 9.4 Ω series res istors terminated by a 75Ω load,
or for LEN2/1/0 = 0/0/1 with a 1:2 transformer and two 15 Ω ser ies resistors terminated by a
120Ω load.
18. Measured broadband through a 0.5 Ω resistor across the secondary of the transmitter transformer
during the transmission of an all ones data pattern for LEN2/1/0 = 0/0/0 or 0/0/1with a 1:2 transformer
and the series resistors specified in Table A1.
ABS((z1 +z0)/(z1-z0)) where z1 = impedance of the transmitter, and
10
2.14
2.7
2.7
2.4
-0.237
-0.3
-
-
-
-
-29-38-dB
-
-5
-5
20
20
20
2.37
3.0
3.0
3.0
-
-
-
-
-
-
0.2
-
-
28
28
24
2.6
3.3
3.3
3.6
0.237
0.3
0.01
0.025
0.025
0.05
0.5
5
5
-
-
-
V
V
V
V
V
V
Ω
UI
UI
UI
UI
dB
%
%
dB
dB
dB
DS157PP33
CS61305A
ANALOG SPECIFICATIONS (TA = -40°C to 85°C; TV+, RV+ = 5.0V ±5%; GND = 0V)
T1, (FCC Part 68) and E1(Note 21)
Allowable Consecutive Zeros before LOS160175190bits
Receiver Input Jitter Tolerance(Note 22)
10kHz - 100kHz
2kHz
10Hz and below
Loss of Signal Threshold-0.30-V
Notes: 19. Attenuation measured with input jitter equal to 3/4 of measured jitter tolerance. Circuit attenuates
jitter at 20 dB/decade above the corner frequency. See Figure 10. Output jitter can increase
significantly when more than 12 UI’s are input to the attenuator. See discussion in the text section.
20. For input amplitude of 1.2 V
21. For input amplitude of 1.05 V
to 4.14 Vpk.
pk
to 3.3 Vpk.
pk
22. Jitter tolerance increases at lower frequencies. See Figure 12.
Rise Time, All Digital Outputs(Note 26)t
Fall Time, All Digital Outputs(Note 26)t
TCLK Frequencyf
TCLK Pulse Width(Notes 16, 27, 28)
c
pwh3/tpw3
aclki
pw1
t
pwh1
t
pwl1
r
f
tclk
t
pwh2
(Notes 29, 30)
TPOS/TNEG (TDATA) to TCLK Falling Setup Timet
TCLK Falling to TPOS/TNEG (TDATA) Hold Timet
RPOS/RNEG Valid Before RCLK Falling(Note 27)t
RDATA Valid Before RCLK Falling(Note 29)t
RPOS/RNEG Valid Before RCLK Rising(Note 28)t
RPOS/RNEG Valid After RCLK Falling(Note 27)t
RDATA Valid After RCLK Falling(Note 29)t
RPOS/RNEG Valid After RCLK Rising(Note 28)t
su2
h2
su1
su1
su1
h1
h1
h1
Notes: 23. Crystal must meet specifications described in CXT6176/CXT8192 data sheet.
24. ACLKI provided by an external source or TCLK but not RCLK.
25. RCLK duty cycle will vary with extent by which pulses are displaced by jitter. Specified under worst
case jitter conditions: 0.4 UI AMI data displacement for T1 and 0.2 UI AMI data displacement for E1.
Key Enhancements of the CS61305A Relative
to the LXT305A
•12.5% lower power consumption,
•50 mA
transmitter short-circuit current
RMS
limiting for E1 (per OFTEL OTR-001),
•Optional AMI, B8ZS, HDB3 encoder/de-
coder or external line coding support,
•Receiver AIS (unframed all ones) detection,
•Improved receiver Loss of Signal handling
(LOS set at power-up, reset upon receipt of
3 ones in 32 bit periods with no more than
15 consecutive zeros),
•Transmitter TTIP and TRING outputs are
forced low when TCLK is static.
Introduction to Operating Modes
The CS61305A supports three operating modes
which are selected by the level of t he MODE pin
as shown in Tables 1 and 2, Figure 7, and Figures
A1-A3 of the Applications section.
There are thirteen multi-function pins whose
functionality is determined by the operating
mode. (see Table 2). The modes are Hardware
Mode, Extended Hardware Mode, and Host
Mode. In Hardware and Extended Hardware
Modes, discrete pins are used to configure and
monitor the device. The Extended Hardware
Mode provides a parallel chip select input which
latches the control inputs allowing individual ICs
to be configured using a common set of control
lines. In the Host Mode, an external processor
monitors and configures the device through a serial interface.
The transmitter takes digital T1 or E1 input data
and drives appropriately shaped bipolar pulses
onto a transmission line. The transmit data (TPOS
& TNEG or TDATA) is supplied synchronously
and sampled on the falling edge of the input
clock, TCLK.
Either T1 (DSX-1 or Network Interface) or E1
CCITT G.703 pulse shapes may be selected.
Pulse shaping and signal level are controlled by
"line length select" inputs as shown in Table 3.
The output options in Table 3 are specified with a
1:1.15 transmitter transformer turns ratio for T1
and a 1:1 turns ratio for E1 without external series resistors. Other turns ratios may be used if
approriate resistors are placed in series with the
TTIP and TRING pins. Table A1 in the applications section lists other combinations which can
be used to provide transmitter impedance matching.
For T1 DSX-1 applications, line lengths from 0 to
655 feet (as measured from the transmitter to the
DSX-1 cross connect) may be selected. The five
partition arrangement in Table 3 meets ANSI
T1.102-1993 and AT&T CB-119 requirements
when using #22 ABAM cable. A typical output
pulse is shown in Figure 8. These pulse settings
can also be used to meet CCITT pulse shape requirements for 1.544 MHz operation.
LEN2 LEN1 LEN0Option SelectedApplication
0110-133 ft
100133-266 ft
101266-399 ft
110399-533 ft
111533-655 ft
000
001
010FCC PART 68, OPT. ANetwork
011ANSI T1.403
Table 3. Line Length Selection
75Ω coax
120Ω twisted-pair
DSX-1
ABAM
(AT&T 600B
or 600C)
E1
CCITT G.703
Interface
The CS61305A transmitter provides short-circuit
current limiting protection and meets OFTEL
OTR-001 short-circuit current limiting requirements for E1 applications.
The CS61305A will detect a static TCLK, and
will force TTIP and TRING low to prevent transmission when data is not present. When any
transmit control pin (TAOS, LEN0-2 or LLOOP)
is toggled, the transmitter outputs will require approximately 22 bit periods to stabilize. The
transmitter will take longer to stabilize when
RLOOP is selected because the timing circuitry
must adjust to the new frequency.
NORMALIZED
AMPLITUDE
1.0
ANSI T1.102,
AT&T CB 119
SPECIFICATIONS
For T1 Network Interface applications, two additional options are provided. Note that the optimal
0.5
pulse width for Part 68 (324 ns) is narrower than
the optimal pulse width for DSX-1 (350 ns). The
CS61305A automatically adjusts the pulse width
based upon the "line length" selection made.
The E1 G.703 pulse shape is supported with line
length selections LEN2/1/0 = 0/0/0 and 0/0/1.
The pulse width will meet the G.703 pulse shape
template shown in Figure 9, and specified in Table 4.
10DS157PP3
0
OUTPUT
PULSE SHAPE
-0.5
02507501000
Figure 8. Typical Pulse Shape at DSX-1 Cross Connect
500
TIME (nanoseconds)
120
110
100
90
80
50
Percent of
nominal
peak
voltage
269 ns
244 ns
194 ns
Attenuation in dB
0
10
20
30
40
50
CS61305A
a) Minimum Attenuation Limit
AT&T 62411
Requirements
b) Maximum
Attenuation
Limit
-10
-20
10
0
219 ns
488 ns
Nominal Pulse
Figure 9. Mask of the Pulse at the 2048 kbps Interface
Transmit All Ones Select
The transmitter provides for all ones insertion at
the frequency of ACLKI. Transmit all ones is selected when TAOS goes high, and causes
continuous ones to be transmitted on the line
(TTIP and TRING). In this mode, the TPOS and
TNEG (or TDATA) inputs are ignored. A TAOS
request will be ignored if remote loopback is in
effect. ACLKI jitter will be attenuated. TAOS is
not available on the CS61305A when ACLKI is
grounded.
60
1101001 k10 k
Frequency in Hz
Measured Performance
Figure 10. Typical Jitter Attenuation Curve
Jitter Attenuator
The jitter attenuator is designed to reduce wander
and jitter in the transmit clock signal. It consists
of a 192 bit FIFO, a crystal oscillator, a set of
load capacitors for the crystal, and control logic.
The jitter attenuator exceeds the jitter attenuation
requirements of Publications 43802 and REC.
G.742. A typical jitter attenuation curve is shown
in Figure 10.
The jitter attenuator works in the following manner. Data on TPOS and TNEG (or TDATA) are
For coaxial cable,
75Ω load and
transformer specified
in Application Section.
For shielded twisted
pair, 120Ω load and
transformer specified
in Application Section.
Nominal peak voltage of a mark (pulse)2.37 V3 V
Peak voltage of a space (no pulse)
0 ±0.237 V0 ±0.30 V
Nominal pulse width244 ns
Ratio of the amplitudes of positive and negative
pulses at the center of the pulse interval
Ratio of the widths of positive and negative
pulses at the nominal half amplitude
0.95 to 1.05*
0.95 to 1.05*
* When configured with a 0.47 µF nonpolarized capacitor in series with the TX transformer
primary as shown in Figures A1, A2 and A3.
Table 4. CCITT G.703 Specifications
DS157PP311
CS61305A
written into the ji tt er at tenu at o r’s FIFO by TCLK.
The rate at which data is read out of the FIFO and
transmitted is determined by the oscillator. Logic
circuits adjust the capacitive loading on the crystal to set its oscillation frequency to the average
of the TCLK frequency. Signal jitter is absorbed
in the FIFO.
Jitter Tolerance of Jitter Attenuator
The FIFO in the jitter attenuator is designed to
neither overflow nor underflow. If the jitter amplitude becomes very large, the read and write
pointers may get very close together. Should the
pointers attempt to cross, the oscillator’s divide
by four circuit adjusts by performing a divide by
3 1/2 or divide by 4 1/2 to prevent the overflow
or underflow. When a divide by 3 1/2 or 4 1/2
occurs, the data bit will be driven on to the line
either an eighth bit period early or an eighth bit
period late.
The FIFO of the jitter attenuator in the transmit
path is 192 bits deep. This FIFO will typically be
near the half full point under normal operating
conditions, buffering about 96 bits of data. The
number of bits actually buffered depends on the
relationship of the nominal TCLK frequency to
the center frequency of the crystal oscillator. As
these frequencies deviate, a few bits of FIFO
depth will be lost.
TCLK can have gaps or bursts. As long as the gap
or burst is less than the remaining FIFO depth,
normal operation will continue. For example, if
the nominal TCLK frequency was less than the
oscillator’s center frequency by 40 Hz. The FIFO
will operate 3-4 bits off center or 92 bits full. A
gap in TCLK of 80 cycles would empty the FIFO
by 80 bits but would still not envoke the divide
by 4 1/2 circuitry, as about 12 bits would remain
in the FIFO.
The crystal frequency must be 4 times the nominal signal frequency: 6.176 MHz for 1.544 MHz
operation; 8.192 MHz for 2.048 MHz applica-
tions. Internal capacitors load the crystal, controlling the oscillation frequency. The crystal must be
designed so that over operating temperature, the
oscillator frequency range exceeds the system frequency tolerance. Crystal Semiconductor offers
the CXT6176 & CXT8192 crystals, which yield
optimum performance with the CS61305A.
Receiver
The receiver extracts data and clock from an AMI
(Alternate Mark Inversion) coded signal and outputs clock and synchronized data. The receiver is
sensitive to signals over the entire range of cable
lengths and requires no equalization or ALBO
(Automatic Line Build Out) circuits. The signal is
received on both ends of a center-tapped, centergrounded transformer. The transformer is
center-tapped on the IC side. The clock and data
recovery circuit exceeds the jitter tolerance specifications of Publications 43802, 43801, 62411
amended, TR-TSY-000170, and CCITT REC.
G.823.
A block diagram of the receiver is shown in Figure 11. The two leads of the transformer (RTIP
and RRING) have opposite polarity allowing the
receiver to treat RTIP and RRING as unipolar signals. Comparators are used to detect pulses on
RTIP and RRING. The comparator thresholds are
dynamically established at a percent of the peak
level (50% of peak for E1, 65% of peak for T1;
with the slicing level selected by LEN2/1/0).
The receiver uses an edge detector and a continuously calibrated delay line to generate the
recovered clock. The delay line divides its reference clock, ACLKI or the jitter attenuator’s
oscillator, into 13 equal divisions or phases. Continuous calibration assures timing accuracy, even
if temperature or power supply voltage fluctuate.
The leading edge of an incoming data pulse triggers the clock phase selector. The phase selector
chooses one of the 13 available phases which the
delay line produces for each bit period. The out-
12DS157PP3
CS61305A
RTIP
1 : 2
RRING
Data
Level
Slicer
Edge
Detector
Figure 11. Receiver Block Dia gram
put from the phase selector feeds the clock and
data recovery circuits which generate the recovered clock and sample the incoming signal at
appropriate intervals to recover the data. The jitter
tolerance of the receiver exceeds that shown in
Figure 12.
The CS61305A outputs a clock immediately upon
power-up and will lock onto the AMI data input
immediately. If loss of signal occurs, the RCLK
frequency will equal the ACLKI frequency.
Data
Sampling
&
Clock
Extraction
Clock
Phase
Selector
Continuously
Calibrated
Delay Line
RPOS
RNEG
RCLK
ACLKI or
Oscillator in Jitter
Attenuator
In the Hardware Mode, data at RPOS and RNEG
is stable and may be sampled on the rising edge
of the recovered clock. In the Extended Hardware
Mode, data at RDATA is stable and may be sampled on the fallings edge of the recovered clock.
In the Host Mode, CLKE determines the clock
polarity for which output data is stable and valid
as shown in Table 5.
Jitter and Recovered Clock
The CS61305A is designed for error free clock
and data recovery from an AMI encoded data
Minimum
Performance
101k10k1100100k700
JITTER FREQUENCY(Hz)
300
PEAK-TO-PEAK
JITTER
(unit intervals)
300
138
100
AT&T 62411
28
10
1
.4
.1
Figure 12. Minimum Input Jitter Tolerance of Receiver
MODE
(pin 5)
LOW
(<0.2V)
HIGH
(>(V+) - 0.2V)
HIGH
(>(V+) - 0.2V)
MIDDLE
(2.5V)
X = Don’t care
Table 5. Data Output/Clock Relationship
CLKE
(pin 28)
XRPOS
LOWRPOS
HIGHRPOS
DATACLOCKClock Edge
for Valid Data
RCLK
RNEG
RCLK
RCLK
RNEG
SDO
RCLK
SCLK
RCLK
RNEG
SDO
RCLK
SCLK
XRDATARCLKFalling
Rising
Rising
Rising
Rising
Falling
Falling
Falling
Rising
DS157PP313
CS61305A
stream in the presence of more than 0.4 unit intervals of jitter at high frequency. The clock
recovery circuit is also tolerant of long strings of
zeros. The edge of an incoming data bit causes
the circuitry to choose a phase from the delay line
which most closely corresponds with the arrival
time of the data edge, and that clock phase triggers a pulse which is typically 140 ns in duration.
This phase of the delay line will continue to be
selected until a data bit arrives which is closer to
another of the 13 phases, causing a new phase to
be selected. The largest jump allowed along the
delay line is six phases.
When an input signal is jitter free, the phase selection will occasionally jump between two
adjacent phases resulting in RCLK jitter with an
amplitude of 1/13 UIpp. These single phase
jumps are due to differences in frequency of the
incoming data and the calibration clock input to
ACLKI. For T1 operation the instantaneous period can be 14/13 * 648 ns = 698 ns or 12/13 *
648 ns = 598 ns when adjacent clock phases are
chosen. As long as the same phase is chosen, the
period will be 648 ns. Similar calculations hold
for the E1 rate.
The clock recovery circuit is designed to accept at
least 0.4 UI of jitter at the receiver. Since the data
stream contains information only when ones are
transmitted, a clock/data recovery circuit must assume a zero when no signal is measured during a
bit period. Likewise, when zeros are received, no
information is present to update the clock recovery circuit regarding the trend of a signal which is
jittered. The result is that two ones that are separated by a string of zeros can exhibit maximum
deviation in pulse arrival time. For example, one
half of a period of jitter at 100 kHz occurs in 5
µs, which is 7.7 T1 bit periods. If the jitter amplitude is 0.4 UI, then a one preceded by seven zeros
can have maximum displacement in arrival time,
i.e. either 0.4 UI too early or 0.4 UI too late. The
data recovery circuit correctly assigns a received
bit to its proper clock period if i t is displaced by
less than 6/13 of a bit period from its optimal location. Theoretically, this would give a jitter
tolerance of 0.46 UI. The actual jitter tolerance of
the CS61305A is only slightly less than the ideal.
In the event of a maximum jitter hit, the RCLK
clock period immediately adjusts to align itself
with the incoming data and prepare to accurately
place the next one, whether it arrives one period
later, or after another string of zeros and is displaced by jitter. For a maximum early jitter hit,
RCLK will have a period of 7/13 * 648 ns = 349
ns. For a maximum late jitter hit, RCLK will have
a period of 19/13 * 648 ns = 947 ns.
Loss of Signal
Receiver loss of signal is indicated upon receiving 175 consecutive zeros. A digital counter
counts received zeros based on RCLK cycles. A
zero input is determined either when zeros are received, or when the received signal amplitude
drops below a 0.3 V peak threshold.
The receiver reports loss of signal by setting the
Loss of Signal pin, LOS, high. If the serial interface is used, the LOS bit will be set and an
interrupt issued on INT. LOS will go low (and
flag the INT pin again if serial I/O is used) when
a valid signal is detected. Note that in the Host
Mode, LOS is simultaneously available from both
the register and pin 12.
In a loss of signal state, the RCLK frequency will
be equal to the ACLKI frequency since ACLKI is
being used to calibrate the clock recovery circuit.
Received data is output on RPOS/RNEG regardless of LOS status. LOS returns to logic zero
when 3 ones are received out of 32 bit periods
containing no more than 15 consecutive zeros.
Also, a power-up or manual reset will set LOS
high.
14DS157PP3
CS61305A
Local Loopback
Local loopback is selected by taking LLOOP, pin
27, high or by setting the LLOOP register bit via
the serial interface.
The local loopback mode takes clock and data
presented on TCLK, TPOS, and TNEG (or
TDATA), and outputs it at RCLK, RPOS and
RNEG (or RDATA). Inputs to the transmitter are
still transmitted on TTIP and TRING, unless
TAOS has been selected in which case, AMIcoded continuous ones are transmitted at the
TCLK frequency. The receiver RTIP and RRING
inputs are ignored when local loopback is in effect. The jitter attenuator is not in the local loop
back path.
Remote Loopback
Remote loopback is selected by taking RLOOP,
pin 26, high or by setting the RLOOP register bit
via the serial interface.
In remote loopback, the recovered clock and data
input on RTIP and RRING are sent through the
jitter attenuator and back out on the line via TTIP
and TRING. Selecting remote loopback overrides
any TAOS request (see Table 7). The recovered
RLOOP
Input
Signal
Notes: 1. X = Don’t Care. The identified All Ones Select
input is ignore d when the indi cated loop back is
in effect.
2. Logic 1 indicates that Loopb ack or All Ones
option is se lected .
Table 7. Interaction of RLOOP with TAOS
Source of
Data for
TTIP & TRING
Source of
Clock for
TTIP & TRING
incoming signals are also sent to RCLK, RPOS
and RNEG (or RDATA). A remote loopback occurs in response to RLOOP going high.
Simultaneous selection of local and remote loopback modes is not valid (see Reset).
In the Extended Hardware Mode the transmitted
data is looped before the AMI/B8ZS/HDB3 encoder/decoder during remote loopback so that the
transmitted signal matches the received signal,
even in the presence of received bipolar violations. Data output on RDATA is decoded,
however, if RCODE is low.
Driver Performance Monitor
To aid in early detection and easy isolation of
non-functioning links, the IC is able to monitor
transmit drive performance and report when the
driver is no longer operational. This feature can
be used to monitor either the device’s performance or the performance of a neighboring driver.
The driver performance monitor indicator is normally low, and goes high upon detecting a driver
failure.
The driver performance monitor consists of an activity detector that monitors the transmitted signal
when MTIP is connected to TTIP and MRING is
connected to TRING. DPM will go high if the
absolute difference between MTIP and MRING
does not transition above or below a threshold
level within a time-out period. In the Host Mode,
DPM is available from both the register and pin
11.
Whenever more than one line interface IC resides
on the same circuit board, the effectiveness of the
driver performance monitor can be maximized by
having each IC monitor performance of a neighboring IC, rather than having it monitor its own
performance.
DS157PP315
CS61305A
LEN 2/1/0
000010-111
TCODE
(Transmit
Encoder
Selection)
RCODE
(Receiver
Decoder
Selection)
Table 8. Encoder/Decoder Selection
LOW
HIGHAMI Encoder
LOW
HIGHAMI Decoder
HDB3
Encoder
HDB3
Decoder
B8ZS
Encoder
B8ZS
Decoder
Alarm Indication Signal
In the Extended Hardware Mode, the receiver sets
the output pin AIS high when unframed all-ones
condition (blue alarm) is detected using the criteria of less than 3 zeros out of 2048 bit periods.
Line Code Encoder/Decoder
In the Extended Hardware Mode, three line codes
are available: AMI, B8ZS and HDB3. The input
to the encoder is TDATA. The outputs from the
decoder are RDATA and BPV (Bipolar Violation
Strobe). The encoder and decoder are selected
using the LEN2, LEN1, LEN0, TCODE and
RCODE pins as shown in Table 8.
Parallel Chip Select
In the Extended Hardware Mode, PCS can be
used to gate the digital control inputs: TCODE,
RCODE, LEN0, LEN1, LEN2, RLOOP, LLOOP
and TAOS. Inputs are accepted on these pins only
when PCS is low and will immediately change
the operating state of the device. Therefore, when
cycling PCS to update the operating state, the
digital control inputs should be stable for the entire PCS low period. The digital control inputs are
ignored when PCS is high.
Power On Reset / Res et
Upon power-up, the IC is held in a static state
until the supply crosses a threshold of approximately 3 Volts. When this threshold is crossed,
the device will delay for about 10 ms to allow the
power supply to reach operating voltage. After
this delay, calibration of the delay lines used in
the transmit and receive sections commences. The
delay lines can be calibrated only if a reference
clock is present. The reference clock for the receiver is provided by ACLKI, or the crystal
oscillator. The reference clock for the transmitter
is provided by TCLK. The initial calibration
should take less than 20 ms.
In operation, the delay lines are continuously calibrated, making the performance of the device
independent of power supply or temperature variations. The continuous calibration function
eliminates any requi rement to reset the line in terface when in operation. However, a reset function
is available which will clear all registers.
In the Hardware and Extended Hardware Modes,
a reset request is made by simultaneously setting
both the RLOOP and LLOOP pins high for at
least 200 ns. Reset will initiate on the falling edge
of the reset request (falling edge of RLOOP and
LLOOP). In the Host Mode, a reset is initiated by
simultaneously writing RLOOP and LLOOP to
the register. In either mode, a reset will set all registers to 0 and force the oscillator to its center
frequency before initiating calibration. A reset
will also set LOS high.
Serial Interface
In the Host Mode, pins 23 through 28 serve as a
microprocessor/microcontroller interface. One
on-board register can be written to via the SDI
pin or read from via the SDO pin at the clock rate
determined by SCLK. Through this register, a
16DS157PP3
CS
SCLK
CS61305A
SDI
SDO
R/W
0D7D6D5D4D3D2D1D0
0
Address/Command Byte
0001X
Figure 13. Input/Output Timing
host controller can be used to control operational
characteristics and monitor device status. The serial port read/write timing is independent of the
system transmit and receive timing.
Data transfers are initiated by taking the chip select input, CS, low (CS must initially be high).
Address and input data bits are clocked in on the
rising edge of SCLK. The clock edge on which
output data is stable and valid is determined by
CLKE as shown in Table 5. Data transfers are terminated by setting CS high. CS may go high no
sooner than 50 ns after the rising edge of the
SCLK cycle corresponding to the last write bit.
For a serial data read, CS may go high any time
to terminate the output.
Figure 13 shows the timing relationships for data
transfers when CLKE = 1. When CLKE = 1, data
bit D7 is held until the falling edge of the 16th
clock cycle. When CLKE = 0, data bit D7 is held
until the rising edge of the 17th clock cycle. SDO
goes to the high impedance state when the serial
port is being written (R/W = 0), or if CS goes
high, or at the end of the hold period of data bit
D7.
An address/command byte, shown in Table 9,
precedes the data byte. The first bit of the address/command byte determines whether a read
or a write is requested. The next six bits contain
the address. The line interface responds to address
16 (0010000). The last bit is ignored.
Data Input/Output
D6D5D4D3D2D1D0D7
BitD esignationDescription
0R/WRead/Write Select; 0 = write, 1 = read
1ADD0LSB of address, Must be 0
2ADD1Must be 0
3ADD2Must be 0
4ADD3Must be 0
5ADD4Must be 1
6-Reserved - Must be 0
7XDon’t Care
Note: Bit 0 is the first bit input (LSB).
Table 9. Address/Command Byte
During a write cycle (R/W = 0), data is written to
the input data register on the eight clock cycles
immediately following the address/command
byte. The input data format over SDI is shown in
Table 10.
BitDesignationDescription
D0clr LOSClear Loss of Signal
D1clr DPMClear Driver Performance Monitor
D2LEN0Bit 0 - Line Length Select
D3LEN1Bit 1 - Line Length Select
D4LEN2Bit 2 - Line Lenght Select
D5RLOOPRemote Loopback
D6LLOOPLocal Loopback
D7TAOST ransm it All O nes Select
Note: Bit D0 is the first bit input (LSB).
Table 10. Input Data Register
Bits D0 and D1 are used to clear an interrupt issued from the INT pin, which occurs in response
to a loss of signal or a problem with the output
driver.
Writing a "1" to either "Clear LOS" or "Clear
DPM" over the serial interface has three effects:
DS157PP317
CS61305A
1) The current interrupt on the serial interface
will be cleared. (Note that simply reading
the register bits will not clear the interrupt).
2) Output data bits D5, D6 and D7 will be reset as appropriate.
3) Future interrupts for the corresponding LOS
or DPM will be prevented from occurring.
Writing a "0" to either "Clear LOS" or "Clear
DPM" enables the corresponding interrupt for
LOS or DPM.
BitDesignationDescription
D0LOSLoss of Signal
D1DPMDriver Performance Monitor
D2LEN0Bit 0 - Line Length Select
D3LEN1Bit 1 - Line Length Select
D4LEN2Bit 2 - Line Lenght Select
Note: Bit D0 is the first bit output (LSB)
Table 11. Output Data Register (bits D0-D4)
During a read cycle (R/W = 1), data is read from
the output data register on the eight clock cycles
immediately following the address/ command
byte. The output data format over SDO is shown
in Tables 11 and 12.
Bits D2, D3 and D4 can be read to verify line
length selection. Bits D5, D6 and D7 must be decoded according to Table 12. Codes 101, 110 and
111 (Bits D5, D6 and D7) indicate intermittent
losses of signal and/or driver problems.
Bits
D5D6D7
0 0 0 Reset has occurred or no program input.
0 0 1 TAOS in effect.
0 1 0 LLOOP in effect.
0 1 1 TAOS/LLOOP in effect.
1 0 0 RLOOP in effect
1 0 1 DPM changed state since last "clear DPM"
occured.
1 1 0 LOS changed state since last "clear LOS"
occured.
1 1 1 LOS and DPM have changed state since
last "clear LOS" and "clear DPM".
Table 12. Output Data Register (bits D5-D7)
Status
respective grounds. TV+ must not exceed RV+ by
more than 0.3V.
Decoupling and filtering of the power supplies is
crucial for the proper operation of the analog circuits in both the transmit and receive paths. A 1.0
µF capacitor should be connected between TV+
and TGND, and a 0.1 µF capacitor should be con-
nected between RV+ and RGND. Use mylar or
ceramic capacitors and place them as closely as
possible to their respective power supply pins. A
68 µF tantalum capacitor should be added close
to the RV+/RGND supply. Wire-wrap breadboarding of the line interface is not recom mended
because lead resistance and inductance serve to
defeat the function of the decoupling capacitors.
The SDO pin goes to a high impedance state
when not in use. The SDO and SDI pins may be
Schematic & Layout Review Service
tied together in applications where the host processor has a bi-directional I/O port.
Power Supply
The device operates from a single +5 Volt supply.
Separate pins for transmit (TV+, TGND) and receive (RV+, RGND) supplies provide internal
isolation. These pins should be connected exter-
Confirm Optimum
Schematic & Layout
Before Building Your Board.
For Our Free Review Service
Call Applications Engineering.
Power supply ground for all subcircuits except the transmit driver; typically 0 Volts.
RV+ - Power Supply, Pin 21.
Power supply for all subcircuits except the transmit driver; typically +5 Volts.
TGND - Ground, Transmit Driver, Pin 14.
Power supply ground for the transmit driver; typically 0 Volts.
TV+ - Power Supply, Transmit Driver, Pin 15.
Power supply for the transmit driver; typically +5 Volts. TV+ must not exceed RV+ by more than
0.3 V.
Oscillator
XTALIN, XTALOUT - Crystal Connections, Pins 9 and 10.
A 6.176 MHz (T1 operation) or 8.192 MHz (E1 operation) crystal should be connected across
these pins. Overdriving the oscillator with an external clock is not supported.
CS61305A
Control
ACLKI - Alternate External Clock Input, Pin 1.
A 1.544 MHz or 2.048 MHz clock signal may be input on ACLKI to calibrate the clock recovery
circuit and control the transmit clock during TAOS. If a clock is not provided on ACLKI, this
input must be grounded, and the oscillator in the jitter attenuator is used to calibrate the clock
recovery circuit and TAOS is not available. ACLKI may not be provided by RCLK.
CLKE - Clock Edge, Pin 28. (Host Mode)
Setting CLKE to logic 1 causes RPOS and RNEG to be valid on the falling edge of RCLK, and
SDO to be valid on the rising edge of SCLK. Conversely, setting CLKE to logic 0 causes RPOS
and RNEG to be valid on the rising edge of RCLK, and SDO to be valid on the falling edge of
SCLK.
CS - Chip Select, Pin 26. (Host Mode)
This pin must transition from high to low to read or write the serial port.
INT - Receive Alarm Interrupt, Pin 23. (Host Mode)
Goes low when LOS or DPM change state to flag the host processor. INT is cleared by writing
"clear LOS" or "clear DPM" t o the regi ster. INT is an open drain output and should be tied to the
power supply through a resistor (47k - 100k).
20DS157PP3
CS61305A
LEN0, LEN1, LEN2 - Line Length Selection, Pins 23, 24 and 25. (Hardware and Extended
Hardware Modes)
Determines the shape and amplitude of the transmitted pulse to accommodate several cable types
and lengths. See Table 3 for information on line length selection. These pins also control the
receiver slicing level.
LLOOP - Local Loopback, Pin 27. (Hardware and Extended Hardware Modes)
Setting LLOOP to a logic 1 routes the transmit clock and data through to the receive clock and
data pins. TPOS/TNEG (or TDATA) are still transmitted unless overridden by a TAOS request.
Inputs on RTIP and RRING are ignored during LLOOP. The jitter attenuator is bypassed.
Simultaneously taking RLOOP and LLOOP high for at least 200 ns initiates a device reset.
MODE - Mode Select, Pin 5.
Driving the MODE pin high places the line interface in the Host Mode. In the Host mode, a serial
control port is used to control the line interface and determine its status. Grounding the MODE
pin places the line interface in the Hardware Mode, where configuration and status are controlled
by discrete pins. Floating the MODE pin or driving it to +2.5 V places the device in Extended
Hardware Mode, where configuration and status are controlled by discrete pins. When floating
MODE, there should be no external load on the pin. MODE defines the status of 13 pins (see
Table 2).
Setting RLOOP to a logic 1 causes the recovered clock and data to be sent through the jitter
attenuator and through the driver back to the line. The recovered signal is also sent to RCLK and
RPOS/RNEG (or RDATA). Any T AOS reques t is ignored.
Simultaneously taking RLOOP and LLOOP high for at least 200 ns initiates a device reset.
SCLK - Serial Clock, Pin 27. (Host Mode)
Clock used to read or write the serial port registers. SCLK can be either high or low when the line
interface is selected using the CS pin.
SDI - Serial Data Input, Pin 24. (Host Mode)
Input for the input data register. Sampled on the rising edge of SCLK.
DS157PP321
CS61305A
SDO - Serial Data Output, Pin 25. (Host Mode)
Status and control output from the output data register. If CLKE is high SDO is valid on the
rising edge of SCLK. If CLKE is low SDO is valid on the falling edge of SCLK. This pin goes to
a high-impedance state when the serial port is being written, or if CS is high, or after bit D7 is
output.
TAOS - Transmit All Ones Select, Pin 28. (Hardware and Extended Hardware Modes)
Setting TAOS to a logic 1 causes continuous ones to be transmitted at the frequency determined
by ACLKI.
Setting TCOD E low en ables B8ZS or HDB3 zero substi tution in the transmitter en coder. Setting
TCODE high enables the AMI transmitter encoder .
Data
RCLK - Recovered Clock, Pin 8.
The receiver recovered clock is output on this pin.
RDATA - Receive Data - Pin 7. (Extended Hardware Mode)
Data recovered from the RTIP and RRING inputs is output in NRZ format at this pin, after being
decoded by the line code decoder. RDATA is stable and valid on the falling edge of RCLK.
RPOS, RNEG - Receive Positive Data, Receive Negative Data, Pins 6 and 7. (Hardware and
Host Modes)
The receiver recovered NRZ digital data from RTIP and RRING is output on these pins. A
positive pulse (with respect to ground) received on the RTIP pin generates a logic 1 on RPOS,
and a positive pulse (with respect to ground) received on the RRING pin generates a logic 1 on
RNEG. In the Hardware Mode, RPOS and RNEG are stable and valid on the rising edge of
RCLK. In the Host Mode, CLKE determines the clock edge for which RPOS and RNEG are
stable and valid (see Table 5).
The AMI receive signal is input on these pins. A center-tapped, center-grounded, 2:1, step-up
transformer is required on these inputs, as shown in Figure A1 of the Applications section. Clock
and data are recovered and output on RCLK and RPOS/RNEG or RDATA.
TCLK - Transmit Clock, Pin 2.
The1.544 MHz (T1 operation) or 2.048 MHz (E1 operation) transmit clock is input on this pin.
TPOS/TNEG or TDATA are sampled on the falling edge of TCLK.
Data to be transmitted by the TTIP and TRING outputs is input in NRZ format at this pin, after
being encoded by the line code encoder. TDATA is sampled on the falling edge of TCLK.
22DS157PP3
CS61305A
TPOS, TNEG - Transmit Positive Data, Transmit Negative Data, Pins 3 and 4. (Hardware and
Host Modes)
The transmit NRZ digital data to TTIP and TRING is input on these pins. A logic 1 on TPOS
causes a positive pulse (with respect to ground) to be transmitted on the TTIP pin, and a logic 1
on TNEG causes a negative pulse (with respect to ground) to be transmitted on the TRING pin.
TPOS and TNEG are sampled on the falling edge of TCLK.
The AMI signal is driven to the line through these pins. This output is designed to drive a 75 Ω
load. A transformer is required as shown in Figure A1 of the Applications section. Clock and data
are sourced on TCLK and TPOS/ TNEG or TDATA.
AIS goes high when unframed all-ones condition (blue alarm) is detected, using the detection
criteria of less than three zeros out of 2048 bit periods.
BPV strobes high when a bipolar violation is detect ed in the received signal. B8ZS (or HDB3)
zero substitutions are not flagged as bipolar violations if the B8ZS (or HDB3) decoder has been
enabled.
DPM goes high if no activity is detected on MTIP and MRING.
LOS - Loss of Signal, Pin 12.
LOS goes high when 175 consecutive zeros have been received. LOS returns low when 3 ones
are received within 32 bit periods containing no more than 15 consecutive zeros.
MTIP, MRING - Monitor Tip, Monitor Ring, Pins 17 and 18. (Hardware and Host Modes)
These pins are normally connected to TTIP and TRING and monitor the transmitter output. If the
INT pin in the Host mode is used, and the monitor is not used, writing a "1" to the "clear DPM"
bit will prevent an interrupt from the driver performance monitor.
DS157PP323
CS61305A
15
14
E1
28 pin
Plastic DIP
A
L
A1
B
∝∝
eA
SEATING
PLANE
B1
28
1
D
e1
NOTES:
1. POSITIONAL TOLERANCE OF LEADS SHALL BE WITHIN
0.25mm (0.010") AT MAXIMUM MATERIAL CONDITION, IN
RELATION TO SEATING PLANE AND EACH OTHER.
2. DIMENSION eA TO CENTER OF LEADS WHEN FORMED PARALLEL.
3. DIMENSION E1 DOES NOT INCLUDE MOLD FLASH.
28-pin PLCC
MILLIMETERS
DIM
MIN
3.94
A
0.51
A1
0.36
B
1.02
B1
0.20
C
36.45
D
E1
13.72
e1
2.41
eA
C
L
∝∝
15.24
3.18
0°
MAX
NOM
4.32
5.08
0.76
1.02
0.46
0.56
1.27
1.65
0.25
0.38
36.83
37.21
13.97
14.22 0.540
2.54
2.670.095
15.870.625
-
-
3.81
-
15°
INCHES
MINMAX
NOM
0.170
0.030
0.018
0.050
0.010
1.450
0.550
0.100
-
-
-
0.200
0.040
0.022
0.065
0.015
1.465
0.560
0.105
0.150
15°
0.155
0.020
0.014
0.040
0.008
1.435
0.600
0.125
0°
28
E
E1
DIM
A1
D/E
D1
D
B
e
A1
D2/E2
D1/E1
D2/E2
A
MILLIMETERSINCHES
NOM
MAXMINMAXMIN
A
B
e
4.45
4.574.200.1800.165
2.290.090
2.79
3.040.120
0.530.330.0210.013
0.41
12.3212.57 0.4850.495
12.45
11.4311.58 0.4500.456
11.51
9.9110.92 0.3900.430
10.41
1.191.350.0470.053
1.27
NOM
0.175
0.110
0.016
0.490
0.453
0.410
0.050
24DS157PP3
APPLICATIONS
CS61305A
CS61305A
RTIP
RRING
TRING
TTIP
16
13
19
20
R1
R2
0.47 µF
1
3
5
R3
21
R4
65
2
2CT:1
T1
Figure A1. Line Interface Circuitry
Frequency
MHz
Crystal
XTL
CableΩR1 and R2ΩLEN2/1/0T1 turns
ratio
1.544 (T1) CXT61761002000/1/1 - 1/1/11:1.15
1:2
1:2.3
2.048 (E1) CXT81921202400/0/0
0/0/0
0/0/1
0/0/1
751500/0/0
0/0/0
0/0/1
0/0/1
1:1.26
1:2
1:1
1:2
1:1
1:2
1:1
1:2
RECEIVE
LINE
6
TRANSMIT
LINE
R3 and R4ΩTypical TX
0
9.4
9.4
0
8.7
0
15
0
9.4
10
14.3
Return Loss
(dB)
0.5
20
28
0.5
12
0.5
30
0.5
24
5
12
Note: Refer to Table A3 for specific transformer recommendations.
Table A1. External Component Values
Line Interface
Mode. Figure A4 illustrates a 75 Ω E1 interface
in the Extended Hardware Mode.
Figure A1 illustrates the external components for
the line interface circuitry and Table A1 shows
the specific components for each application.
Figures A2-A4 show typical T1 and E1 line interface application circuits. Figure A2 illustrates a
The receiver transformer has a grounded center
tap on the IC side. Resistors between the RTIP
and RRING pins to ground provide the termination for the receive line.
T1 interface in the Host Mode. Figure A3 illustrates a 120 Ω E1 interface in the Hardware
DS157PP325
Control
&
Monitor
Frame
Format
Encoder/
Decoder
XTL
+
RV+
68
RGND
28
1
12
11
5
7
6
8
3
4
2
9
10
F
µ
CLKE
ACLKI
LOS
DPM
MODE
RPOS
RNEG
RCLK
TPOS
TNEG
TCLK
XTALIN
XTALOUT
+5V
0.1 µF
2115
RV+TV+
CS61305A
IN
HOST
MODE
RGNDTGND
2214
+
1.0 µF
SCLK
CS
INT
SDI
SDO
RTIP
RRING
MTIP
MRING
TRING
TTIP
TGND
27
26
23
24
25
19
20
17
18
16
13
+5V
100 k
0.47
200
200
Ω
Serial
Port
F
µ
CS61305A
P
µ
1
2CT:1
1:1.15
2
RECEIVE
LINE
6
1
TRANSMIT
LINE
5
Ω
3
Ω
5
PE-65351
2
6
PE-65388
Figure A2. T1 Host Mode Configuration
Figures A2-A4 show a 0.47 µF capacitor in series
with the transmit transformer primary. This capacitor is needed to prevent any output stage
imbalance from resulting in a DC current through
the transformer primary. This current might saturate the transformer producing an output offset
level shift.
Transformers
Recommended transmitter and receiver transformer specifications are shown in Table A2. The
transformers in Table A3 are recommended for
use with the CS61305A. Refer to the "Telecom
Transformer Selection Guide" for detailed schematics which show how to connect the line
interface IC with a particular transformer.
Selecting an Oscillator Crystal
Specific crystal parameters are required for
proper operation of the jitter attenuator. It is recommended that the Crystal Semiconductor
CXT6176 crystal be used for T1 applications and
the CXT8192 crystal be used for E1 applications.
Line Protection
Secondary protection components can be added
to provide lightning surge and AC power-cross
immunity. Refer to the Application Note "Secondary Line Protection for T1 and E1 Line Cards"
for detailed information on the different electrical
safety standards and specific application circuit
recommendations.
Interfacing The CS61305A With the
CS62180B T1 Transceiver
CS61305A
To interface with the CS62180B, connect the devices as shown in Figure A5. In this case, the line
interface and CS62180B are in Host mode controlled by a microprocessor serial interface. If the
line interface is used in Hardware mode, then the
line interface RCLK output must be inverted before being input to the CS62180B. If the
CS61305A is used in Extended Hardware Mode,
the RCLK output does not have to be inverted
before being input to the CS62180B.
TO HOST CONTROLLER
1.544 MHz
SCLK
SDO
SDI
CS
CS62180B
TCLK
TPOS
TNEG
RNEG
RPOS
RCLK
CLOCK
SIGNAL
ACLK
TCLK
TPOS
TNEG
RNEG
RPOS
RCLK
SCLK
CLKE
MODE
CS61305A
SDO
SDI
INT
CS
Figure A5. Interfacing the CS61305 A with a
CS62180B (Ho st Mode)
V+
100k
V+22k
28DS157PP3
CS61305A
ApplicationTurns
Ratio(s)
RX:
1:2CTPulse EngineeringPE-653511.5 kV through-hole, single
T1 & E1
TX:
1:1.15Pulse EngineeringPE-653881.5 kV through-hole, single
T1
TX:
1:1.26
E1 (75 & 120 Ω)
RX &TX:
T1
RX &TX:
E1 (75 & 120 Ω)
RX &TX:
T1
RX &TX:
E1 (75 & 120 Ω)
RX :
1:2CT
1:1.15
1:2CT
1:1.26
1:2CT
1:1.15
1:2CT
1:1.26
1:2CTPulse EngineeringPE-658353 kV through-hole, single
T1 & E1
TX:
1:1.26
E1 (75 & 120 Ω)
1:1
1:1
1:1
1:1
ManufacturerPart NumberPackage Type
Schott67129300
Bel Fuse0553-0013-HC
Schott67129310
Bel Fuse0553-0013-RC
Pulse EngineeringPE-653891.5 kV through-hole, single
Line Interface Evaluation
Configuration by DIP Switch or Serial
••
Interface
LED Status Indicators for Alarm
••
Conditions
Support for Host, Hardware, and
••
Extended Hardware Modes
Mode Select
Circuit
General Description
The evaluation board includes a socketed line interface
device and all support components necessary for
evaluation. The board is powered by an external 5 Volt
supply.
The board may be configured for 100 Ω twisted-pair
T1, 75 Ω coax E1, or 120 Ω twisted-pair E1 operation.
Binding posts are provided for line connections. Several BNC connectors are available to provide system
clocks and data I/O. Two LED indicators monitor device alarm conditions. The board supports all line
interface operating modes.
As shown on the evaluation board schematic in
Figure 1, power is supplied to the evaluation
board from an external +5 Volt supply connected
to the two binding posts labeled +5V and GND.
Transient suppressor D10 protects the components on the board from over-voltage damage and
reversed supply connections. The recommended
power supply decoupling is provided by C1, C2
and C3. Ceramic capacitor C1 and electrolyt ic capacitor C2 are used to decouple RV+ to RGND.
Capacitor C3 decouples TV+ to TGND. The TV+
and RV+ power supply traces are connected at the
device socket U1. A ground plane on the component side of the evaluation board insures optimum
performance.
BOARD CONFIGURATION
Pins on line interface device U1 with more than
one pin name have different functions depending
on the operating mode selected. Pin names not
enclosed in parenthesis or square brackets describe the Hardware mode pin function. Pin
names enclosed in parenthesis describe the Extended Hardware mode pin function. Pin names
enclosed in square brackets describe the Host
mode pin function.
Table 1 explains how to configure the evaluation
board jumpers depending on the device installed
and the desired operating mode. Mode selection
is accomplished with slide switch SW1 and jumpers JP2, JP6, and JP7. The CS61535A,
CS61574A, CS61575, CS61577, CS61304A, and
CS61305A support the Hardware, Extended
Hardware, and Host operating modes. The
CS61534, CS61535, and CS61574 support the
Hardware and Host operating modes. The
CS6158 and CS6158A only support the Hardware
operating mode.
Hardware Mode
In the Hardware operating mode, the line interface is configured using DIP switch S2. The digital control inputs to the device selected by S2 include: transmit all ones (TAOS), local loopback
(LLOOP), remote loopback (RLOOP), and transmit line length selection (LEN2,LEN1,LEN0).
Closing a DIP switch on S2 towards the label sets
the device control pin of the same name to logic 1
(+5 Volts). Note that S2 switch positions TCODE
and RCODE have no function in Hardware mode.
In addition, the host processor interface connector
JP1 should not be used in the Hardware mode.
Two LED status indicators are provided in Hardware mode. The LED labeled DPM (AIS) illuminates when the line interface asserts the Driver
JUMPERPOSITIONFUNCTION SELECTED
JP1-Connector for external processor in Host operating mode.
JP2, JP6, JP7
JP3
JP4
JP5
JP8
32DS40DB3
A-AExtended Hardware operating mode.
B-BHardware or Host operating modes.
INHardware or Extended Hardware operating modes.
OUTHost operating mode.
C-CConnects the ACLKI BNC input to pin 1 of device.
D-D
E-ETransmit line connection for all applications except those listed for "F-F" on the next line.
F-F
INShorts resistor R2 for all applications except those listed for "OUT" on the next line.
OUT
Grounds the ACLKI BNC input through 51Ω resistor R1.
75Ω coax E1 applications using the Schott 12932/12532 or PE-65389/65566 at transformer T1.
Inserts resistor R2 for 75Ω coax E1 applications using the CS61534, 35, 58, 74, or 77.
Table 1. Evaluation Board Jumper Settings
LINE INTERFACE EVALUATION BOARD
R15
100
RV+
+5V
D10
CC
Pin 4
ACLKI
JP3
R17
10k
P6KE
6
RNEG (BPV)
8
RCLK
2
TCLK
3
TPOS (TDATA)
7
RPOS (RDATA)
1
ACLKI
4
TNEG (TCODE)
23
LEN0 [INT]
24
LEN1 [SDI]
25
LEN2 [SD0]
26
RLOOP [CS]
27
LLOOP [SCLK]
28
TAOS [CKLE]
R14
4.7k
SIP
MODE
MODE
SW1
W
W
GND
(0V)
R1 51. 1
Ω
JP2
BB
D8
C4 0.047mF
6
R16
1k
Ω
Pin 6
RCLK
TCLK
Pin 3
Pin 7
JP4
DD
AA
3
R18
W
10k
RNEG
(BPV)
RCLK
TCLK
TPOS
(TDATA)
RPOS
(RDATA)
RV+
ACLKI
Ω
TNEG
S2
RCODE
TCODE
LEN0/INT
LEN1/SDI
LEN2/SD0
RLOOP/CS
LLOOP/SCLK
TAOS/CLKE
INT
SDI
SDO
CS
SCLK
D9
JP1
1N914
S1
RESET
R4
W
221k
875124
RV+
C2
0.1mF
1 mF
TGND RGND
51112
DPM
(AIS)
HOST:3-1,6-8
EXT HW: 3-2, 6-7
HW: 3-4, 6-5
C1
C3
68mF
+
221415
RV+TV+
{CS6158/58A: RT}
{CS6158/58A: NC}
U1
XTALIN
XTALOUT
RRING
MRING (PCS)
TRING
MTIP (RCODE)
LOSDPM (AIS)MODE
RV+
Q2
2N2222
LED
D2
R5
470
Ω
21
RTIP
TTIP
LOS
Prototyping
Area
RV+
R13 (only included for CS6158/58A)
W
1k
9
E1: CXT8192
T1: CXT6176
(not included for CS6158/58A)
10
RV+
RTIP
19
RRING
20
13
Pin 18
18
TRING
16
Pin 17
17
2N2222
Q1
LED
470
D3
R6
Change R9 and R10 for E1 operation
R10
W
200
R9
W
200
TTIP
JP6
BB
AA
JP7
BB
AA
Ω
0.47 mF
(Used only for E1 75
applications with the CS61534,
CS61535, CS6158, CS61574,
OR CS61577)
Performance Monitor alarm. The LED labeled
LOS illuminates when the line interface receiver
has detected a loss of signal.
Extended Hardware Mode
In the Extended Hardware operating mode, the
line interface is configured using DIP switch S2.
The digital control inputs to the device selected
by S2 include: transmit all ones (TAOS), local
loopback (LLOOP), remote loopback (RLOOP),
transmit line length selection (LEN2, LEN1,
LEN0), transmit line code (TCODE), and receive
line code (RCODE). Closing a DIP switch (moving it towards the S2 label) sets the device control
pin of the same name to logic 1 (+5 Volts). Note
that the TCODE and RCODE options are active
low and are enabled when the switch is moved
away from the S2 label. The parallel chip select
input PCS is tied to ground in Extended Hardware mode to enable the device to be reconfigured when S2 is changed. In addition, the host
processor interface connector JP1 should not be
used in Extended Hardware mode.
Two LED status indicators are provided in Extended Hardware mode. The LED labeled DPM
(AIS) illuminates when the line interface detects
the receive blue alarm (AIS). The LED labeled
LOS illuminates when the line interface receiver
has detected a loss of signal.
Host Mode
In the Host operating mode, the line interface is
configured using a host processor connected to
the serial interface port JP1. The S 2 switch position labeled CLKE selects the active edge of
SCLK and RCLK. Closing the CLKE switch selects RPOS and RNEG to be valid on the falling
edge of RCLK and SDO to be valid on the rising
edge of SCLK as required by the CS2180B T1
framer.
All other DIP switch positions on S2 should be
open (logic 0) to prevent shorting of the serial in-
terface signals. Resistor R15 is a current limiting
resistor that prevents the serial interface signals
from being shorted directly to the +5 Volt supply
if any S2 switch, other than CLKE, is closed.
Jumper JP3 should be out so the INT pin may be
externally pulled-up at the host processor interrupt pin.
Two LED status indicators are provided in Host
mode. The LED labeled DPM (AIS) illuminates
when the line interface asserts the Driver Performance Monitor alarm. The LED labeled LOS
illuminates when the line interface receiver has
detected a loss of signal.
Manual Reset
A manual reset circuit is provided that can be
used in Hardware and Extended Hardware
modes. The reset circuit consists of S1, R4, R16,
C4, D8, and D9. Pressing switch S1 forces both
LLOOP and RLOOP to a logic 1 and causes a
reset. A reset is only necessary for the CS61534
device to calibrate the center frequency of the receiver clock recovery circuit. All other line interface units use a continuously calibrated clock recovery circuit that eliminates the reset requirement.
TRANSMIT CIRCUIT
The transmit clock and data signals are supplied
on BNC inputs labeled TCLK, TPOS(TDATA),
and TNEG. In the Hardware and Host operating
modes, data is supplied on the TPOS(TDATA)
and TNEG connectors in dual NRZ format. In the
Extended Hardware operating mode, data is supplied in NRZ format on the TPOS(TDATA) connector and TNEG is not used.
The transmitter output is transformer coupled to
the line through a transformer denoted as T1 in
Figure 1. The signal is availabl e at the TTIP and
TRING binding posts. Capacitor C5 is the recommended 0.47 µF DC blocking capacitor.
34DS40DB3
LINE INTERFACE EVALUATION BOARD
The evaluation board supports 100Ω twisted-pair
T1, 75Ω coax E1, and 120Ω twisted-pair E1 op-
eration. The CDB61534, CDB61535, CDB6158,
CDB61574, and CDB61577 are supplied from
the factory with a 1:2 transmit transformer that
may be used for all T1 and E1 applications. The
CDB61535A, CDB6158A, CDB61574A,
CDB61575, CDB61304A, and CDB61305A are
supplied with a 1:1.15 transmit transformer installed for T1 applications. An additional 1:1:1.26
transformer for E1 applications is provided with
the board. This transformer requires JP5 to be
jumpered across F-F for 75Ω coax E1 applications.
The CDB61534, CDB61535, CDB6158,
CDB61574, and CDB61577 require the JP8
jumper to be out for 75Ω coax E1 applications.
This inserts resistor R2 to reduce the transmit
pulse amplitude and meet the 2.37 V nominal
pulse amplitude requirement in CCITT G.703. In
addition, R2 increases the equivalent load impedance across TTIP and TRING.
The recovered clock and data signals are available on BNC outputs labeled RCLK,
RPOS(RDATA), and RNEG(BPV). In the Hardware and Host operating modes, data is output on
the RPOS(RDATA) and RNEG(BPV) connectors
in dual NRZ format. In the Extended Hardware
operating mode, data is output in NRZ format on
the RPOS(RDATA) connector and bipolar violations are reported on the RNEG(BPV) connector.
QUARTZ CRYSTAL
A quartz crystal must be installed in socket Y1 for
all devices except the CS6158 and CS6158A. A
Crystal Semiconductor CXT6176 crystal is recommended for T1 operation and a CXT8192 is
recommended for E1 operation. The evaluation
board has a CXT6176 installed at the factory and
a CXT8192 is also provided with the board.
The CDB6158 and CDB6158A have resistor R13
installed instead of a crystal. This connects the RT
pin of the device to the +5 Volt supply.
RECEIVE CIRCUIT
The receive line interface signal is input at the
RTIP and RRING binding posts. The receive signal is transformer coupled to the line interface device through a center-tapped 1:2 transformer. The
transformer produces ground referenced pulses of
equal amplitude and opposite polarity on RTIP
and RRING.
The receive line interface is terminated by resistors R9 and R10. The evaluation boards are sup-
plied from the factory with 200Ω resistors for terminating 100Ω T1 twisted-pair lines. Resistors
R9 and R10 should be replaced with 240Ω resistors for terminating 120Ω E1 twisted-pair lines or
150Ω resistors for terminating 75Ω E1 coaxial
lines. Two 243Ω resistors and two 150Ω resistor s
are included with the evaluation board for this
purpose.
ALTERNATE CLOCK INPUT
The ACLKI BNC input provides the alternate
clock reference for the line interface device
(ACLK for the CS61534) when JP4 is jumpered
across C-C. This clock is required for the
CS61534, CS61535, CS6158, and CS6158A operation but is optional for all other line interface
devices. If ACLKI is provided, it may be desirable to connect both C-C and D-D positions on
JP4 to terminate the external clock source provid-
ing ACLKI with the 51Ω resistor R1. If ACLKI is
optional and not used, connector JP4 should be
jumpered across D-D to ground pin 1 of the device through resistor R1.
TRANSFORMER SELECTION
To permit the evaluation of other transformers,
Table 2 lists the transformer and line interface device combinations that can be used in T1 and E1
DS40DB335
LINE INTERFACE EVALUATION BOARD
applications. A letter at the intersection of a row
and column in Table 2 indicates that the selected
transformer is supported for use with the device.
The transformer is installed in the evaluation
board with pin 1 positioned to match the letter
illustrated on the drawing in Table 2. For example, the Pulse Engineering PE-65388 transformer
may be used with the transmitter of the CS61575
device for 100Ω T1 applications only (as indi-
cated by note 3) when installed in transformer
socket T1 with pin 1 at position D (upper right).
PROTOTYPING AREA
A prototyping area with power supply and ground
connections is provided on the evaluation board.
This area can be used to develop and test a variety of additional circuits like a data pattern generator, CS2180B framer, system synchronizer PLL,
or specialized interface logic.
4. To avoid damage to the external host controller
connected to JP1, all S2 switch positions (except
CLKE) should be open. In the Host operating
mode, the CLKE switch selects the active edge of
SCLK and RCLK.
EVALUATION HINTS
1. Properly terminate TTIP/TRING when evaluating the transmit output signal. For more information concerning pulse shape evaluation, refer to
the Crystal application note entitled "Measurement and Evaluation of Pulse Shapes in T1/E1
Transmission Systems."
2. Change the receiver terminating resistors R9
and R10 when evaluating E1 applications. Resis-
tors R9 and R10 should be replaced with 240Ω
resistors for terminating 120Ω E1 twisted-pair
lines or 150Ω resistors for terminating 75Ω E1
coaxial lines. Two 243Ω resistors and two 150Ω
resistors are included with the evaluation board
for this purpose.
3. Closing a DIP switch on S2 towards the label
sets the device control pin of the same name to
logic 1 (+5 Volts).
1. A letter at the intersection of a row and column in Table 2 indic ates
that the selected transformer is supported for use with the dev ice.
The transformer is installed in the evaluation board with pin 1 po-
T2
sitioned to match the letter illustrated in the drawing to the left.
2. The receive transformer (RX) is soldered at location T2 on the
evaluation board and is used for all applications. The transmit
transformer (TX) is socketed at location T1 on the evaluation
board and may be changed according to the applic ation.
3. For use in 100Ω T1 twisted-pair applications only.
4. For use in 75Ω and 120Ω E1 applications only. Place jumper JP5
in position F-F for 75Ω E1 applications requiring a 1:1 turns ratio.
5. Tran smitter ret urn loss im proves when using a 1:2 tur ns ratio trans -
E
T1
former with t he appro priate tr ansmit re sistors.
’304A,
’305A
D
C
D
C
3,5
E
3,5
E
4,5
E
4,5
E
3,5
3,5
4,5
4,5
Table 2. Transformer Applications
DS40DB337
LINE INTERFACE EVALUATION BOARD
Figure 2. Silk Screen Layer (NOT TO SCALE)
38DS40DB3
LINE INTERFACE EVALUATION BOARD
Figure 3. Top Ground Plane Layer (NOT TO SCALE)
DS40DB339
LINE INTERFACE EVALUATION BOARD
Figure 4. Bo ttom Trace Layer (NOT TO SCALE)
40DS40DB3
• Notes •
• Notes •
• Notes •
Smart
Analog
TM
is a Trademark of Crystal Semiconductor Corporation
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