Cirrus Logic CS61305A-IP1, CS61305A-IL1 Datasheet

T1/E1 Line Interface

CS61305A

Features

Provides Analog Transmission Line

••

Interface for T1 and E1 Applications
Provides Line Driver, Jitter Attenuator

••

and Clock Recovery Functions
Transmit Side Jitter Attenuation

••

Starting at 3 Hz, with > 300 UI of Jitter
Tolerance

B8ZS/HDB3/AMI Encoders/Decoders

••

Compatible with SONET, M13 , CCITT

••

G.742, and Other Asynchronous Muxes
50 mA Transmitter Short-Circuit

••

Current Limiting

General Description

The CS61305A combines the complete analog transmit
and receive line interface for T1 or E1 applications in a
low power, 28-pin device operating from a +5V supply.
The CS61305A is a pin-compatible replacement for the
LXT305A in most applications.

The CS61305A provides a transmitter jitter attenuator
making it ideal for use in asynchronous multiplexor
systems with gapped transmit clocks. The transmitter
features internal pulse shaping and a low impedance
output stage allowing the use of external resistors for
transmitter impedance matching. The receiver uses a
digital Delay-Locked-Loop clock and data recovery cir­cuit which is continuously calibrated from a crystal
reference to provide excellent stability and jitter toler­ance.

Applications

•

Interfacing network transmission equipment such as
SONET multiplexor and M13 to a DSX-1 cross con­nect.

•

Interfacing customer premises equipment to a CSU.

ORDERING INFORMATION

CS61305A-IP1 28 Pin Plastic DIP
CS61305A-IL1 28 Pin Plastic PLCC

[ ] = Pin Function in
( ) = Pin Function in

TCLK

TPOS

[TDATA]

TNEG

[TCODE]

RCLK

RPOS

[RDATA]

RNEG

[BPV]

2

3

4

8

7

6

Extended Hardware Mode

Host Mode

AMI,
B8ZS,
HDB3

CODER

LOOP
BACK

27

LLOOP
(SCLK)

XTALIN

26

RLOOP

(CS)

Preliminary Product Information

Crystal Semiconductor Corporation

P. O. Box 17847, Austin, Texas, 78760
[phone] FAX:[phone]

(INT)

(SDI)

XTALOUT

9

JITTER

ATTENUATOR

(CLKE)

MODE

10

5

CONTROL

ACLKI

LEN0

TAOS

28 23

CLOCK &

DATA

RECOVERY

SIGNAL

QUALITY

MONITOR

12 21

1

LOS

LEN1

PULSE

SHAPER

RV+

(SDO)

LEN2

2524

RGND

TGND

14

LINE DRIVER

LINE RECEIVER

DRIVER

MONITOR

22

TV+

15

13

TTIP

16

TRING

19

RTIP

20

RRING

17

MTIP
[RCODE]

18

MRING
[PCS]

11

DPM
[AIS]

This document contains information for a new product. Crystal
Semiconductor reserves the right to modify this product without notice.

Copyright  Crystal Semiconductor Corporation 1996

(All Rights Reserved)

MAY ’96

DS157PP3

1

CS61305A

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Min Max Units

DC Supply (referenced to RGND=TGND=0V) RV+

TV+
Input Voltage, Any Pin (Note 1) V
Input Current, Any Pin (Note 2) I
Ambient Operating Temperature T
Storage Temperature T

in

in

A

stg

-

-

6.0

(RV+) + 0.3

RGND-0.3 (RV+) + 0.3 V

-10 10 mA

-40 85

-65 150

WARNING: Operations at or beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes.

Notes: 1. Excluding RTIP, RRING, which must stay within -6V to (RV+) + 0.3V.

2. Transient currents of up to 100 mA will not cause SCR latch-up. Also TTIP, TRING, TV+ and TGND
can withstand a continuous current of 100 mA.

RECOMMENDED OPERATING CONDITIONS

Parameter Symbol Min Typ Max Units

DC Supply (Note 3) RV+, TV+ 4.75 5.0 5.25 V
Ambient Operating Temperature T
Power Consumption (Notes 4,5) P

Notes: 3. TV+ must not exceed RV+ by mor e than 0.3V.

4. Power consumption while driving line load over oper ating temperature range. Includes IC and load.
Digital input levels are within 10% of the supply rails and digital outputs are driving a 50 pF
capacitive load.

5. Assumes 100% ones density and maximum line length at 5.25V.

A
C

-40 25 85

- - 350 mW

V
V

°C
°C

°C

DIGITAL CHARACTERISTICS (TA = -40°C to 85°C; TV+, RV+ = 5.0V ±5%; GND = 0V)

Parameter Symbol Min Typ Max Units

High-Level Input Voltage (Notes 6, 7)

PINS 1-4, 17, 18, 23-28

Low-Level Input Voltage (Notes 6, 7)

PINS 1-4, 17, 18, 23-28

High-Level Output Voltage (Notes 6, 7, 8)
I

= -400 µA PINS 6-8, 11, 12, 25

OUT
Low-Level Output Voltage (Notes 6, 7, 8)
I

= 1.6 mA PINS 6-8, 11, 12, 23, 25

OUT
Input Leakage Current (Except Pin 5) - -

Low-Level Input Voltage, PIN 5 V
High-Level Input Voltage, PIN 5 V
Mid-Level Input Voltage, PIN 5 (Note 9) V

Notes: 6. In Extended Hardware Mode, pins 17 and 18 are digital inputs. In Host Mode, pin 23 is

an open drain output and pin 25 is a tristate digital output.

7. This specification guarantees TTL compatibility (V

8. Output drivers will drive CMOS logic levels into a CMOS load.

9. As an alternative to supplying a 2.3-to-2.7V input, this pin may be left floating.

2 DS157PP3

V

IH

V

IL

V

OH

V

OL

IL
IH

IM

= 2.4V @ I

OH

2.0 - - V

--0.8V

2.4 - - V

--0.4V

±10 µA

--0.2V

(RV+) - 0.2 - - V

2.3 - 2.7 V

= -40µA).

OUT

CS61305A

ANALOG SPECIFICATIONS (TA = -40°C to 85°C; TV+, RV+ = 5.0V ±5%; GND = 0V)

Parameter Min Typ Max Units

Transmitter

AMI Output Pulse Amplitudes (Note 10)

E1, 75 Ω (Note 11)
E1, 120 Ω (Note 12)
T1, FCC Part 68 (Note 13)
T1, DSX-1 (Note 14)

E1 Zero (space) level (LEN2/1/0 = 000)

1:1 transformer and 75Ω load

1:1.26 transformer and 120Ω load
Load Presented To Transmitter Output (Note 10) - 75 ­Jitter Added by the Transmitter (Note 15)

10Hz - 8kHz

8kHz - 40kHz

10Hz - 40kHz

Broad Band
Power in 2kHz band about 772kHz (Notes 10, 16) 12.6 15 17.9 dBm
Power in 2kHz band about 1.544MHz (Notes 10, 16)

(referenced to power in 2kHz band at 772kHz)
Positive to Negative Pulse Imbalance (Notes 10, 16)

T1, DSX-1

E1 amplitude at center of pulse

E1 pulse width at 50% of nominal amplitude
E1 Transmitter Return Loss (Notes 10, 16, 17)

51 kHz to 102 kHz

102 kHz to 2.048 MHz

2.048 MHz to 3.072 MHz

E1 Transmitter Short Circuit Current (Notes 10, 18) - - 50 mA RMS

Notes: 10. Using a 0.47 µF capacitor in series with the primary of a tr ansformer recommended

in the Applications Section.

11. Pulse amplitude measured at the output of a 1:1 tr ansformer across a 75 Ω load for
line length setting LEN2/1/0 = 0/0/0.

12. Pulse amplitude measured at the output of a 1:1.26 tr ansformer across a 120 Ω load for line length
setting LEN2/1/0 = 0/0/0 or at the output of a 1:1 transformer across a 120 Ω load for LEN2/1/0 = 001.

13. Pulse amplitude measured at the output of a 1:1.15 tr ansformer across a 100 Ω load for
line length setting LEN2/1/0 = 0/1/0.

14. Pulse amplitude measured at the DSX-1 Cross -Connect across a 100 Ω load for all line length
settings from LEN2/1/0 = 0/1/1 to LEN2/1/0 = 1/1/1 using a 1:1.5 transformer.

15. Input signal to RTIP/RRING is jitter free. Values will reduce slightly if jitter free clock is input to TCLK.

16. Not production tested. Parameters guaranteed by design and characterization.

17. Return loss = 20 log

= impedance of line load. Measured with a repeating 1010 data pattern with LEN2/1/0 = 0/0/0

z

0

and a 1:2 transformer with two 9.4 Ω series res istors terminated by a 75Ω load,
or for LEN2/1/0 = 0/0/1 with a 1:2 transformer and two 15 Ω ser ies resistors terminated by a
120Ω load.

18. Measured broadband through a 0.5 Ω resistor across the secondary of the transmitter transformer
during the transmission of an all ones data pattern for LEN2/1/0 = 0/0/0 or 0/0/1with a 1:2 transformer
and the series resistors specified in Table A1.

ABS((z1 +z0)/(z1-z0)) where z1 = impedance of the transmitter, and

10

2.14

2.7

2.7

2.4

-0.237

-0.3

-

-

-

-

-29 -38 - dB

-

-5

-5

20
20
20

2.37

3.0

3.0

3.0

-

-

-

-

-

-

0.2

-

-

28
28
24

2.6

3.3

3.3

3.6

0.237

0.3

0.01

0.025

0.025

0.05

0.5
5
5

-

-

-

V
V
V
V

V
V

Ω

UI
UI
UI
UI

dB

%
%

dB
dB
dB

DS157PP3 3

CS61305A

ANALOG SPECIFICATIONS (TA = -40°C to 85°C; TV+, RV+ = 5.0V ±5%; GND = 0V)

Parameter Min Typ Max Units

Transmitter Jitter Attenuator

Jitter Attenuation Curve Corner Frequency (Notes 16, 19) - 3 - Hz
Attenuation at 10kHz Jitter Frequency (Notes 16, 19) - 50 - dB
Attenuator Input Jitter Tolerance (Notes 16, 19)

(Before Onset of FIFO Overflow or Underflow Protection)

Receiver

RTIP/RRING Input Impedance - 50k ­Sensitivity Below DSX (0dB = 2.4V ) -13.6

Data Decision Threshold

T1, DSX-1 (Note 20)

T1, (FCC Part 68) and E1 (Note 21)
Allowable Consecutive Zeros before LOS 160 175 190 bits
Receiver Input Jitter Tolerance (Note 22)

10kHz - 100kHz

2kHz

10Hz and below
Loss of Signal Threshold - 0.30 - V

Notes: 19. Attenuation measured with input jitter equal to 3/4 of measured jitter tolerance. Circuit attenuates

jitter at 20 dB/decade above the corner frequency. See Figure 10. Output jitter can increase
significantly when more than 12 UI’s are input to the attenuator. See discussion in the text section.

20. For input amplitude of 1.2 V

21. For input amplitude of 1.05 V

to 4.14 Vpk.

pk

to 3.3 Vpk.

pk

22. Jitter tolerance increases at lower frequencies. See Figure 12.

138 - - UI

Ω

500

53
45

0.4

6.0

300

-

-

65
50

-

-

-

77
55

-

-

dB

mV

% of peak
% of peak

-

-

-

UI
UI
UI

E1 SWITCHING CHARACTERISTICS (TA = -40°C to 85°C; TV+, RV+ = 5.0V ±5%;

GND = 0V; Inputs: Logic 0 = 0V, Logic 1 = RV+; See Figures 1, 2, & 3)

Parameter Symbol Min Typ Max Units

Crystal Frequency (Note 23) f
ACLKI Duty Cycle t

pwh3/tpw3

ACLKI Frequency (Note 24) f
RCLK Cycle Width (Note 25) t

t

t
Rise Time, All Digital Outputs (Note 26) t
Fall Time, All Digital Outputs (Note 26) t
TCLK Frequency f
TCLK Pulse Width (Notes 27, 28)

t

(Notes 29, 30)
TPOS/TNEG (TDATA) to TCLK Falling Setup Time t
TCLK Falling to TPOS/TNEG (TDATA) Hold Time t
RPOS/RNEG Valid Before RCLK Falling (Note 27) t
RDATA Valid Before RCLK Falling (Note 29) t
RPOS/RNEG Valid Before RCLK Rising (Note 28) t
RPOS/RNEG Valid After RCLK Falling (Note 27) t
RDATA Valid After RCLK Falling (Note 29) t
RPOS/RNEG Valid After RCLK Rising (Note 28) t

c

aclki

pw1

pwh1

pwl1

r

f

tclk

pwh2

su2

h2
su1
su1
su1

h1

h1

h1

- 8.192000 - MHz

40 - 60 %

- 2.048 - MHz

310

90

120

488
140
348

620
190
500

- - 85 ns

- - 85 ns

- 2.048 - MHz

80

150

-

-

340
25 - - ns
25 - - ns

100 194 - ns
100 194 - ns
100 194 - ns
100 194 - ns
100 194 - ns
100 194 - ns

ns
ns
ns

-

ns
ns

4 DS157PP3

CS61305A

T1 SWITCHING CHARACTERISTICS (TA = -40°C to 85°C; TV+, RV+ = 5.0V ±5%;

GND = 0V; Inputs: Logic 0 = 0V, Logic 1 = RV+; See Figures 1, 2, & 3)

Parameter Symbol Min Typ Max Units

Crystal Frequency (Note 23) f
ACLKI Duty Cycle t
ACLKI Frequency (Note 24) f
RCLK Cycle Width (Note 25) t

Rise Time, All Digital Outputs (Note 26) t
Fall Time, All Digital Outputs (Note 26) t
TCLK Frequency f
TCLK Pulse Width (Notes 16, 27, 28)

c

pwh3/tpw3

aclki

pw1

t

pwh1

t

pwl1

r

f

tclk

t

pwh2

(Notes 29, 30)
TPOS/TNEG (TDATA) to TCLK Falling Setup Time t
TCLK Falling to TPOS/TNEG (TDATA) Hold Time t
RPOS/RNEG Valid Before RCLK Falling (Note 27) t
RDATA Valid Before RCLK Falling (Note 29) t
RPOS/RNEG Valid Before RCLK Rising (Note 28) t
RPOS/RNEG Valid After RCLK Falling (Note 27) t
RDATA Valid After RCLK Falling (Note 29) t
RPOS/RNEG Valid After RCLK Rising (Note 28) t

su2

h2
su1
su1
su1

h1

h1

h1

Notes: 23. Crystal must meet specifications described in CXT6176/CXT8192 data sheet.

24. ACLKI provided by an external source or TCLK but not RCLK.

25. RCLK duty cycle will vary with extent by which pulses are displaced by jitter. Specified under worst
case jitter conditions: 0.4 UI AMI data displacement for T1 and 0.2 UI AMI data displacement for E1.

26. At max load of 1.6 mA and 50 pF.

27. Host Mode (CLKE = 1).

28. Hardware Mode, or Host Mode (CLKE = 0).

29. Extended Hardware Mode.

30. The maximum TCLK burst rate is 5 MHz and t

(min) = 200ns. The maximum gap size that can

pw2

be tolerated on TCLK is 138 VI.

- 6.176000 - MHz

40 - 60 %

- 1.544 - MHz

320
130
100

648
190
458

980
240
850

- - 85 ns

- - 85 ns

- 1.544 - MHz

80

150

-

-

500
25 - - ns
25 - - ns

150 274 - ns
150 274 - ns
150 274 - ns
150 274 - ns
150 274 - ns
150 274 - ns

ns
ns
ns

-

ns
ns

DS157PP3 5

CS61305A

SWITCHING CHARACTERISTICS

(TA = -40° to 85°C; TV+, RV+ = ±5%;

Inputs: Logic 0 = 0V, Logic 1 = RV+)

Parameter Symbol Min Typ Max Units

SDI to SCLK Setup Time t
SCLK to SDI Hold Time t
SCLK Low Time t
SCLK High Time t
SCLK Rise and Fall Time t
CS to SCLK Setup Time t
SCLK to

CS Hold Time t
CS Inactive Time t
SCLK to SDO Valid (Note 31) t
CS to SDO High Z t
Input Valid To

PCS Falling Setup Time t
PCS Rising to Input Invalid Hold Time t
PCS Active Low Time t

Notes: 31. Output load capacitance = 50pF.

t

r

dc

cdh

cl

ch

, t

r

cc
cch
cwh
cdv
cdz
su4

h4

pcsl

50 - - ns

50 - - ns
240 - - ns
240 - - ns

f

- - 50 ns
50 - - ns
50 - - ns

250 - - ns

- - 200 ns

- 100 - ns
50 - - ns
50 - - ns

250 - - ns

t

f

RCLK

RPOS
RNEG
RDATA

BPV

RCLK

Any Digital Output

Figure 1. Signal Rise and Fall Characteristics

t

pwl1

tt

su1

t

pw1

90% 90%

10%

t

pwh1

h1

10%

EXTENDED

HARDWARE
MODE OR
HOST MODE

(CLKE = 1)

HARDWARE
MODE OR

HOST MODE
(CLKE = 0)

Figure 2. Recovered Clock and Data Sw itching Characterist ics

6 DS157PP3

TCLK

t

pwh2

t

su2

t

pw2

CS61305A

t

pw3

t

h2

t

pwh3

TPOS/TNEG

Figure 3a. Transmit Clock and Data Switching

Characteristics

CS

t

ch

cc

CONTROL BYTE DATA BYTE

t

cl

t

cdh

Figure 4. Serial Port Write Timing Diagram

SCLK

SDI

t

t

dc

LSB LSB MS B

CS

ACLKI

Figure 3b. Alternate External Clock Characteristics

t

cwh

t

cch

t

cdh

t

cdz

SCLK

t

cdv

SDO

CLKE = 1

Figure 5. Serial Port Read Timing Diagram

PCS

t

su4

t

LEN0/1/2, TAOS,
RLOOP, LLOOP,

RCODE, TCODE

Figure 6. Extended Hardware Mode Parallel Chip Select Timing Diagram

DS157PP3 7

VALID INPUT DATA

pcsl

t

h4

HIGH Z

CS61305A

THEORY OF OPERATION

Key Enhancements of the CS61305A Relative
to the LXT305A

• 12.5% lower power consumption,

• 50 mA

transmitter short-circuit current

RMS

limiting for E1 (per OFTEL OTR-001),

• Optional AMI, B8ZS, HDB3 encoder/de-

coder or external line coding support,

• Receiver AIS (unframed all ones) detection,

• Improved receiver Loss of Signal handling

(LOS set at power-up, reset upon receipt of
3 ones in 32 bit periods with no more than
15 consecutive zeros),

• Transmitter TTIP and TRING outputs are

forced low when TCLK is static.

Introduction to Operating Modes

The CS61305A supports three operating modes
which are selected by the level of t he MODE pin
as shown in Tables 1 and 2, Figure 7, and Figures
A1-A3 of the Applications section.

There are thirteen multi-function pins whose
functionality is determined by the operating
mode. (see Table 2). The modes are Hardware
Mode, Extended Hardware Mode, and Host
Mode. In Hardware and Extended Hardware
Modes, discrete pins are used to configure and
monitor the device. The Extended Hardware
Mode provides a parallel chip select input which
latches the control inputs allowing individual ICs
to be configured using a common set of control
lines. In the Host Mode, an external processor
monitors and configures the device through a se­rial interface.

Hardware

Mode

Control

Method

MODE

Pin

Level

Line

Coding

AIS

Detection

Driver

Performance

Monitor

Table 1. Differences Between Operating Modes

FUNCTION PIN HARDWARE

TRANSMITTER

RECEIVER/DPM

CONTROL

Control

Pins

<0.2 V Floating or

External Internal-

No Yes No

Yes No Yes

3TPOS TDATA TPOS
4TNEG
6 RNEG BPV RNEG

7 RPOS RDATA RPOS
11 DPM AIS DPM
17 MTIP
18 MRIN G - MRING
18 ­23 LEN0 LEN0
24 LEN1 LEN1 SDI
25 LEN2 LEN2 SDO
26 RLOOP RLOOP
27 LLOOP LLOOP SCLK
28 TAOS TAOS CLKE

Table 2. Pin Definitions

Extended

Hardware

Mode

Control Pins

with Parallel

Chip Select

2.5 V

AMI, B8ZS,

or HDB3

MODE

EXTENDED

HARDWARE HOST

TCODE TNEG

RCODE MTIP

PCS -

Host

Mode

Serial

Interface

>(R V+)-0.2

V

External

INT

CS

8 DS157PP3

CS62180B
FRAMER
CIRCUIT

TNEG

RPOS
RNEG

HARDWARE MODE

RLOOP LEN0/1/2LLOOPTAOS

CONTROL

JITTER

ATTENUATOR

CS61305A

LINE DRIVER

DRIVER MONITOR

LINE RECEIVER

EXTENDED HARDWARE MODE

RCODETCODE

RLOOP PCS LEN0/1/2LLOOPTAOS

MRING

MTIP

TTIPTPOS

TRING

DPM
RTIP

RRING

CS61305A

TRANSMIT

TRANSFORMER

RECEIVE

TRANSFORMER

HIGH

SPEED

MUX

(e.g., M13)

CONTROL

CS62180B

FRAMER

CIRCUIT

TDATA

RDATA

BPV

P SERIAL PORT

µ

5

TPOS
TNEG

RPOS
RNEG

AMI
B8ZS,
HDB3,

CODER

JITTER

ATTENUATOR

CS61305A

JITTER

ATTENUATOR

CS61305A

AIS

DETECT

AIS

HOST MODE

CLKE

CONTROL

CONTROL

LINE DRIVER

DRIVER MONITOR

LINE RECEIVER

LINE DRIVER

LINE RECEIVER

MRING

MTIP

TTIP
TRING

RTIP

RRING

TTIP
TRING

DPM
RTIP

RRING

TRANSMIT

TRANSFORMER

RECEIVE

TRANSFORMER

TRANSMIT

TRANSFORMER

RECEIVE

TRANSFORMER

Figure 7. Overview of Operating Modes

DS157PP3 9

CS61305A

Transmitter

The transmitter takes digital T1 or E1 input data
and drives appropriately shaped bipolar pulses
onto a transmission line. The transmit data (TPOS
& TNEG or TDATA) is supplied synchronously
and sampled on the falling edge of the input
clock, TCLK.

Either T1 (DSX-1 or Network Interface) or E1
CCITT G.703 pulse shapes may be selected.
Pulse shaping and signal level are controlled by
"line length select" inputs as shown in Table 3.
The output options in Table 3 are specified with a
1:1.15 transmitter transformer turns ratio for T1
and a 1:1 turns ratio for E1 without external se­ries resistors. Other turns ratios may be used if
approriate resistors are placed in series with the
TTIP and TRING pins. Table A1 in the applica­tions section lists other combinations which can
be used to provide transmitter impedance match­ing.

For T1 DSX-1 applications, line lengths from 0 to
655 feet (as measured from the transmitter to the
DSX-1 cross connect) may be selected. The five
partition arrangement in Table 3 meets ANSI
T1.102-1993 and AT&T CB-119 requirements
when using #22 ABAM cable. A typical output
pulse is shown in Figure 8. These pulse settings
can also be used to meet CCITT pulse shape re­quirements for 1.544 MHz operation.

LEN2 LEN1 LEN0 Option Selected Application

011 0-133 ft
100 133-266 ft
101 266-399 ft
110 399-533 ft
111 533-655 ft
000
001
0 1 0 FCC PART 68, OPT. A Network
0 1 1 ANSI T1.403

Table 3. Line Length Selection

75Ω coax

120Ω twisted-pair

DSX-1
ABAM

(AT&T 600B

or 600C)

E1

CCITT G.703

Interface

The CS61305A transmitter provides short-circuit
current limiting protection and meets OFTEL
OTR-001 short-circuit current limiting require­ments for E1 applications.

The CS61305A will detect a static TCLK, and
will force TTIP and TRING low to prevent trans­mission when data is not present. When any
transmit control pin (TAOS, LEN0-2 or LLOOP)
is toggled, the transmitter outputs will require ap­proximately 22 bit periods to stabilize. The
transmitter will take longer to stabilize when
RLOOP is selected because the timing circuitry
must adjust to the new frequency.

NORMALIZED
AMPLITUDE

1.0

ANSI T1.102,
AT&T CB 119
SPECIFICATIONS

For T1 Network Interface applications, two addi­tional options are provided. Note that the optimal

0.5

pulse width for Part 68 (324 ns) is narrower than
the optimal pulse width for DSX-1 (350 ns). The
CS61305A automatically adjusts the pulse width
based upon the "line length" selection made.

The E1 G.703 pulse shape is supported with line
length selections LEN2/1/0 = 0/0/0 and 0/0/1.
The pulse width will meet the G.703 pulse shape
template shown in Figure 9, and specified in Ta­ble 4.

10 DS157PP3

0

OUTPUT

PULSE SHAPE

-0.5

0 250 750 1000

Figure 8. Typical Pulse Shape at DSX-1 Cross Connect

500

TIME (nanoseconds)

120
110
100

90
80

50

Percent of
nominal
peak
voltage

269 ns

244 ns
194 ns

Attenuation in dB

0

10

20

30

40

50

CS61305A

a) Minimum Attenuation Limit

AT&T 62411

Requirements

b) Maximum
Attenuation
Limit

-10

-20

10

0

219 ns
488 ns

Nominal Pulse

Figure 9. Mask of the Pulse at the 2048 kbps Interface

Transmit All Ones Select

The transmitter provides for all ones insertion at
the frequency of ACLKI. Transmit all ones is se­lected when TAOS goes high, and causes
continuous ones to be transmitted on the line
(TTIP and TRING). In this mode, the TPOS and
TNEG (or TDATA) inputs are ignored. A TAOS
request will be ignored if remote loopback is in
effect. ACLKI jitter will be attenuated. TAOS is
not available on the CS61305A when ACLKI is
grounded.

60

1 10 100 1 k 10 k

Frequency in Hz

Measured Performance

Figure 10. Typical Jitter Attenuation Curve

Jitter Attenuator

The jitter attenuator is designed to reduce wander
and jitter in the transmit clock signal. It consists
of a 192 bit FIFO, a crystal oscillator, a set of
load capacitors for the crystal, and control logic.
The jitter attenuator exceeds the jitter attenuation
requirements of Publications 43802 and REC.
G.742. A typical jitter attenuation curve is shown
in Figure 10.

The jitter attenuator works in the following man­ner. Data on TPOS and TNEG (or TDATA) are

For coaxial cable,
75Ω load and
transformer specified
in Application Section.

For shielded twisted
pair, 120Ω load and
transformer specified

in Application Section.
Nominal peak voltage of a mark (pulse) 2.37 V 3 V
Peak voltage of a space (no pulse)

0 ±0.237 V 0 ±0.30 V
Nominal pulse width 244 ns
Ratio of the amplitudes of positive and negative

pulses at the center of the pulse interval
Ratio of the widths of positive and negative

pulses at the nominal half amplitude

0.95 to 1.05*

0.95 to 1.05*

* When configured with a 0.47 µF nonpolarized capacitor in series with the TX transformer

primary as shown in Figures A1, A2 and A3.

Table 4. CCITT G.703 Specifications

DS157PP3 11

CS61305A

written into the ji tt er at tenu at o r’s FIFO by TCLK.
The rate at which data is read out of the FIFO and
transmitted is determined by the oscillator. Logic
circuits adjust the capacitive loading on the crys­tal to set its oscillation frequency to the average
of the TCLK frequency. Signal jitter is absorbed
in the FIFO.

Jitter Tolerance of Jitter Attenuator

The FIFO in the jitter attenuator is designed to
neither overflow nor underflow. If the jitter am­plitude becomes very large, the read and write
pointers may get very close together. Should the
pointers attempt to cross, the oscillator’s divide
by four circuit adjusts by performing a divide by
3 1/2 or divide by 4 1/2 to prevent the overflow
or underflow. When a divide by 3 1/2 or 4 1/2
occurs, the data bit will be driven on to the line
either an eighth bit period early or an eighth bit
period late.

The FIFO of the jitter attenuator in the transmit
path is 192 bits deep. This FIFO will typically be
near the half full point under normal operating
conditions, buffering about 96 bits of data. The
number of bits actually buffered depends on the
relationship of the nominal TCLK frequency to
the center frequency of the crystal oscillator. As
these frequencies deviate, a few bits of FIFO
depth will be lost.

TCLK can have gaps or bursts. As long as the gap
or burst is less than the remaining FIFO depth,
normal operation will continue. For example, if
the nominal TCLK frequency was less than the
oscillator’s center frequency by 40 Hz. The FIFO
will operate 3-4 bits off center or 92 bits full. A
gap in TCLK of 80 cycles would empty the FIFO
by 80 bits but would still not envoke the divide
by 4 1/2 circuitry, as about 12 bits would remain
in the FIFO.

The crystal frequency must be 4 times the nomi­nal signal frequency: 6.176 MHz for 1.544 MHz
operation; 8.192 MHz for 2.048 MHz applica-

tions. Internal capacitors load the crystal, control­ling the oscillation frequency. The crystal must be
designed so that over operating temperature, the
oscillator frequency range exceeds the system fre­quency tolerance. Crystal Semiconductor offers
the CXT6176 & CXT8192 crystals, which yield
optimum performance with the CS61305A.

Receiver

The receiver extracts data and clock from an AMI
(Alternate Mark Inversion) coded signal and out­puts clock and synchronized data. The receiver is
sensitive to signals over the entire range of cable
lengths and requires no equalization or ALBO
(Automatic Line Build Out) circuits. The signal is
received on both ends of a center-tapped, center­grounded transformer. The transformer is
center-tapped on the IC side. The clock and data
recovery circuit exceeds the jitter tolerance speci­fications of Publications 43802, 43801, 62411
amended, TR-TSY-000170, and CCITT REC.
G.823.

A block diagram of the receiver is shown in Fig­ure 11. The two leads of the transformer (RTIP
and RRING) have opposite polarity allowing the
receiver to treat RTIP and RRING as unipolar sig­nals. Comparators are used to detect pulses on
RTIP and RRING. The comparator thresholds are
dynamically established at a percent of the peak
level (50% of peak for E1, 65% of peak for T1;
with the slicing level selected by LEN2/1/0).

The receiver uses an edge detector and a continu­ously calibrated delay line to generate the
recovered clock. The delay line divides its refer­ence clock, ACLKI or the jitter attenuator’s
oscillator, into 13 equal divisions or phases. Con­tinuous calibration assures timing accuracy, even
if temperature or power supply voltage fluctuate.

The leading edge of an incoming data pulse trig­gers the clock phase selector. The phase selector
chooses one of the 13 available phases which the
delay line produces for each bit period. The out-

12 DS157PP3

CS61305A

RTIP

1 : 2

RRING

Data
Level
Slicer

Edge

Detector

Figure 11. Receiver Block Dia gram

put from the phase selector feeds the clock and
data recovery circuits which generate the recov­ered clock and sample the incoming signal at
appropriate intervals to recover the data. The jitter
tolerance of the receiver exceeds that shown in
Figure 12.

The CS61305A outputs a clock immediately upon
power-up and will lock onto the AMI data input
immediately. If loss of signal occurs, the RCLK
frequency will equal the ACLKI frequency.

Data

Sampling

&

Clock

Extraction

Clock

Phase

Selector

Continuously

Calibrated

Delay Line

RPOS
RNEG

RCLK

ACLKI or
Oscillator in Jitter

Attenuator

In the Hardware Mode, data at RPOS and RNEG
is stable and may be sampled on the rising edge
of the recovered clock. In the Extended Hardware
Mode, data at RDATA is stable and may be sam­pled on the fallings edge of the recovered clock.
In the Host Mode, CLKE determines the clock
polarity for which output data is stable and valid
as shown in Table 5.

Jitter and Recovered Clock

The CS61305A is designed for error free clock
and data recovery from an AMI encoded data

Minimum
Performance

10 1k 10k1 100 100k700

JITTER FREQUENCY (Hz)

300

PEAK-TO-PEAK

JITTER

(unit intervals)

300
138

100

AT&T 62411

28

10

1

.4

.1

Figure 12. Minimum Input Jitter Tolerance of Receiver

MODE

(pin 5)

LOW

(<0.2V)

HIGH

(>(V+) - 0.2V)

HIGH

(>(V+) - 0.2V)

MIDDLE

(2.5V)

X = Don’t care

Table 5. Data Output/Clock Relationship

CLKE

(pin 28)

X RPOS

LOW RPOS

HIGH RPOS

DATA CLOCK Clock Edge

for Valid Data

RCLK

RNEG

RCLK
RCLK

RNEG

SDO

RCLK
SCLK

RCLK

RNEG

SDO

RCLK
SCLK

X RDATA RCLK Falling

Rising
Rising

Rising
Rising
Falling

Falling
Falling
Rising

DS157PP3 13

CS61305A

stream in the presence of more than 0.4 unit inter­vals of jitter at high frequency. The clock
recovery circuit is also tolerant of long strings of
zeros. The edge of an incoming data bit causes
the circuitry to choose a phase from the delay line
which most closely corresponds with the arrival
time of the data edge, and that clock phase trig­gers a pulse which is typically 140 ns in duration.
This phase of the delay line will continue to be
selected until a data bit arrives which is closer to
another of the 13 phases, causing a new phase to
be selected. The largest jump allowed along the
delay line is six phases.

When an input signal is jitter free, the phase se­lection will occasionally jump between two
adjacent phases resulting in RCLK jitter with an
amplitude of 1/13 UIpp. These single phase
jumps are due to differences in frequency of the
incoming data and the calibration clock input to
ACLKI. For T1 operation the instantaneous pe­riod can be 14/13 * 648 ns = 698 ns or 12/13 *
648 ns = 598 ns when adjacent clock phases are
chosen. As long as the same phase is chosen, the
period will be 648 ns. Similar calculations hold
for the E1 rate.

The clock recovery circuit is designed to accept at
least 0.4 UI of jitter at the receiver. Since the data
stream contains information only when ones are
transmitted, a clock/data recovery circuit must as­sume a zero when no signal is measured during a
bit period. Likewise, when zeros are received, no
information is present to update the clock recov­ery circuit regarding the trend of a signal which is
jittered. The result is that two ones that are sepa­rated by a string of zeros can exhibit maximum
deviation in pulse arrival time. For example, one
half of a period of jitter at 100 kHz occurs in 5

µs, which is 7.7 T1 bit periods. If the jitter ampli­tude is 0.4 UI, then a one preceded by seven zeros
can have maximum displacement in arrival time,
i.e. either 0.4 UI too early or 0.4 UI too late. The
data recovery circuit correctly assigns a received
bit to its proper clock period if i t is displaced by

less than 6/13 of a bit period from its optimal lo­cation. Theoretically, this would give a jitter
tolerance of 0.46 UI. The actual jitter tolerance of
the CS61305A is only slightly less than the ideal.

In the event of a maximum jitter hit, the RCLK
clock period immediately adjusts to align itself
with the incoming data and prepare to accurately
place the next one, whether it arrives one period
later, or after another string of zeros and is dis­placed by jitter. For a maximum early jitter hit,
RCLK will have a period of 7/13 * 648 ns = 349
ns. For a maximum late jitter hit, RCLK will have
a period of 19/13 * 648 ns = 947 ns.

Loss of Signal

Receiver loss of signal is indicated upon receiv­ing 175 consecutive zeros. A digital counter
counts received zeros based on RCLK cycles. A
zero input is determined either when zeros are re­ceived, or when the received signal amplitude
drops below a 0.3 V peak threshold.

The receiver reports loss of signal by setting the
Loss of Signal pin, LOS, high. If the serial inter­face is used, the LOS bit will be set and an
interrupt issued on INT. LOS will go low (and
flag the INT pin again if serial I/O is used) when
a valid signal is detected. Note that in the Host
Mode, LOS is simultaneously available from both
the register and pin 12.

In a loss of signal state, the RCLK frequency will
be equal to the ACLKI frequency since ACLKI is
being used to calibrate the clock recovery circuit.
Received data is output on RPOS/RNEG regard­less of LOS status. LOS returns to logic zero
when 3 ones are received out of 32 bit periods
containing no more than 15 consecutive zeros.
Also, a power-up or manual reset will set LOS
high.

14 DS157PP3