Cirrus Logic CS5543-KL, CS5542-KL Datasheet

CS5542 CS5543

22-Bit, Multi-Channel

Features

Delta-Sigma Architecture:

- 5th Order Modulator

- 22-Bit Resolution

dc Accuracy (fBW = 250Hz):

- Integral Linearity: ±0.001 % F.S.

- Differential Linearity: ±0.5 LSBs

- RMS Noise: 1.1 pA

Pin Selectable Input Range:

- ±400 nA to ±2.5 µA Full Scale

8-Channel Digital FIR Filter

Self-calibration of Offset and Gain

Low Power: 50 mW /ch for 8-ch system

RMS

∆Σ

ADC Chip Set

Description

The CS5542 / CS5543 chip set is desi gned to be a complete current measurement data acquisition system. The CS5542 is a 22-Bit, 2-channel, 5th-order delta sigma modulator. The CS5543 is a monolithic CMOS, 8channel digital FIR filter designed to be used with up to

four CS5542’s forming an 8-channel system. The complete system is capable of cascading up to 1024 channels.

The system supports 22-bit measurement resolution with output conversion rates up to 1 kHz per channel. JTAG boundary-scan capability is available to facilitate self-test a t the system level.

Potential applications for the CS5542/CS5543 system are environmental monitoring, process control systems, color sensing, light measurement, chemical analyzers and photo-diode transducer applications.

ORDERING INFORMATION

CS5542-KL 0 to 70°C 28-pin PLCC CS5543-KL 0 to 70°C 28-pin PLCC

VA+ VA- GNDLVD+DGND

ICAL MUX

5th Order

Delta-Sigma

Modulator

Left

Channel

Bias

Regulator

5th Order

Delta-Sigma

Modulator

Right

Channel

Calibra-

tion and

Digital

Control

Logic

REFGNDL

INL

ICAL

INR

REFGNDR

VREF+ VREF- GNDR SEL0SEL1

Preliminary Product Information

Cirrus Logic, Inc. Crystal Semiconductor Products Division

P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.crystal.com

VD1+GND1VD2+GND2VD3+GND3

CAPSIZE PDN MCLK FSYNC CAL[1:0] MDATA[3:0]

C[2:0]

CAPSIZE

MCLK

FSYNC

PDN

C[2.0]

CAL[1:0]

TCK

TMS

TDI

TDO

MDATA

[3:0]

DAT ACLK

FRAME

Access

Test Port

Fir Filter

Data Decode

Control/Sequencing

Calibration

System Offset

Noise Calibration

Serial I/O

System Or ITest

DMODE[2:0] RST CLKIN FEGAIN OE DATSEL[3:0]

Registers

Offset/Gain

Gain Calibration

DATAIN[3:0]

DATAOUT

[3:0]

CS5543CS5542

This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.

(All Rights Reserv ed)

DS109PP2

SEP ‘96

CS5542 CS5543

ANALOG CHARACTERISTICS: (T

& DGND= 0V;VREF+ = 4V, VREF- = -4 V; MCLK frequency as noted.)

Parameter Min Typ Max Units

Specified Temperature Range 0 - 70 °C

Accuracy

Full Scale Input Current (Bipolar)

CAPSIZE=0 (Note 1) CAPSIZE=1 (Note 1)

Dynamic Range

CAPSIZE=0 (Note 1)

CAPSIZE=1 (Note 1) Differential Nonlinearity (No Missing Codes) (Note 2) 22 - - Bits Integral Nonlinearity (Note 1) - - 0.001 %FS Full Scale Error (Note 3) - - 0.1 %FS Full Scale Drift (Note 3) - 30 - ppm/°C System Offset Calibratio n Range (Note 4) - - 10 %FS Offset Drift (Note 1) - ±0.3 - LSB/°C Power Supplies (Note 5) Consumption

Active

Powerdown 50, 60 Hz Power Supply Rejection: VA+ or VA- (Notes 1, 6) - TBD - dB Fullscale Current = 400 nA

60 Hz

500 Hz Fullscale Current = 2500 nA

60 Hz

500 Hz

= 25° C; VA+, VD+ = 5 V ± 5%; VA- = -5 V ±5%; GNDL,GNDR,

106 113

400

2500

109 116

1.85

13.5

1.88

15.3

80 10

nA nA

dB dB

mW mW

nA/V nA/V

Notes: 1. Full scale current is tested under two conditions: CAPSIZE = 0 (CDAC = 1.6 pF) with MCLK at 1.024

MHz and CAPSIZE = 1 (CDAC = 4.8 pF) with MCLK at 2.048 MHz. Dynamic Range (Signal -to-No ise) i s tested with 101 Hz si ne wave voltage dr iven into a 5 M from INR or INL to REFGNDR or REFGNDL respectively, to test each modulator. S/N and integral nonlinearity are tested with CAPSIZE = 0 (CDAC = 1.6 pF) with MCLK at 2.048 MHz and CAPSIZE = 1 (CDAC = 4.8 pF) with MCLK at 1.024 MHz.

2. Guaranteed by design or characterization.

3. Specificatio n applies after a complete calibrati on sequence using the CS5542/CS5543 combi nation. Drift specification i s for the CS5542/CS554 3 only and does not include drift due to the input components, the VREF voltage, or a frequency change of CLKIN.

4. Specification ap plies only to System Offse t Calibrat ion using the CS5542/ CS5543 chip combin ation aft er Input Offset Voltage calibration has been completed with no external offset applied to the input.

5. The VA+ and VA- supplies should be quiet supplies (see data sheet text). Power supply sequence is important. The VA+ and VA- supplies should be applied to the CS5542 prior to or at the same time as the VD+ supply.

6. Power supply rejection is tested with a 100 mVp-p sine wave applied to each supply. See data sheet text for power supply noise requirements.

2 DS109PP2

Ω input resisto r with a 470 pF capac itor connect ed

MCLK

(2048 x OWR)

FSYNC

(Modulator

Fs Rate)

SLOT6 SLOT7 SLOT0 SLOT1 SLOT2 SLOT3 SLOT4 SLOT5 SLOT7SLOT6

(Previou s

Frame)

(Previous

Frame)

ONE FRAME

8 CHANNELS

4 SLOT-PAIRS

CS5542 CS5543

MDATA3:0

MCLK

CHIP #4 ACTIVE (Previous Frame)

INTER-CHIP

HANDOFF POINT

CHIP #1 ACTIVE

SLOT PAIR #1

CHIP #2 AC TIVE

SLOT PAIR #2

CHIP #3 ACTIVE

SLOT PAIR #3

CHIP #4 ACTIVE

SLOT PAIR #4

CS5542 Frame Timing Overview

ONE SLOT

PAIR

MDATA[3:0]

LEFT DATA

RIGHT

DATA

HI-Z STATE (Note 1)HI-Z STATE (Note 1)

Notes

Hi-Z State shown as intermediate level for clarity only. Bus capacitance would n or mall y maintain valid logic one level during Hi-Z until next time slot pair becomes active.

CS5542 MDATA3-MDATA0 Output Timing Characteristics

DS109PP2 3

CS5542 CS5543

CS5542 / CS5543 SYSTEM SWITCHING CHARACTERISTICS: (T

VD2+ = VD3+ = 5 V ±5%; GND1 = GND2 = GND3 = 0 V; For timing parameters: CLKIN= 2.048 MHz; DATACLK =

6.144 MHz; MCLK = 2.048 MHz; Outputs loaded with 50 pF.)

Parameter Number Min Typ Max Units

CS5542 Modulator Timing

MCLK Frequency 0 1.024 - 2.048 MHz MCLK Duty Cycle 1 40 - 60 %

FSYNC Frequency 2 FSYNC set-up before MCLK rising edge 3 70 - - ns

FSYNC hold time after MCLK rising edge 4 70 - - ns MCLK rising to MDATA[3:0] valid 5 70 ns MCLK rising to MDATA[3:0] high 6 70 ns MCLK falling to MDATA[3:0] to Hi-Z 7 70 ns MCLK falling to MDATA[3:0] active 8 70 ns

CS5543 System Timing

CLKIN Frequency (1/Clock Period) 9 1.024 - 2.048 MHz CLKIN Duty Cycle 10 40 - 60 % DATACLK Frequency (1/Clock Period) 11 3.072 - 6.144 MHz DATACLK Duty Cycle 12 40 - 60 % FRAME rising to CLKIN rising 13 20 ns FRAME rising to next DATACLK rising 14 20 ns FRAME period 15 1 ms CLKIN rising to MCLK rising 16 0 50 ns CLKIN falling to MCLK falling 17 0 50 ns

CS5542 /CS5543 Interface

FSYNC period 18 - 7.81 - µs MCLK falling to FSYNC rising or falling 19 0 70 ns

CS5543 to CS5543 Interface

DATACLK rising to DATAOUT valid 20 65 ns DATAIN set-up time before DATACLK rising 21 0 15 ns DATAIN hold time after DATACLK rising 22 15 15 ns

MCLK/

= 25°C, VD1+ =

-Hz

4 DS109PP2

DATACLK

TCK, CLKIN

FRAME

DATAIN [3:0]

DATAOUT [3:0]

DMODE [2:0],

DATSEL[3:0],

JTAG pins,

OE, FEGAIN

MCLK

FSYNC

CS5542 CS5543

16 17

CS5542/CS5543 System Timing Diagram

valid data

Output Word Cycle N - 1 N N + 1 N + 2 N + 3

1 Filter Output Time

FRAME

CLKIN

DATACLK

DATAOUT [3:0]

N - 2N - 3

N - 1

Expanded inter-view timing

FRAME

CLKIN

DATACLK

DATAOUT [3:0]

parity bit from

"most remote" channel

(end of Frame N-3)

sign bit from

"nearest" channel

(beginning of Frame N-2)

Multi-Frame System Timing Diagram

DS109PP2 5

CS5542 CS5543

CS5543 FILTER CHARACTERISTICS: (T

GND2 = GND3 = 0 V; Output Word Rate (OWR) = CLKIN/2048)

Parameter Min Typ Max Units

Passband - - 0.5 OWR

-3 dB Frequency - 0.536 - OWR Equivalent Noise Bandwidth 0.536 OWR

Stop Band 0.016 0.5 Stop Band Rejection (CS5543 only) 120 dB

Stop Band Rejection (CS5542/43 Combination) 127 dB Group Delay 3/OWR s Group Delay vs. Frequency (Linear Phase) 0 s Decimation Ratio (CS5543 input to output) 128

= 25°C, VD1+ = VD2+ = VD3+ = 5 V ±5%; GND1 =

128 X

OWR

6 DS109PP2

CS5542 CS5543

-30

-60

-90

-120

-150

H(z), dB

-180

-210

-240

-270

-300

0.0 0.1 0.2 0.3 0.4 0.5

Normalized to Modulator Sample Frequency

Modulator Sample Frequency = MCLK/16; Output Word Rate = MCLK/2048 Hz

Digital Filter Total Response

-0.0

-0.3

-0.6

-0.9

-1.2

-1.5

H(z), dB

-1.8

-2.1

-2.4

-2.7

-3.0

0.0 0.1 0.2 0. 3 0.4 0.5

Normalized to Output Word Rate

CS5543 Digital Filter Passband Response

DS109PP2 7

CS5542 CS5543

CS5542 DIGITAL CHARACTERISTICS: (T

= 25°C, VD+ = 5 V ±5%; DGND = 0V; Output loaded

with 50 pF)

Parameter Symbol Min Typ Max Units

High-Level Input Voltage V Low-Level Input Voltage V High-Level Output Voltage (I Low-Level Output Voltage (I

out = 600µA) Voh VD+ -0.4 - - V

out = 800µA) Vol --0.4V

Input Leakage Current (All pins except OE = Logic 0) I Input Leakage Current (OE pin only, OE pin = Logic 0) I

Output Leakage Current

ih VD+ -1.0 - - V

il --1V

in --10µA in --25µA

out

--10µA Digital Input Capacitance Cin -7-pF Digital Output Capacitance C

out -7-pF

CS5542 RECOMMENDED OPERATING CONDITIONS: (GNDR = GNDL = REFGNDR =

REFGNDL = DGND = 0V)

Operating Voltages

Positive Analog VA+ 4.75 5.0 +5.25 V Negative Analog VA- -4.75 -5.0 -5.25 V Positive Digital VD+ 4.75 5.0 +5.25 V VREF+ VREF+ 2.0 4.0 4.1 V VREF- VREF- -2.0 -4.0 -4.1 V

Parameter Symbol Min Typ Max Units

CS5542 ABSOLUTE MAXIMUM RATINGS*: (Voltages with respect to GND = 0V)

Parameter Symbol Min Typ Max Units

Source Transient Voltage into INL and INR inputs (Note 7) - - 1000 V Source Transient Current into I NL and INR inputs - - 100 mA Operating Voltages

Positive Analog Negative Analog

Positive Digital Input Current, Any Pin Except Supplies I Digital Input Voltage V Storage Temperature T

Notes: 7. Transient model is 100 pF through a 1500 ohm source resistance. *Warning: Operation beyond these limits may result in permanent damage to the device Normal operations not guaranteed at these extremes

VA+

VA-

VD+

in --±10mA

IND -0.3 - (VD+)+0.3 V

stg -65 150 °C

-0.3

+0.3

0.3

6.0

-6.0

(VA+)+0.3

V V V

8 DS109PP2

CS5542 CS5543

CS5543 POWER SUPPLY: (T

= 25°C; CLKIN = 2.048 MHz; DATACLK = 6.144 MHz, VD+ = 5.25 V;

GND1 = GND2 = GND3 = 0V)

Parameter Symbol Min Typ Max Units

Consumption

Active Powerdown

CS5543 DIGITAL CHARACTERISTICS: (T

= 25°C, VD+ = 5 V ±5%; GND1 = GND2 = GND3 =

1700

0V; Output loaded with 50 pF)

Parameter Symbol Min Typ Max Units

High-Level Input Vol tage V Low-Level Input Voltage V High-Level Output Voltage (I Low-Level Output Voltage (I

out = -600µA) Voh VD+-0.4 - - V

out = 800µA) Vol --0.4V

Input Leakage Current I Output Leakage Current

ih VD+-1.0 - - V

il --1V

in --10µA

out

--10µA Digital Input Capacitance Cin -7-pF Digital Output Capacitance C

out -7-pF

CS5543 RECOMMENDED OPERATING CONDITIONS: (GND1 = GND2 = GND3 = 0V, All

voltages with respect to 0V.)

Parameter Symbol Min Typ Max Units

Digital DC Supply VD+ 4.75 5.0 5.25 V Supply Voltage Required to Maintain Ca li bration Information 4.0 - - V

CS5543 ABSOLUTE MAXIMUM RATINGS*: (GND = 0V, All voltages with respect to 0V.)

Parameter Symbol Min Typ Max Units

Power Supplies: VD1+

VD2+ VD3+

Input Current (Except Supply Pins) Digital Input Voltage

inp

Storage Temperature Tstg -65 150 °C

*Warning: Operation beyond these limits may result in permanent damage to the device Normal operations not guaranteed at these extremes

-0.3 6.0 V

±10.0 mA

-0.3 (VD+)+0.3 V

DS109PP2 9

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