Cirrus Logic CS5541-BS Datasheet

CS5541

Low-Power, Low-Voltage, 24-Bit ∆Σ ADC

Features

l ∆Σ Analog-to-Digital Converter

- Linearity Error: 0.0015% FS

- RMS Noise: 2 µV

l Two Channel Differential MUX l Buffered, Fully Differential Analog and

Voltage Reference Inputs

l Scalable V l Absolute Accuracy via Calibration l Flexible Digital Filters

- Single Conversion Settling at 13.4 SPS or 4 Conversion Settling at 53.7 SPS with Simultaneous 50/60 Hz Rejection

- Single Conversion Settling at 64.8 SPS or Four Conversion Settling at 260 SPS with 16-bit Resolution

l Simple 3-Wire Serial Interface

- SPITM and MicrowireTM Compatible

- Schmitt Trigger on Serial Clock (SCLK)

l Low Power

- Single +3.0 V Supply

- 330 µA Operating; 10 µA Sleep Current

Input: 0.1 V to Analog Supply

REF

Description

The CS5541 is a 24-bit low-power and low-voltage ∆Σ analog-to-digital converter (ADC). It is optimized to convert analog signals in DC measurement applications, such as temperature and pressure measurement, and various portable devices where low-power consumption is required.

To accommodate these applications, the ADC integrates analog input and reference buffers for increased input impedance and includes a two-channel multiplexer. Absolute accuracy is achieved via one-time or continuous calibration modes. The device draws less than 330µA.

The CS5541 includes two digital filters. The first filter, which achieves simultaneous rejection of 50/60 Hz, provides single conversion settling at 13.4 SPS throughput or four conversion settling at 53.7 SPS throughput. The second filter, which achieves 16-bit performance, provides single conversion settling at 64.8 SPS throughput or four conversion settling at 260 SPS throughput.

Low-power, low-voltage operation and an easy-to-configure serial interface reduces time-to-market and makes the CS5541 an ideal device for low-cost, power-conscious DC measurement applications.

ORDERING INFORMATION

CS5541-BS-40 ºC - +85 ºC 16-Pin SSOP

VA+

AIN1+

AIN1-

AIN2+

AIN2-

VA-

Input Mux

Preliminary Product Information

P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com

VREF+ VREF-

Differential 4th Order

Modulator

This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.

∆Σ

OSC1 OSC2

Clock Generator

Digital Filter

Serial Interface

Calibration Register

Output Register

VD+

DGND

SDI

SDO

SCLK

JUN ‘01

DS500PP1

TABLE OF CONTENTS

1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 4

2. GENERAL DESCRIPTION ..................................................................................................... 10

2.1 Analog Input ..................................................................................................................... 10

2.1.1 Analog Input Model ............................................................................................. 10

2.2 Voltage Reference Input .................................................................................................. 11

2.2.1 Voltage Reference Input Model ........................................................................... 11

2.3 Power Supply Arrangements ........................................................................................... 12

2.4 Clock Generator ............................................................................................................... 12

2.5 Serial Port Interface ......................................................................................................... 12

2.6 Serial Port ........................................................................................................................ 13

2.7 Serial Port Initialization Sequence ................................................................................... 14

2.8 Command Register Quick Reference ............................................................................. 15

2.9 Performing Conversions/Calibrations .............................................................................. 16

2.9.1 Continuous Calibrations and Conversions (reduced output rate) ....................... 16

2.9.2 One Time Calibration followed by Continuous Conversions ............................... 17

2.9.3 Continuous Conversions with Default Calibration Coefficients ........................... 17

2.9.4 Continuous Conversions with Existing Calibration Coefficients .......................... 17

2.9.5 System Calibration .............................................................................................. 17

2.9.6 Reading Conversions .......................................................................................... 17

2.9.7 Output Coding ..................................................................................................... 18

2.9.8 Digital Filter ......................................................................................................... 18

2.10 Sleep and Standby Modes ............................................................................................. 20

2.11 Power-Up Sequence and Initialization ........................................................................... 20

2.12 PCB Layout .................................................................................................................... 20

3. PIN DESCRIPTIONS .............................................................................................................. 22

4. SPECIFICATION DEFINITIONS ............................................................................................. 24

CS5541

Contacting Cirrus Logic Support

For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:

http://www.cirrus.com/corporate/contacts/

SPI is a trademark of Motorola Inc. Microwire is a trademark of National Semiconductor Corp.

Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty

of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.

2 DS500PP1

LIST OF FIGURES

Figure 1. Continuous Running SCLK Timing (Not to Scale) ................................ 9

Figure 2. SDI Write Timing (Not to Scale) ............................................................ 9

Figure 3. SDO Read Timing (Not to Scale) .......................................................... 9

Figure 4. Multiplexer Configuration. ................................................................... 10

Figure 5. Input model for AIN+ and AIN- pins. ................................................... 10

Figure 6. Resolution vs. Voltage Reference ....................................................... 11

Figure 7. Resolution vs. Voltage Reference ....................................................... 11

Figure 8. Input model for VREF+ and VREF- pins. ............................................ 11

Figure 9. CS5541 Configured with +3.0 V Analog Supply. ................................ 12

Figure 10. CS5541 Register Diagram. ............................................................... 13

Figure 11. Command and Data Word Timing. ................................................... 13

Figure 12. Self Calibration of Offset. .................................................................. 16

Figure 13. Self Calibration of Gain. .................................................................... 16

Figure 14. Digital Filter 1 Response ................................................................... 19

Figure 15. Filter 2 Response (MCLK = 32.768 kHz) .......................................... 19

LIST OF TABLES

Table 1. Filter Output Word Rates ................................................................................................ 14

Table 2. Output Conversion Data Register Description (24 bits + flags) ...................................... 18

Table 3. CS5541 24-Bit Output Coding......................................................................................... 19

CS5541

DS500PP1 3

1. CHARACTERISTICS AND SPECIFICATIONS

CS5541

ANALOG CHARACTERISTICS (T

= 0 V, VREF+ = 2.5 V, VREF- = 0 V, MCLK = 32.768 kHz, OWR (Output Word Rate) = 53.7 SPS, Bipolar Mode, Input Range = ±2.5 V Differential, Vcm=1.25 V.) (See Notes 1 and 2.)

Parameter Min Typ Max Units

Accuracy

Linearity Error - ±0.0015 ±0.003 %FS

No Missing Codes 24 - - Bits

Bipolar Offset (Note 3) - ±16 TBD LSB

Unipolar Offset (Note 3) - ±32 TBD LSB

Offset Drift (Notes 3 and 4) - 20 - nV/°C

Bipolar Full Scale Error - ±8 ±31 ppm

Unipolar Full Scale Error - ±16 ±62 ppm

Full Scale Drift (Note 4) - 1 - ppm/°C

Noise

(Notes 5, 6, and 7)

Filter Type Output Word Rate (SPS) -3 dB Filter Frequency (Hz) RMS Noise (µV)

Single Conversion Settling with

50/60 Hz Rejection

Four Conversion Settling with

50/60 Hz Rejection

Fast Filter with

Single Conversion Settling

Fast Filter with

Four Conversion Settling

= 25 °C; VA+ = +3 V ±5%, VA- = 0 V, VD+ = +3.0 V ±5%, DGND

13.4 11.96 2

53.7 11.96 2

64.8 56.91 35

260 56.91 35

Notes: 1. Applies after a one-time self-calibration at any temperature within -40 °C ~ +85 °C.

2. Specifications guaranteed by design, characterization, and/or test.

3. Specification applies to the device only and does not include any effects by external parasitic thermocouples.

4. Drift over specified temperature range after calibration at power-up at 25 °C.

5. Wideband noise aliased into the baseband. Referred to the input. Typical values shown for 25 °C.

6. For peak-to-peak noise multiply by 6.6 for all ranges and output rates.

7. RMS noise numbers assume continuous calibration mode is not used. In continuous calibration mode the noise increases by a factor of two.

* Specifications are subject to change without notice.

4 DS500PP1

CS5541

ANALOG CHARACTERISTICS (Continued)

Parameter Min Typ Max Units

Analog Inputs

Common Mode + Signal on AIN+ or AIN- (Bipolar/Unipolar Mode)

Single Supply Dual Supply

CVF Current on AIN+, AIN- (Note 8) - 12 - nA

Input Leakage for MUX when off - 10 - pA

Common Mode Rejection dc

50, 60Hz

Input Capacitance - 8 - pF

Voltage Reference Inputs

Range (VREF+) - (VREF-) (Note 10) 0.1 2.5 (VA+) -

CVF Current on VREF+ and VREF- (Note 9) - 20 - nA

Common Mode Rejection dc

50, 60 Hz

Input Capacitance - 12 - pF

Dynamic Characteristics

Modulator Sampling Frequency - MCLK/2 - Hz

Filter Settling to 1/2 LSB (Full Scale Step) (Note 11)

13.4 SPS OWR

53.7 SPS OWR

64.8 SPS OWR 260 SPS OWR

Power Supplies

DC Power Supply Currents (Normal Mode)

A+

D+

Power Consumption Normal Mode (Note 12)

Standby Mode Sleep Mode

Power Supply Rejection dc Positive Supplies

dc Negative Supply

0.0

VA-

120 120

1/OWR 4/OWR 1/OWR 4/OWR

225

750

75 30

80 80

VA+ VA+

(VA-)

280

1000

dB dB

µA µA

µW µW µW

dB dB

V V

s s s s

Notes: 8. See Section

9. See Section

10. VREF must be less than or equal to supply voltages.

11. The CS5541 includes two digital filters. The first filter, which achieves simultaneous rejection of 50/60 Hz, provides single conversion settling at 13.4 SPS throughput or four conversion settling at 53.7 SPS throughput. The second filter, which achieves 16-bit performance, provides single conversion settling at

64.8 SPS throughput or four conversion settling at 260 SPS throughput.

12. All outputs unloaded. All digital inputs at CMOS levels.

DS500PP1 5

2.1, “Analog Input”.

2.2, “Voltage Reference Input”.

CS5541

3 V DIGITAL CHARACTERISTICS (T

= 25 °C; VA+ = 3.0 V ±5%, VA- = 0 V, VD+ = 3.0 V ± 5%,

DGND = 0 V.)(See Notes 2 and 13.)

Parameter Symbol Min Typ Max Units

High-Level Input Voltage: All Pins Except OSC1, SCLK

OSC1

SCLK

Low-Level Input Voltage: All Pins Except OSC1, SCLK

OSC1

SCLK

High-Level Output Voltage: (SDO pin) I

Low-Level Output Voltage: (SDO pin) I

= -1.0 mA V

out

= 1.0 mA V

out

Input Leakage Current I

3-State Leakage Current I

Digital Output Pin Capacitance C

Notes: 13. All measurements performed under static conditions.

V V V

out

0.6VD+ TBD

(VD+)-0.45

(VD+)-0.25 - - V

--0.2V

-±1±10µA

--±10µA

-9-pF

0.16VD+ TBD

0.6

V V V

6 DS500PP1

CS5541

ABSOLUTE MAXIMUM RATINGS (DGND = 0 V) (See Note 14.)

Parameter Symbol Min Typ Max Units

DC Power Supplies (Notes 15 and 16)

Positive Digital

Positive Analog

Negative Analog

Input Current, Any Pin Except Supplies (Notes 17 and 18) I

Output Current I

Power Dissipation (Note 19) PDN - - 500 mW

Analog Input Voltage AIN and VREF pins V

Digital Input Voltage V

Ambient Operating Temperature T

Storage Temperature T

Notes: 14. All voltages measured with respect to digital ground (DGND).

15. VA+ and VA- must satisfy {(VA+) - (VA-)} ≤ +4.0 V.

16. VD+ and VA- must satisfy {(VD+) - (VA-)} ≤ +4.0 V.

17. Applies to all pins including continuous overvoltage conditions at the analog input (AIN) pins.

18. Transient currents up to 100 mA will not cause SCR latch-up. Maximum input current for a power supply pin is ±50 mA.

19. Total power dissipation, including all input currents and output currents.

VD+ VA+

VA-

OUT

INA

IND

stg

-0.3

+4.0 +4.0 +0.3

--±10mA

--±25mA

(VA-) + (-0.3) - (VA+)+0.3 V

-0.3 - (VD+)+0.3 V

-40 - +85 °C

-65 - +150 °C

V V V

WARNING: Operation at or beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes.

DS500PP1 7

CS5541

SWITCHING CHARACTERISTICS (T

DGND = 0 V; Input Levels: Logic 0 = 0 V, Logic 1 = VD+; C

= 25 °C; VA+ = +3.0 V ±5% VA- = 0 V, VD+ = 3.0 V ±5%,

= 50 pF)

Parameter Symbol Min Typ Max Units

Master Clock Frequency: External Clock

Internal Oscillator (Note 20)

MCLK 5

32.768

kHz

Master Clock Duty Cycle 40 - 60 %

Rise Times (Note 21)

Any Digital Input Except SCLK

SCLK

Any Digital Output

Fall Times (Note 21)

Any Digital Input Except SCLK

SCLK

Any Digital Output

rise

1.0

100

1.0

100

µs µs ns

Start-up

Oscillator Start-up Time XTAL = 32.768 kHz (Note 22) t

Power-on-Reset Period t

ost

por

-500-ms

-490-MCLK cycles

Serial Port Timing

Serial Clock Frequency SCLK 0 - 2 MHz

Serial Clock Pulse Width High

Pulse Width Low

250 250

ns ns

SDI Write Timing

Enable to SCLK Rising t

Data Set-up Time prior to SCLK rising t

Data Hold Time After SCLK Rising t

SCLK Falling Prior to CS

Disable t

50 - - ns

100 - - ns

SDO Read Timing

to Data Valid t

SCLK Falling to New Data Bit t

Rising to SDO Hi-Z t

--150ns

Notes: 20. Device parameters are specified with 32.768 kHz clock; however, clocks up to 40 kHz can be used for

increased throughput.

21. Specified using 10% and 90% points on waveform of interest. Output loaded with 50 pF.

22. Oscillator start-up time varies with crystal parameters. This specification does not apply when using an external clock source.

8 DS500PP1

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