Cirrus Logic CS5540-AS Datasheet

CS5540

Low-Power, Low-Voltage, 24 - Bit ∆Σ ADC

Features

l ∆Σ Analog-to-Digital Converter

- Linearity Error: 0.0015% FS

- RMS Noise: 4 µV

l Two Channel Differential MUX l Buffered, Fully Differential Analog and

Voltage Reference Inputs

l Scalable V l High Absolute Accuracy via Self-Calibration l Fixed Digital Filter

- Single Conversion Settling at 6.7 SPS

- Simultaneous 50/60 Hz Rejection

l Simple Serial Interface

- SPITM and MicrowireTM Compatible

- Schmitt Trigger on Serial Clock (SCLK)

l Low Power

- Single +3.0 V Supply

- 330 µA Supply Current

- 10 µA in Sleep Mode

Input: 0.1 V to Analog Supply

REF

Description

The CS5540 is a low-power and low-voltage ∆Σ analog-to-digital converter (ADC), which achieves highly accurate conversions using a simple non-programmable interface that is easy to understand and design-in. It is optimized to convert analog signals in DC measurement applications, such as temperature and pressure measurement, and various portable devices where low-power consumption is required.

To accommodate these applications, the ADC integrates analog input and reference buffers for increased input impedance and a two-channel multiplexer.

The CS5540 includes a digital filter, which achieves simultaneous rejection of 50/60 Hz signals and provides single conversion settling at 6.7 SPS throughput. Absolute accuracy is achieved via continuous internal self-calibration. The device draws a nominal 330 µA.

Low-power, low-voltage operation, and a simple serial interface make the CS5540 an ideal device for low-cost, power-conscious DC measurement applications.

ORDERING INFORMATION

CS5540-AS -40 ºC - +85 ºC 16-Pin SSOP

CHS

AIN1+

AIN1-

AIN2+

AIN2-

VA+

Input

Mux

VA-

VREF+

Preliminary Product Information

P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com

VREF-

Differential 4th Order

Modulator

This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.

∆Σ

OSC1 OSC2

Clock Generator

Digital Filter

VD+

Serial Interface

Calibration Register

Output Register

DGND

SDO

SCLK

JUN ‘01

DS503PP1

TABLE OF CONTENTS

1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 4

2. GENERAL DESCRIPTION ..................................................................................................... 10

2.1 Analog Input ..................................................................................................................... 10

2.1.1 Analog Input Model ............................................................................................. 10

2.2 Voltage Reference Input .................................................................................................. 11

2.2.1 Voltage Reference Input Model ........................................................................... 11

2.3 Power Supply Arrangements ........................................................................................... 12

2.4 Clock Generator ............................................................................................................... 12

2.5 Serial Port Interface ......................................................................................................... 12

2.6 Input Channel Selector .................................................................................................... 12

2.6.1 Switching Channels ............................................................................................. 13

2.7 Serial Port and Data Conversions .................................................................................... 13

2.7.1 Reading Conversions .......................................................................................... 14

2.7.2 Output Coding ..................................................................................................... 14

2.7.3 Digital Filter ......................................................................................................... 14

2.8 Sleep Mode ...................................................................................................................... 15

2.9 Power-Up and Initialization .............................................................................................. 16

2.10 PCB Layout .................................................................................................................... 16

3. PIN DESCRIPTIONS .............................................................................................................. 17

4. SPECIFICATION DEFINITIONS ............................................................................................. 19

5. PACKAGE DIMENSIONS ...................................................................................................... 20

CS5540

Contacting Cirrus Logic Support

For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:

http://www.cirrus.com/corporate/contacts/

SPI is a trademark of Motorola Inc. Microwire is a trademark of National Semiconductor Corp.

Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty

of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.

2 DS503PP1

LIST OF FIGURES

Figure 1. Continuous Running SCLK Timing (Not to Scale) ........................................................... 9

Figure 2. SDO Read Timing (Not to Scale)..................................................................................... 9

Figure 3. Multiplexer Configuration. .............................................................................................. 10

Figure 4. Input model for AIN+ and AIN- pins. .............................................................................. 10

Figure 5. Resolution vs. Voltage Reference.................................................................................. 11

Figure 6. Input model for VREF+ and VREF- pins. ....................................................................... 11

Figure 7. CS5540 Configured with a single +3.0 V Supply. .......................................................... 12

Figure 8. Command and Data Word Timing. ................................................................................ 13

Figure 9. Self Calibration of Offset. ............................................................................................... 13

Figure 10. Self Calibration of Gain. ............................................................................................... 14

Figure 11. Digital Filter Response................................................................................................. 15

LIST OF TABLES

Table 1. Output Conversion Data Register Description (24 bits + flags) ...................................... 15

Table 2. CS5540 24-Bit Bipolar Output Coding ............................................................................ 15

CS5540

DS503PP1 3

1. CHARACTERISTICS AND SPECIFICATIONS

CS5540

ANALOG CHARACTERISTICS (T

DGND = 0 V, VREF+ = 2.5 V, VREF- = 0 V, MCLK = 32.768 kHz, OWR (Output Word Rate) = 6.7 SPS, Input Range = ±2.5 V Differential, Vcm=1.25 V. (See Note 1.)

Parameter Min Typ Max Units

Accuracy

Linearity Error - ±0.0015 ±0.003 %FS

No Missing Codes 24 - - Bits

Offset Error (Note 2) - ±16 TBD LSB

Offset Drift (Notes 2 and 3) - 20 - nV/°C

Full Scale Error - ±8 ±31 ppm

Full Scale Drift (Note 3) - 1 - ppm/°C

RMS Noise (Notes 4 and 5) - 4 - µV

Bandwidth (-3 dB) - 11.96 - Hz

Notes: 1. Specifications guaranteed by design, characterization, and/or test.

2. Specification applies to the device only and does not include any effects caused by external parasitic thermocouples.

3. Drift over specified temperature range after power-up at 25 °C.

4. Wideband noise aliased into the baseband. Referred to the input. Typical values shown for 25 °C.

5. For peak-to-peak noise multiply the RMS value by 6.6.

= 25 °C; VA+ = +3.0 V ±5%, VA- = 0 V, VD+ = 3.0 V ±5%,

* Specifications are subject to change without notice.

4 DS503PP1

CS5540

ANALOG CHARACTERISTICS (Continued)

Parameter Min Typ Max Units

Analog Input

Common Mode + Signal on AIN+ or AIN-

Single Supply Dual Supplies

CVF Current on AIN+, AIN- (Note 6) - 12 - nA

Input Leakage for MUX when off - 10 - pA

Common Mode Rejection dc

50, 60Hz

Input Capacitance - 8 - pF

Voltage Reference Input

Range (VREF+) - (VREF-) (Note 8) 0.1 2.5 (VA+) -

CVF Current on VREF+ and VREF- (Note 7) - 20 - nA

Common Mode Rejection dc

50, 60 Hz

Input Capacitance - 12 - pF

Dynamic Characteristics

Modulator Sampling Frequency - MCLK/2 - Hz

Filter Settling to 1/2 LSB (Full Scale Step) (Note 9)

6.7 SPS OWR

Power Supplies

DC Power Supply Currents (Normal Mode)

A+

D+

Power Consumption Normal Mode (Note 10)

Sleep Mode

Power Supply Rejection dc Positive Supplies

dc Negative Supplies

0.0

VA-

-1/OWR - s

120 120

225

750

80 80

VA+ VA+

(VA-)

280

1000

dB dB

µA µA

µW µW

dB dB

V V

Notes: 6. See Section 2.1, “Analog Input”.

7. See Section 2.2, “Voltage Reference Input”.

8. Absolute voltages on VREF+ and VREF- must be less than or equal to the supply voltages.

9. The CS5540 includes a digital filter. The filter which achieves simultaneous rejection of 50/60 Hz provides single conversion settling at a 6.7 SPS throughput.

10. All outputs unloaded. All inputs at CMOS levels.

DS503PP1 5

CS5540

3 V DIGITAL CHARACTERISTICS (T

= 25 °C; VA+ = 3.0 V ±5%, VA- = 0 V, VD+ = 3.0 V ± 5%,

DGND = 0 V.) (See Notes 1 and 11.) All voltage levels measured relative to DGND.

Parameter Symbol Min Typ Max Units

High-Level Input Voltage: All Pins Except OSC1, SCLK

OSC1

SCLK

Low-Level Input Voltage: All Pins Except OSC1, SCLK

OSC1

SCLK

High-Level Output Voltage: SDO, I

Low-Level Output Voltage: SDO, I

= -1.0 mA V

out

= 1.6mA V

out

Input Leakage Current I

3-State Leakage Current I

Digital Output Pin Capacitance C

V V V

out

0.6VD+

(VD+)-0.45

(VD+)-.25 - - V

Notes: 11. All measurements performed under static conditions.

TBD

0.16VD+ TBD

0.6

V V V

--0.4V

-±1±10µA

--±10µA

-9-pF

6 DS503PP1

CS5540

ABSOLUTE MAXIMUM RATINGS (DGND = 0 V; See Note 12.)

Parameter Symbol Min Typ Max Units

DC Power Supplies (Notes 13 and 14)

Positive Digital

Positive Analog

Negative Analog

Input Current, Any Pin Except Supplies (Notes 15 and 16) I

Output Current I

Power Dissipation (Note 17) PDN - - 500 mW

Analog Input Voltage AIN and VREF pins V

Digital Input Voltage V

Ambient Operating Temperature T

Storage Temperature T

Notes: 12. All voltages are measured with respect to the digital ground pin (DGND).

13. VA+ and VA- must satisfy {(VA+) - (VA-)} ≤ +4.0 V.

14. VD+ and VA- must satisfy {(VD+) - (VA-)} ≤ +4.0 V.

15. Applies to all pins including continuous overvoltage conditions at the analog input (AIN) pins.

16. Transient current of up to 100mA will not cause SCR latch-up. Maximum input current for a power supply pin is ±50 mA.

17. Total power dissipation, including all input currents and output currents.

VD+ VA+

VA-

OUT

INA

IND

stg

-0.3

+4.0 +4.0 +0.3

--±10mA

--±25mA

(VA-) + (-0.3) - (VA+)+0.3 V

-0.3 - (VD+)+0.3 V

-40 - +85 °C

-65 - +150 °C

V V V

WARNING: Operation at or beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes.

DS503PP1 7

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Cirrus Logic CS5540-AS Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

Features

Description

1. CHARACTERISTICS AND SPECIFICATIONS