Cirrus Logic CS5534-BS, CS5534-AS, CS5533-AS, CS5532-BS, CS5532-AS Datasheet

CS5531/32/33/34

16-Bit and 24-Bit ADCs with Ultra Low Noise PGIA

Features



Chopper Stabilized PGIA (Programmable
Gain Instrumentation Amplifier, 1x to 64x)

6nV/√Hz @ 0. 1 Hz (No 1/f noise) at64x
500 pA Input Current with Gains >1



Delta-Sigma Analog-to-Digital Converter

Linearity Error: 0.0007% FS
Noise Free Resolution: Up to 23 bits



Two or Four Channel Differential MUX



Scalable Input Span via Calibration

±5 mV to differential ±2.5V



Scalable V



Simple three-wire serial interface

SPIand Microwire™ Com patible
Schmitt Trigger on Serial Clock (SCLK)



R/W Calibration Registers Per Channel



Selectable Word Rates: 6.25 to 3,840 Sps



Selectable 50 or 60 Hz Rejection



Power Supply Configurations

VA+=+5V;VA-=0V;VD+=+3Vto+5V
VA+=+2.5V;VA-=-2.5V;VD+=+3Vto+5V
VA+ = +3 V; VA- = -3 V; VD+ = +3 V

Input: Up to Analog Supply

REF

General Description

The CS5531/32/33/34 are highly integrated ∆Σ Analog­to-Digital Converters (ADCs) which use charge-balance
techniques to achieve 16-bit (CS5531/33) and 24-bit
(CS5532/34) performance. The ADCs are optimized f or
measuring low-level unipolar or bipolar signals in weigh
scale, process control, scientific, and medical
applications.

To accommodate these applications, the ADCs c ome as
either two-channel (CS5531/ 32) or four-channel
(CS5533/34) devices and include a very low noise chop­per-stabilized instrum entation amplifier (6 nV/√Hz
Hz) with selectable gains of 1×, 2×, 4×, 8×, 16×, 32×, and
64×. These ADCs also include a fo urth order ∆Σ modu­lator followed by a digital filter

which provides twenty
selectableoutput wordrates of 6.25, 7.5, 12.5, 15, 25, 30,
50, 60, 100, 120, 200, 240, 400, 480, 800, 960, 1600,
1920, 3200, and 3840 Sps (MCLK = 4.9152 MHz).

To ease communication between the ADCs and a micro­controller, the c onv ert ers include a simple three-wire se­rial interface which is SPI and Microwire compatible with
a S c hmi tt Trigger input on the serial c lock (SCLK).

High dynamic range, programmable output rates, and
flexible power supp ly options makes these ADCs ideal
solutions for weigh scale and process control
applications.

@0.1

VA+ C1 C2 VREF+ VREF- VD+

AIN1+

AIN1-

AIN2+

AIN2-

AIN3+

AIN3-

AIN4+

AIN4-

MUX

(CS5533/34

SHOWN)

PGIA
1,2,4,8,16

32,64

Preliminary Product Information

P.O. Box 17847, Austin, Texas 78760
[phone] FAX: [phone]
http://www.cirrus.com

ORDERING INFORM ATION

See page 48

CS

SDI
SDO

SCLK

LATCH

DIFFERENTIAL

TH

4

ORDER

MODULATOR

∆Σ

PROGRAMMABLE

SINC FIR FILTER

CLOCK

GENERATOR

OSC2OSC1A1A0/GUARDVA-

SERIAL

INTERFACE

CALIBRATION

SRAM/CONTROL

LOGIC

DGND

This document contains information for a new product.
Cirrus Logic reserves the right to modify this product withoutnotice.

CopyrightCirrus Logic, Inc. 2002

(All Rights Reserved)

MAR ‘02

DS289PP5

1

TABLE OF CONTENTS

1. CHARACTERISTICS AND SPECIFICATIONS ..........................................................5

ANALOG CHARACTERISTICS..........................................................................5

TYPICAL RMS NOISE (NV), C S5531/32/33/34-AS...........................................8

TYPICAL NOISE FREE RESOLUTION(BITS), CS5532/34-AS.........................8

TYPICAL RMS NOISE (NV), C S5532/34-BS.....................................................9

TYPICAL NOISE FREE RESOLUTION(BITS), CS5532/34-BS.........................9

5 V DIGITAL CHARACTERISTICS ..................................................................10

3 V DIGITAL CHARACTERISTICS ..................................................................10

DYNAMIC CHARACTERISTICS......................................................................11

ABSOLUTE MAXIMUM RATINGS...................................................................11

SWITCHING CHARACTERISTICS..................................................................12

2. GENERAL DESCRIPTION .......................................................................................14

2.1. Analog Input ....................................................................................................14

2.1.1. Analog Input Span .................................................................................... 15

2.1.2. Multiplexed Settling Limitations ............................................................15

2.1.3. Voltage Noise Density Performance .....................................................15

2.1.4. No Offset DAC ......................................................................................15

2.2. Overview o f ADC Register Structure and Operating Modes ............................16

2.2.1. System Initialization ..............................................................................17

2.2.2. Command Register Quick Reference ..................................................19

2.2.3. Command Register Descriptions ..........................................................20

2.2.4. Serial Port Interface ..............................................................................24

2.2.5. Reading/Writing On-Chip Registers ......................................................25

2.3. Configuration Register .....................................................................................25

2.3.1. Power Consumption .............................................................................25

2.3.2. System Reset Sequence ......................................................................25

2.3.3. Input Short ............................................................................................26

2.3.4. Guard Signal .........................................................................................26

2.3.5. Voltage Reference Select .....................................................................26

2.3.6. Output Latch Pins .................................................................................26

2.3.7. Offset and G ain Select ..........................................................................27

CS5531/32/33/34

Contacting Cirrus Logic Support

For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:

http://www.cirrus.com/corporate/contacts/sales.cfm

SPI is a registered trademark of International Business Machines Corporation.
Microwire is atrademark of National Semiconductor Corporation.

IMPORTANT NOTICE
"Preliminary" product information describes products that are inproduction, but for which full characterization data is not yetavailable. "Advance" product infor-

mation describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the infor­mation contained inthis document is accurateand reliable. However, theinformation is subject to changewithoutnotice and isprovided "AS IS" without warranty
of any kind (express or implied). Customers areadvised to obtain the latest versionof relevant information to verify, before placing orders, that information being
reliedon is current and complete. All products are sold subject to the termsand conditions of sale supplied at thetime of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this
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for general distribution, advertising or promotional purposes, or for creating any work for resale.

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obtained fromthecompetentauthorities of the Chinese Governmentifanyof the products or technologies describedin this material is subject to the PRC Foreign
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CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE
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Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trade­marks or service marks of their respective owners.

2 DS289PP5

CS5531/32/33/34

2.3.8. Filter Rate Select ..................................................................................27

2.3.9. Configuration Register Descriptions .....................................................28

2.4. Setting up the CSRs for a Measurement .........................................................29

2.4.1. Channel-Setup Register Descriptions .................................................30

2.5. Calibration .......................................................................................................32

2.5.1. Calibration Registers ............................................................................ 32

2.5.2. Gain Register ......................................................................................32

2.5.3. Offset Register ....................................................................................32

2.5.4. Performing Calibrations ........................................................................33

2.5.5. Self Calibration .....................................................................................33

2.5.6. System Calibration ...............................................................................34

2.5.7. Calibration T ips ....................................................................................34

2.5.8. Limitations in Cal ibration Range ...........................................................35

2.6. Performing Conversions .................................................................................. 35

2.6.1. Single Conversion Mode ......................................................................35

2.6.2. Continuous Conversion Mode ..............................................................36

2.6.3. Examples of Using CSRs to Perform Conversions and Calibrations ...37

2.7. Using Multiple ADCs Synchronously ............................................................... 38

2.8. Conversion Output Coding ..............................................................................38

2.8.1. Conversion Data O utput Descriptions ..................................................39

2.9. Digital Filter .....................................................................................................40

2.10. ClockGenerator .............................................................................................. 41

2.11. Power Supply Arrangements ...........................................................................41

2.12. Getting Started ................................................................................................45

2.13. PCBLayout .....................................................................................................45

3. PIN DESCRIPTIONS ............................................................................................... 46

Clock Generator ..............................................................................................46

Control Pins and Serial Data I/O .....................................................................46

Measurement and Reference Inputs ...............................................................47

Power Supply Connections .. ...........................................................................47

4. SPECIFICATION DEFINITIONS ...............................................................................48

5. ORDERING GUIDE ..................................................................................................48

6. PACKAGE DRAWINGS ...........................................................................................49

DS289PP5 3

LIST OF FIGURES

Figure 1 . SDI Write T iming (Not to Scale)...............................................................................13

Figure 2 . SDO R ead Timing (Not to Scale).............................................................................13

Figure 3 . Multiplexer Configuration .........................................................................................14

Figure 4. Input models for AIN+ and A I N- pins .......................................................................15

Figure 5 . Measured Voltage Noise Density.............................................................................15

Figure 6. CS5531/32/ 33/3 4 Register Diagram ........................................................................16

Figure 7 . Command and Data Word Timing............................................................................24

Figure 8 . Guard Signal Shielding Scheme ..............................................................................26

Figure 9 . Input Reference Model when VRS = 1.....................................................................27

Figure 1 0. Input Reference Model when VRS = 0...................................................................27

Figure 1 1. Self Calibration of Offset........................................................................................34

Figure 1 2. Self Calibration of Gain ..........................................................................................34

Figure 1 3. System Calibration of Offset ..................................................................................34

Figure 1 4. System Calibration of Gain ....................................................................................34

Figure 1 5. Synchronizing Multiple ADCs.................................................................................38

Figure 1 6. Digital Filter Response (Word Rate = 60 Sps).......................................................40

Figure 1 7. 120 Sps Filter Magnitude Plot to 120 Hz................................................................40

Figure 1 8. 120 Sps Filter Phase Plot to 120 Hz......................................................................40

Figure 1 9. Z-Transforms of Digital Filters................................................................................40

Figure 2 0. On-chip Oscillator Model........................................................................................41

Figure 2 1. CS5532 Configured with a Single +5 V S upply......................................................42

Figure 22. CS5532 Configured with ±2.5 V Ana log Supplies..................................................43

Figure 23. CS5532 Configured with ±3 V Analog Supplies.....................................................43

Figure 2 4. CS5532 Configured for Thermoc ouple Meas urement ...........................................44

Figure 2 5. Bridge with Series Resistors..................................................................................44

CS5531/32/33/34

LIST OF TABLES

Table 1. Conversion Timing for Single Mode..........................................................................36

Table 2 . Conversion Timi ng for Continuous M ode..................................................................37

Table 3. Command Byte Pointer.............................................................................................37

Table 4 . Output Coding for 16-bit CS5531 and CS5533.........................................................39

Table 5 . Output Coding for 24-bit CS5532 and CS5534.........................................................39

4 DS289PP5

CS5531/32/33/34

1. CHARACTERISTICS AND SPECIFICATIONS

ANALOG CHARACTERISTICS (VA+, VD+ = 5 V ±5%; VREF+ = 5 V; VA-, VREF-, DGND = 0 V;

MCLK = 4. 9152 MHz; OWR (Output W ord Rate) = 60 Sps; Bipolar Mode; Gain = 32)
(SeeNotes 1 and 2.)

CS5531-AS/CS5533-AS

Parameter

Accuracy

Linearity E rror - ±0.0015 ±0.003 %FS
No Missing Codes 16 - - Bits
Bipolar Offset - ±1±2LSB

Unipolar Offset - ±2 ±4LSB
Offset Drift (Notes 3 a nd 4) - 640/G + 5 - nV/°C

Bipolar Full Scale Error - ±8 ±31 ppm
Unipolar Full Scale Error - ±16 ±62 ppm
Full S ca le Drift (Note 4 ) - 2 - ppm/°C

CS5532-AS/CS5534-AS CS5532-BS/C S5 534-BS

Parameter

Accuracy

Linearity E rror - ±0.0015 ±0.003 - ±0.0007 ±0.0015 %FS
No Missing Codes 24 - - 24 - - Bits
Bipolar Offset - ±16 ±32 - ±16 ±32 LSB

Unipolar Offset - ±32 ±64 - ±32 ±64 LSB
Offset Drift (Notes 3 and 4) - 640/ G + 5 - - 640/G + 5 - nV/°C

Bipolar Full Scale Error - ±8 ±31 - ±8 ±31 ppm
Unipolar Full Scale Error - ±16 ±62 - ±16 ±62 ppm
Full S ca le Drift (Note 4 ) - TBD - - 2 - ppm/°C

UnitMin Typ Max

16
16

UnitMin Typ Max Min Typ Max

24
24

Notes: 1. Applies after system calibration at any temperature within -40 °C ~ +85 °C.

2. Specifications guaranteed by design,characterization, and/or t est.LSB is 16 bits fo r the CS5531/33 and
LSB is 24 bits for the CS5532/34.

3. This specification applies to the device only and does not include any effects by external parasitic
thermocouples. The PGIA con tributes 5 nV of offset drift, an d the modulator contributes 640/G nV of
offset drift, where G is t he am plifier gain setting.

4. Drift over spec ified tem perature range after calibration at power-up at 25 °C.

DS289PP5 5

CS5531/32/33/34

ANALOG CHARACTERISTICS (Continued) (See Notes 1 an d 2. )

Parameter Min Typ Max Unit

Analog Input

Common Mode + Signal on AIN+ or AIN-Bipolar/Unipolar Mode

Gain = 1
Gain = 2, 4, 8, 16, 32, 64 (Note 5)

CVF Current o n AIN+ or AIN- Gain = 1 (Note 6)

Gain = 2, 4, 8, 16, 32, 64

Input Current Noise Gain = 1

Gain = 2, 4, 8, 16, 32, 64
Input Leakage for Mux when Off (at 25 °C) - 10 - pA
Off-Channel M ux Isolation - 120 - dB
Open Circuit Det ec t Current 100 300 - nA
Common Mode Rejection dc, Gai n = 1

dc, Gai n = 64

50, 60 Hz
Input Capacitance - 60 - pF
Guard DriveOutput - 20 - µA

Voltage Reference Input

Range (VREF+) - (VREF-) 1 2.5 (VA+)-(VA -) V
CVF C urrent (Note 6) - 500 - nA
Common Mode Rejection dc

50, 60 Hz
Input Capacitance 11 - 2 2 pF

System Calibration Specifications

Full Scale Calibration Range Bipolar/Unipolar Mode 3 - 110 %FS
Offset Calibration Range Bipolar Mode -100 - 100 %FS
Offset Calibration Range Unipolar Mode -90 - 90 %FS

VA-

VA- + 0.7--

-

-

-

-

-

-

-

-

-

500
500

200

130
120

120
120

1

90

VA+

VA+ - 1.7

-

-

-

-

-

-

-

-

-

V
V

nA
pA

pA/√Hz
pA/√Hz

dB
dB
dB

dB
dB

Notes: 5. The vol tage on the analog inputs is amplified by the PGIA, and becom es V

the differential outputs of the amplifier. In addition to the input comm on mode + signal requirements for
the an alog input pins, the differential outputs of the amplifier must remain between (VA- + 0.1 V) and
(VA+ - 0.1 V) to avoid saturation of the output stage.

6. See the section of the dat a sheet whic h discusses input mod els.

6 DS289PP5

± Gain*(AIN+ - AIN-)/2 at

CM

ANALOG CHARACTERISTICS (Continued) (See Notes 1 an d 2. )

CS5531/32/33/34-AS CS5532/34-BS

Parameter

Power Supplies

DC Power Supply Currents (Normal Mode) I

Power Consumption Normal Mode (Notes 7 and 8)

Standby
Sleep

Power Supply Rejection (Note 9)

dc Positive Supplies
dc Negative Supply

7. All outputs unloaded. All input CMOS levels.

8. Power is specified when the instrumen tation ampl ifier (Gain ≥ 2) is on. Analog supplycurrent is reduced
by ap prox imately 1/2 when the instrumentation amplifier is off ( Gain = 1).

9. Tested with 100 mV change on VA+ or VA-.

A+,IA-

I

D+

Min Typ

-

-

-

-

-

-

-

0.5
35

500

115
115

Max

6

45

3

8
1

-

-

-

-

CS5531/32/33/34

13

70

4

Max

15

1

80

-

-

-

-

Unit

mA
mA

mW
mW

µW

dB
dB

Min Typ

-

0.5

-

-

-

-

500

-

115

-

115

DS289PP5 7

CS5531/32/33/34

TYPICAL RMS NOISE (nV), CS5531/32/33/34-AS (See notes 10, 11 and 12 )

Output Word

Rate (Sps)

7.5 1.94 171719264279155
15 3.88 24 25 27 36 59 111 218
30 7.75 34 35 39 51 84 157 308
60 15.5 48 49 54 72 118 222 436

120 31 68 70 77 102 167 314 616
240 62 115 160 276 527 1040 2070 4150
480 122 163 230 392 748 1480 2950 5890

960 230 229 321 554 1060 2090 4170 8340
1,920 390 344 523 946 1840 3650 7290 14600
3,840 780 1390 2710 5390 10800 21500 43000 86100

Notes: 10. Wideband noise aliased into the baseband. Referred to the input. Typical values shown for 25 °C.

11. For Peak-to-Peak Noise multiply by 6.6 for all ranges and output rates.

12. Word rates and -3dB points w ith FRS = 0. When FRS = 1, word rates and -3dB points scale by 5/6.

-3 dB Filter

Frequency (Hz)

x64 x32 x16 x8 x4 x2 x1

Instrumentation Am pl ifier Gain

TYPICAL NOISE FREE RESOLUTION(BITS), CS5532/34-AS (See Notes 13 and 14)

Output Word

Rate (Sps)

7.5 1.94 19202122222222
15 3.88 19 20 21 21 21 22 22
30 7.75 18 19 20 21 21 21 21
60 15.5 18192020202121

120 31 17 18 19 20 20 20 20
240 62 16 17 17 17 17 17 17
480 122 16 17 17 17 17 17 17

960 230 15 16 16 16 16 16 16
1,920 390 15 15 15 15 15 15 15
3,840 780 13 13 13 13 13 13 13

-3 dB Filter

Frequency (Hz)

x64 x32 x16 x8 x4 x2 x1

Instrumentation Am pl ifier Gain

13. Noise Free Resolution listed is for Bipolar operation, and is calculated as LOG((Input S pan)/(6.6xRMS
Noise))/LOG(2) rounded to the nearest bit. For Unipolar operation, the input span is 1/2 as large,so one
bit is lost. The input span is calculated in the analog input span section of the data s heet. The Noise
Free Resolution table is computed with a value of 1.0 in the gain register. Values other than 1.0 will
scale the noise , and change the Noise Free Resolution accordingly.

14. “Noise Free Resolution” is not the same as “Effective Resolution”. Effective Resolution is based on the
RMS noise value, while Noise Free Resolution is based on a peak -to-pe ak noise value sp ec ified as 6.6
times the RMS noise value. Effective Resolution is calculated as LOG((Input Span)/(RMS
Noise))/LOG(2).

Specifications are s ubject to change without notice.

8 DS289PP5

CS5531/32/33/34

TYPICAL RMS NOISE (nV), CS5532/34-BS (See notes 15, 16, 17 and 18)

Output Word

Rate (Sps)

7.5 1.94 8.59 1015265099
15 3.88 12 13 15 21 37 70 139
30 7.75 17 18 21 30 52 99 196
60 15.5 24 25 29 42 73 140 277

120 31 34 36 42 59 103 198 392
240 62 80 136 260 514 1020 2050 4090
480 122 113 194 369 730 1450 2900 5810

960 230 159 274 523 1030 2060 4110 8230
1,920 390 260 470 912 1810 3620 7230 14500
3,840 780 1360 2690 5380 10800 21500 43000 86000

Notes: 15. The -B devices provide the best noise specifications.

16. Wideband noise aliased into the baseband. Referred to the input. Typical values shown for 25 °C.

17. For Peak-to-Peak Noise multiply by 6.6 for all ranges and output rates.

18. Word rates and -3dB points w ith FRS = 0. When FRS = 1, word rates and -3dB points scale by 5/6.

-3 dB Filter

Frequency (Hz)

x64 x32 x16 x8 x4 x2 x1

Instrumentation Am pl ifier Gain

TYPICAL NOISE FREE RESOLUTION(BITS), CS5532/34-BS (See Notes 19 and 20)

Output Word

Rate (Sps)

7.5 1.94 20212223232323
15 3.88 20 21 22 22 22 22 22
30 7.75 19 20 21 22 22 22 22
60 15.5 19202121212121

120 31 18 19 20 21 21 21 21
240 62 17 17 18 18 18 18 18
480 122 17 17 17 17 17 17 17

960 230 16 16 17 17 17 17 17
1,920 390 16 16 16 16 16 16 16
3,840 780 13 13 13 13 13 13 13

-3 dB Filter

Frequency (Hz)

x64 x32 x16 x8 x4 x2 x1

Instrumentation Am pl ifier Gain

19. Noise Free Resolution listed is for Bipolar operation, and is calculated as LOG((Input S pan)/(6.6xRMS
Noise))/LOG(2) rounded to the nearest bit. For Unipolar operation, the input span is 1/2 as large,so one
bit is lost. The input span is calculated in the analog input span section of the data s heet. The Noise
Free Resolution table is computed witha value of 1.0 in the gain register. Values otherthan 1.0 will s c ale
the no ise, and change the Noise Free Resolution accordingly.

20. “Noise Free Resolution” is not the same as “Effective Resolution”. Effective Resolution is based on the
RMS noise value, while Noise Free Resolution is based on a peak -to-pe ak noise value sp ec ified as 6.6
times the RMS noise value. Effective Resolution is calculated as LOG((Input Span)/(RMS
Noise))/LOG(2).

Specifications are s ubject to change without notice.

DS289PP5 9

CS5531/32/33/34

5 V DIGITAL CHARACTERISTICS (VA+, VD+ = 5 V ±5%; VA-, DGND = 0 V;

See Notes 2 and 21.)

Parameter Symbol Min Typ Max Unit

High-Level Input Voltage All Pins Excep t SCLK

SCLK

Low-Level I nput Voltage All Pins Except SCLK

SCLK

High-Level Output Voltage A0 and A1, I

SDO, I

Low-Level Output Voltage A0 and A1, I

SDO, I

=-1.0mA

out

=-5.0mA

out

=1.0mA

out

=5.0mA

out

V

Input Leakage Current I
SDO 3-State Leakage Current I
Digital Output Pin Capacitance C

V

IH

V

IL

OH

V

OL

in

OZ

out

0.6 VD+

(VD+) - 0.45--

0.0

-0.8

0.0

(VA+) - 1.0

--V

(VD+) - 1.0

--(VA-)+0.4

- ±1 ±10 µA

--±10µA

-9-pF

VD+
VD+

0.6

0.4

V

V

V

3 V DIGITAL CHARACTERISTICS (T

= 25 °C; VA+ = 5V ±5%; V D+ = 3.0V±10%; VA-, DGND =

A

0V; S ee Notes 2 and 21.)

Parameter Symbol Min Typ Max Unit

High-Level Input Voltage All Pins Excep t SCLK

SCLK

Low-Level I nput Voltage All Pins Except SCLK

SCLK

High-Level Output Voltage A0 and A1, I

SDO, I

Low-Level Output Voltage A0 and A1, I

SDO, I

=-1.0mA

out

=-5.0mA

out

=1.0mA

out

=5.0mA

out

Input Leakage Current I
SDO 3-State Leakage Current I
Digital Output Pin Capacitance C

21. All measurements performed under static conditions.

V

IH

V

IL

V

OH

0.6 VD+

(VD+) - 0.45

0.0

0.0

(VA+) - 1.0

-VD+

V

VD+

-0.8

V

0.6

--V

(VD+) - 1.0

V

OL

--(VA-)+0.4

V

0.4

in

OZ

out

-±1±10µA

--±10µA

-9-pF

10 DS289PP5

DYNAMIC CHARACTERISTICS

Parameter Symbol Ratio Unit

Modulator Sampling Rate f
Filter Set tling Time to 1/2 LSB (Full Scale Step Input)

Single Conv ers ion mode (Notes 22, 23, and 24)
Continuous Conversion mode, OWR < 3200 Sps
Continuous Conversion mode, OWR ≥ 3200 Sps

CS5531/32/33/34

s

t

s

t

s

t

s

MCLK/16 Sps

1/OWR

5/OWR

sinc5

SC

+3/OWR

5/OWR

s
s
s

22. The ADCs use a Sinc5filter for the 3200 Sps and 3840 Sps output word rate (OWR) and a Sinc5filter
followed by a Sinc
(FRS = 0) word rate as soc iated with the Sinc

3

filter for the other OWRs. OWR

5

filter.

refers to the 3200 Sps (FRS = 1) or 3840 Sps

sinc5

23. The single convers ion mode only outputs fully settled conv ersions . See Table 1 for more details about
single conv ersion mode timing. OW R

is used here to designate the different conversion time

SC

associated wi th single conversions.

24. The continuous conversion mode output s every conversion. This means that the filter’s set tling time
with a full scale step input in th e continuous conversion mode is dictated by the OWR.

ABSOLUTE MAXIMUM RATINGS (DG ND = 0 V; See Note 25.)

Parameter Symbol Min Typ Max Unit

DC P ower Supp lies (Notes 26 and 27)

Positive Di gital

Positive Analog

Negative Analog

Input Current, Any Pin Except Supplies (Notes 28 an d 29) I
Output Current I
Power Dissipation (Note 30) PDN - - 500 mW

Analog I nput Voltage VREF pins

AIN Pins

Digital Input Voltage V
Ambient Operating Temperature T
Storage Temperature T

VD+

VA+

VA-

IN

OUT

V

INR

V

INA
IND

A

stg

-0.3

-0.3

+0.3

-

-

-

+6.0
+6.0

-3.75

V
V
V

--±10mA

--±25mA

(VA-) -0.3
(VA-) -0.3

--(VA+)+ 0.3
(VA+)+ 0.3VV

-0.3 - (VD+) + 0.3 V

-40 - 85 °C

-65 - 150 °C

Notes: 25. All voltages with respect to ground.

26. VA+ and VA- must satisfy {(VA+) - (VA-)} ≤ +6.6 V.

27. VD+ and VA- must s at isf y {(VD+) - (VA-)} ≤ +7.5 V.

28. Applies to all pins including continuous overvoltage conditions at the analog input (AIN) pins.

29. Transient current of up to 100 mA will not ca us e SCR latch-up. Maximum input current for a power
supply pin is ±50 mA.

30. Total power dissipation, including all input currents and out put currents .

WARNING: Operation at or beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes.

DS289PP5 11

CS5531/32/33/34

SWITCHING CHARACTERISTI CS (VA+ = 2.5 V or 5 V ±5%; VA- = -2.5V±5% or 0 V ; VD+ = 3.0 V

rise

fall

ost

t

1

t

2

3
4
5
6

7
8
9

=50pF;

L

1 4.9152 5 MHz

-

-

-

-

-

-

-

-

50

-

-

50

-20-ms

250
250

-

-

50 - - ns

50 - - ns
100 - - ns
100 - - ns

- - 150 ns

- - 150 ns

- - 150 ns

1.0

100

-

1.0

100

-

-

-

µs
µs
ns

µs
µs
ns

ns
ns

±10% or 5 V ±5%;DGND = 0 V; Levels: Logic 0 = 0 V, Logic 1 = VD+; C
See Figures 1 and 2.)

Parameter Symbol Min Typ Max Unit

Master Clock Frequency (Note 31)

MCLK

External Clo ck or Crystal Oscillator
Master Clock Duty Cy c le 40 - 60 %
Rise Times (Note32)

t

Any Digi tal Input Except SCLK

SCLK

Any Digital Output

Fall Times (Note32)

t

Any Digi tal Input Except SCLK

SCLK

Any Digital Output

Start-up

Oscillator Start-up Time XTAL = 4.9152 MHz (Note 33) t

Serial Port Timing

Serial Clock Frequenc y SCLK 0 - 2 MHz
Serial Clock Pulse Width High

Pulse Width Low

SDI Write Timing

CS

Enable to Valid Latch Clock t
Data Set-up Time prior to SCLK rising t
Data Hold Time After SCLK Rising t
SCLK Falling Prior to CS

Disable t

SDO Read Timing

CS

to Data Valid t
SCLK Falling to New Data Bit t

Rising to SDO Hi-Z t

CS

Notes: 31. Device param ete rs are specified with a 4.9152 MHz clock.

32. Specified using 10% and 90% points on waveform of interest. Output loaded with 50 pF.

33. Oscillator start-up time varies with crystal parameters. This s pec if icat ion does not apply when using an
external cloc k source.

12 DS289PP5

CS

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

SDI

SCLK

t3

MSB

MSB-1

t2

Figure 1. SDI Wr ite Timing (Not to Sc ale)

CS5531/32/33/34

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

LSB

t6t4 t5 t1

0

0

0

CS

SDO

SCLK

t7

MSB MSB-1

t8

t1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

t2

0

0

0

0

0

0

0

0

0

0

0

LSB

t9

Figure 2. SDO Read Timing (Not to Scale)

DS289PP5 13

CS5531/32/33/34

2. GENERAL DESCRIPTION

The CS5531/32/33/34 are highly integrated ∆ΣAn­alog-to-Digital Converters (ADCs) which use
charge-balance techniques to achieve 16-bit
(CS5531/33) and 24-bit (CS5532/34) performance.
The ADCs are optimized for measuring low-level
unipolar or bipolar signals in weigh scale, process
control, scientific, and medical applications.

To accommodate these applications, the ADCs
come as either two-channel (CS5531/32) or four­channel (CS5533/34) devices and include a very
low noise chopper-stabilized programmable gain
instrumentation amplifier (PGIA, 6 nV/√Hz
Hz) with selectable gains of 1×, 2×, 4×, 8×, 16×,
32×, and 64×. These ADCs also include a fourth or­der ∆Σ modulator followed by a digital filter
provides twenty selectable output word rates of 6.25,

7.5, 12.5, 15, 25, 30, 50, 60, 100, 120, 200, 240, 400,
480, 800, 960, 1600, 1920, 3200, and 3840 Samples
per second (MCLK = 4.9152 MHz).

To ease communication between the ADCs and a
micro-controller, the converters include a simple
three-wire serial interface which is SPI and Mi-

@0.1

which

crowire compatible with a Schmitt Trigger input on
the s erial clock (SCLK).

2.1. Analog Input

Figure 3 illustrates a block diagram of the
CS5531/32/33/34. The front end consistsof a multi­plexer, a unity gain coarse/fine charge input buffer,
and a programmable gain chopper-stabilized instru­mentation amplifier. The unity gain buffer is activat­ed any time conversions are performed with a gain
of one and the instrumentation amplifier is activated
any time conversions are performed with gain set­tings greater than one.

The unity gain buffer is designed to accommodate
rail to rail input signals. The common-mode plus
signal range for the unity gain buffer amplifier is
VA- to VA+. Typical CVF (sampling) current for
the unity gain buffer amplifier is about 500 nA
(MCLK = 4.9152 MHz, see Figure 4).

The instrumentation amplifier is chopper-stabi­lized and operates with a chop clock frequency of
MCLK/128. The CVF (sampling) current into the
instrumentation amplifier is typically 500 pA over

VREF+

VREF-

AIN2+

AIN2-

AIN1+

AIN1-

AIN4+

AIN4-

AIN1+

AIN1-

14 DS289PP5

CS5531/32

CS5533/34

*
*
*

IN+

M
U

IN-

X

IN+

IN-

IN+

M
U
X

IN-

GAINis the gain setting of the PGIA (i.e. 2, 4, 8, 16, 32, 64)

X1

1000

Ω

XGAIN

X1

Figure 3. M ultiplexer Configuration

22 nF

1000

Ω

C1 PIN
C2 PIN

X1

Differential

th

4 Order

∆Σ

Modulator

X1

Sinc

Digital

Filter

5

Programmable

3

Sinc

Digital Filter

Serial

Port

CS5531/32/33/34

-40°C to +85°C (MCLK=4.9152 MHz). The com­mon-mode plus signal range of the instrumentation
amplifier is (VA-) + 0.7 V to (VA+) - 1.7 V.

Figure 4 illustrates the input models for the ampli­fiers. The dynamic input current for each of the
pins can be determined from the models shown.

Gain=2,4,8,16,32,64

AIN

V≤1mV

os

i=fV C

n

os

AIN

V≤20 mV

os

i=fV C

osn

Figure 4. Input models for AIN+ and AIN- pins

MCLK

f=

128

Gain= 1

MCLK

f=

16

=12.5 pF

C

φ

Fine

1

φ

Coarse

1

C=80pF

After reset, the unity gain buffer is engaged. With a

2.5V reference this would make the full scale input
range default to 2.5 V. By activating the instrumen­tation amplifier (i.e. a gain setting other than 1) and
using a gain setting of 32, the full scale input range
can quickly be set to 2.5/32 or about 78 mV. Note
that these input ranges assume the calibration regis­ters are set to their default values (i.e. Gain = 1.0 and
Offset = 0.0).

2.1.2. Multiplexed Settling Limitations

The settling performance of the CS5531/32/33/34
in multiplexed applications is affected by the sin­gle-pole low-pass filter which follows the instru­mentation amplifier (see Figure3). To achieve data
sheet settling and linearity specifications, it is rec­ommended that a 22 nF C0G capacitorbe used. Ca­pacitors as low as 10 nF or X7R type capacitorscan
also be used with some minor increase in distortion
for AC signals.

2.1.3. Voltage Noise Density Performance

Figure5 illustrates the measuredvoltage noise den­sity versus frequency from 0.01 Hz to 10 Hz of a
CS5532-BS. The device was powered with ±2.5 V
supplies, using 120 Sps OWR, t he 64x gain range,
bipolarmode, and withthe inputshort bit enabled.

Note: T he C=2.5pF and C = 16pFcapacitors are for

input c urrent modeling only. For physical
input capacitance s ee ‘Input Capa citan ce ’
specification under Analog Characteristics.

2.1.1. Analog Input Span

The full scale input signal that the converter can dig­itize is a function of the gain setting and the refer­ence voltage connected between the VREF+ and

100

Hz

√

√

√

√

10

nV/

1

0.01 0.1 1 10

Freque ncy (Hz)

Gain = 64

VREF- pins. The full scale input span of the convert­er is ((VREF+) - (VREF-))/(GxA), where G is the

Figure 5. Measured Voltage Noise Density

gain of the amplifier and A is 2 for VRS = 0, or A is
1 for VRS = 1. VRS is the Voltage Reference Select
bit, and must be set according to the differential volt­age applied to the VREF+ and VREF- pins on the
part. See section 2.3.5 for more details.

DS289PP5 15

2.1.4. No Offset DAC

An offset DAC was not included in the CS553X
family because the high dynamic range of the con­verter eliminates the need for one. The offset regis-

CS5531/32/33/34

ter can be manipulated by the user to mimic the
function of a DAC if desired.

2.2. Overview of ADC Register Structure and Operating Modes

The CS5531/32/33/34 ADCs have an on-chip con­troller, which includes a number of user-accessible
registers. The registers are used to hold offset and
gain calibration results, configure the chip's operat­ing modes, hold conversion instructions, and to
store conversion data words. Figure 6 depicts a
block diagram of the on-chip controller’s internal
registers.

Each of the converters has 32-bit registers to func­tion as offset and gain calibration registers for each
channel. The converters with two channels have
two offset and two gain calibration registers, the
converters with four channels have four offset and
four gain calibration registers. These registers hold
calibration results. The contents of these registers
can be read or written by the user. This allows cal-

ibration data to be off-loaded into an external EE­PROM. The user can also manipulate the contents
of these registers to modify the offset or the gain
slope of the converter.

The converters include a 32-bit configuration reg­ister which is used for setting options such as the
power down modes, resetting the converter, short­ing the analog inputs, and enabling diagnostic test
bits like the guard signal.

A group of registers, called Channel Setup Regis­ters, are used to hold pre-loaded conversion in­structions. Each channel setup register is 32 bits
long, and holds two 16-bit conversion instructions
referred to as Setups. Upon power up, these regis­ters can be initialized by the system microcontrol­ler with conversion instructions. The user can then
instruct the converter to perform single or multiple
conversions or calibrations with the converter in
the mode defined by one of these Setups.

Offset Registers(4 x 32) Gain Registers (4 x 32)

Offset 1 (1 x 32 )

Offset 2 ( 1 x 32 )

Offset 3 ( 1 x 32 )

Offset 4 ( 1 x 32 )

Configur ation Reg iste r (1 x 32)

Pow er Sav e Se lect
Re set System
InputShort
Guard Signal
Voltag e Referen c e Se lect
Output Latch
Output Latch S e lect
Offset/Gain Select
Filter Rate Select

Gain1(1x32)

Gain2(1x32)

Gain3(1x32)

Gain4(1x32)

Figure 6. CS5531/32/33/34Register Diagram

Channel Set up

Registers (4 x 32)

Setup 1
(1 x 1 6)

Setup 3
(1 x 1 6)

Setup 5
(1 x 1 6)

Setup 7
(1 x 1 6)

Channel Select
Gain
Word Rate
Unipolar/B ipolar
Output Latch
DelayTime
Open Circuit Detect
Offset/Gain Pointer

Setup 2
(1 x 16)

Setup 4
(1 x 16)

Setup 6
(1 x 16)

Setup 8
(1 x 16)

Write Only

Command

Register(1 × 8)

Conv ersion Data

Register (1 x 32)

Data (1 x 32 )

Read Only

Serial

Interface

CS
SDI
SDO
SCLK

16 DS289PP5