CIRRUS LOGIC CS5531, CS5532, CS5533, CS5534 Service Manual

CS5531/32/33/34

16-bit and 24-bit ADCs with Ultra-low-noise PGIA

Features

z Chopper-stabilized PGIA (Programmable

Gain Instrumentation Amplifier, 1x to 64x)

6 nV/√Hz @ 0.1 Hz (No 1/f noise) at 64x
500 pA Input Current with Gains >1

Delta-sigma Analog-to-digital Converter

z

Linearity Error: 0.0007% FS
Noise Free Resolution: Up to 23 bits

Two- or Four-channel Differential MUX

z

z Scalable Input Span via Calibration

±5 mV to differential ±2.5V

Scalable V

z

z Simple Three-wire Serial Interface

SPI™ and Microwire™ Compatible
Schmitt Trigger on Serial Clock (SCLK)

R/W Calibration Registers Per Channel

z

z Selectable Word Rates: 6.25 to 3,840 Sps

z Selectable 50 or 60 Hz Rejection

z Power Supply Configurations

VA+ = +5 V; VA- = 0 V; VD+ = +3 V to +5 V
VA+ = +2.5 V; VA- = -2.5 V; VD+ = +3 V to +5 V
VA+ = +3 V; VA- = -3 V; VD+ = +3 V

Input: Up to Analog Supply

REF

General Description

The CS5531/32/33/34 are highly integrated ∆Σ Analog­to-Digital Converters (ADCs) which use charge-balance
techniques to achieve 16-bit (CS5531/33) and 24-bit
(CS5532/34) performance. The ADCs are optimized for
measuring low-level unipolar or bipolar signals in weigh
scale, process control, scientific, and medical
applications.

To accommodate these applications, the ADCs
either two-channel (CS5531/32) or four-channel
(CS5533/34) devices and include a very low noise chop­per-stabilized instrumentation amplifier (6 nV/√Hz
Hz) with selectable gains of 1×, 2×, 4×, 8×, 16×, 32×, and
64×. These ADCs also include a fourth order ∆Σ modu­lator followed by a digital filter

which provides twenty
selectable output word rates of 6.25, 7.5, 12.5, 15, 25, 30,
50, 60, 100, 120, 200, 240, 400, 480, 800, 960, 1600,
1920, 3200, and 3840 Sps (MCLK = 4.9152 MHz).

To ease communication between the ADCs and a micro­controller, the converters include a simple three-wire se­rial interface which is SPI and Microwire compatible with
a Schmitt Trigger input on the serial clock (SCLK).

High dynamic range, programmable output rates, and
flexible power supply options makes these ADCs ideal
solutions for weigh scale and process control
applications.

ORDERING INFORMATION

See page 48

come as

@ 0.1

VA+ C1 C2 VREF+ VREF- VD+

AIN1+

AIN1-

AIN2+

AIN2-

AIN3+

AIN3-

AIN4+

AIN4-

MUX

(CS5533/34

SHOWN)

PGIA
1,2,4,8,16
32,64

Preliminary Product Information

http://www.cirrus.com

CS

SDI

SDO

SCLK

LATCH

DIFFERENTIAL

TH

ORDER

4

MODULATOR

∆Σ

PROGRAMMABLE

SINC FIR FILTER

CLOCK

GENERATOR

OSC2OSC1A1A0/GUARDVA-

SERIAL

INTERFACE

CALIBRATION

SRAM/CONTROL

LOGIC

DGND

This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.

Copyright © Cirrus Logic, Inc. 2005

(All Rights Reserved)

JUL ‘05

DS289F1

1

TABLE OF CONTENTS

1. CHARACTERISTICS AND SPECIFICATIONS ..........................................................4

ANALOG CHARACTERISTICS..........................................................................4

TYPICAL RMS NOISE (NV), CS5531/32/33/34-AS ...........................................7

TYPICAL NOISE FREE RESOLUTION(BITS), CS5532/34-AS .........................7

TYPICAL RMS NOISE (NV), CS5532/34-BS .....................................................8

TYPICAL NOISE FREE RESOLUTION(BITS), CS5532/34-BS .........................8

5 V DIGITAL CHARACTERISTICS ....................................................................9

3 V DIGITAL CHARACTERISTICS ....................................................................9

DYNAMIC CHARACTERISTICS ......................................................................10

ABSOLUTE MAXIMUM RATINGS ...................................................................10

SWITCHING CHARACTERISTICS ..................................................................11

2. GENERAL DESCRIPTION .......................................................................................13

2.1. Analog Input ....................................................................................................13

2.1.1. Analog Input Span .................................................................................... 14

2.1.2. Multiplexed Settling Limitations ............................................................14

2.1.3. Voltage Noise Density Performance .....................................................14

2.1.4. No Offset DAC ......................................................................................14

2.2. Overview of ADC Register Structure and Operating Modes ............................15

2.2.1. System Initialization ..............................................................................16

2.2.2. Command Register Quick Reference ..................................................18

2.2.3. Command Register Descriptions ..........................................................19

2.2.4. Serial Port Interface ..............................................................................23

2.2.5. Reading/Writing On-Chip Registers ......................................................24

2.3. Configuration Register .....................................................................................24

2.3.1. Power Consumption .............................................................................24

2.3.2. System Reset Sequence ......................................................................24

2.3.3. Input Short ............................................................................................25

2.3.4. Guard Signal .........................................................................................25

2.3.5. Voltage Reference Select .....................................................................25

2.3.6. Output Latch Pins .................................................................................25

2.3.7. Offset and Gain Select ..........................................................................26

2.3.8. Filter Rate Select ..................................................................................26

2.3.9. Configuration Register Descriptions .....................................................27

2.4. Setting up the CSRs for a Measurement .........................................................28

2.4.1. Channel-Setup Register Descriptions ..................................................29

2.5. Calibration ........................................................................................................31

2.5.1. Calibration Registers ............................................................................31

2.5.2. Gain Register .......................................................................................31

2.5.3. Offset Register .....................................................................................31

2.5.4. Performing Calibrations ........................................................................32

2.5.5. Self Calibration .....................................................................................32

2.5.6. System Calibration ................................................................................33

2.5.7. Calibration Tips .....................................................................................33

2.5.8. Limitations in Calibration Range ...........................................................34

2.6. Performing Conversions ..................................................................................34

2.6.1. Single Conversion Mode .......................................................................34

2.6.2. Continuous Conversion Mode ..............................................................35

2.6.3. Examples of Using CSRs to Perform Conversions and Calibrations ....36

2.7. Using Multiple ADCs Synchronously ...............................................................37

2.8. Conversion Output Coding ..............................................................................37

2.8.1. Conversion Data Output Descriptions ..................................................38

2.9. Digital Filter ......................................................................................................39

2.10. Clock Generator ...............................................................................................40

2.11. Power Supply Arrangements ...........................................................................40

CS5531/32/33/34

2 DS289F1

2.12. Getting Started ................................................................................................ 44

2.13. PCB Layout ..................................................................................................... 44

3. PIN DESCRIPTIONS ............................................................................................... 45

Clock Generator .............................................................................................. 45

Control Pins and Serial Data I/O ..................................................................... 45

Measurement and Reference Inputs ............................................................... 46

Power Supply Connections ............................................................................. 46

4. SPECIFICATION DEFINITIONS ............................................................................... 47

5. ORDERING GUIDE .................................................................................................. 48

6. PACKAGE DRAWINGS ........................................................................................... 49

LIST OF FIGURES

Figure 1. SDI Write Timing (Not to Scale)............................................................................... 12

Figure 2. SDO Read Timing (Not to Scale)............................................................................. 12

Figure 3. Multiplexer Configuration ......................................................................................... 13

Figure 4. Input models for AIN+ and AIN- pins ....................................................................... 14

Figure 5. Measured Voltage Noise Density............................................................................. 14

Figure 6. CS5531/32/33/34 Register Diagram ........................................................................ 15

Figure 7. Command and Data Word Timing ........................................................................... 23

Figure 8. Guard Signal Shielding Scheme .............................................................................. 25

Figure 9. Input Reference Model when VRS = 1 .................................................................... 26

Figure 10. Input Reference Model when VRS = 0 .................................................................. 26

Figure 11. Self Calibration of Offset ........................................................................................ 33

Figure 12. Self Calibration of Gain .......................................................................................... 33

Figure 13. System Calibration of Offset .................................................................................. 33

Figure 14. System Calibration of Gain .................................................................................... 33

Figure 15. Synchronizing Multiple ADCs................................................................................. 37

Figure 16. Digital Filter Response (Word Rate = 60 Sps) ....................................................... 39

Figure 17. 120 Sps Filter Magnitude Plot to 120 Hz ............................................................... 39

Figure 18. 120 Sps Filter Phase Plot to 120 Hz ......................................................................39

Figure 19. Z-Transforms of Digital Filters................................................................................ 39

Figure 20. On-chip Oscillator Model........................................................................................ 40

Figure 21. CS5532 Configured with a Single +5 V Supply ..................................................... 41

Figure 22. CS5532 Configured with ±2.5 V Analog Supplies..................................................42

Figure 23. CS5532 Configured with ±3 V Analog Supplies..................................................... 42

Figure 24. CS5532 Configured for Thermocouple Measurement ........................................... 43

Figure 25. Bridge with Series Resistors .................................................................................. 43

CS5531/32/33/34

LIST OF TABLES

Table 1. Conversion Timing for Single Mode .......................................................................... 35

Table 2. Conversion Timing for Continuous Mode..................................................................36

Table 3. Command Byte Pointer ............................................................................................. 36

Table 4. Output Coding for 16-bit CS5531 and CS5533......................................................... 37

Table 5. Output Coding for 24-bit CS5532 and CS5534......................................................... 38

DS289F1 3

CS5531/32/33/34

1. CHARACTERISTICS AND SPECIFICATIONS

ANALOG CHARACTERISTICS (

VA+, VD+ = 5 V ±5%; VREF+ = 5 V; VA-, VREF-, DGND = 0 V; MCLK = 4.9152 MHz; OWR (Output Word Rate) =
60 Sps; Bipolar Mode; Gain = 32)
(See Notes 1 and 2.)

CS5531-AS/CS5533-AS

Parameter

Accuracy

Linearity Error - ±0.0015 ±0.003 %FS
No Missing Codes 16 - - Bits
Bipolar Offset - ±1±2LSB

Unipolar Offset - ±2 ±4LSB

Offset Drift (Notes 3 and 4) - 640/G + 5 - nV/°C
Bipolar Full Scale Error - ±8 ±31 ppm
Unipolar Full Scale Error - ±16 ±62 ppm
Full Scale Drift (Note 4) - 2 - ppm/°C

UnitMin Typ Max

16

16

CS5532-AS/CS5534-AS CS5532-BS/CS5534-BS

Parameter

Accuracy

Linearity Error - ±0.0015 ±0.003 - ±0.0007 ±0.0015 %FS
No Missing Codes 24 - - 24 - - Bits
Bipolar Offset - ±16 ±32 - ±16 ±32 LSB

Unipolar Offset - ±32 ±64 - ±32 ±64 LSB

Offset Drift (Notes 3 and 4) - 640/G + 5 - - 640/G + 5 - nV/°C
Bipolar Full Scale Error - ±8 ±31 - ±8 ±31 ppm
Unipolar Full Scale Error - ±16 ±62 - ±16 ±62 ppm
Full Scale Drift (Note 4) - 2 - - 2 - ppm/°C

Notes: 1. Applies after system calibration at any temperature within -40 °C ~ +85 °C.

2. Specifications guaranteed by design, characterization, and/or test. LSB is 16 bits for the CS5531/33 and
LSB is 24 bits for the CS5532/34.

3. This specification applies to the device only and does not include any effects by external parasitic
thermocouples. The PGIA contributes 5 nV of offset drift, and the modulator contributes 640/G nV of
offset drift, where G is the amplifier gain setting.

4. Drift over specified temperature range after calibration at power-up at 25 °C.

UnitMin Typ Max Min Typ Max

24

24

4 DS289F1

CS5531/32/33/34

ANALOG CHARACTERISTICS (Continued)

(See Notes 1 and 2.)

Parameter Min Typ Max Unit

Analog Input

Common Mode + Signal on AIN+ or AIN-Bipolar/Unipolar Mode

Gain = 1

Gain = 2, 4, 8, 16, 32, 64 (Note 5)

CVF Current on AIN+ or AIN- Gain = 1 (Note 6, 7)

Gain = 2, 4, 8, 16, 32, 64

Input Current Noise Gain = 1

Gain = 2, 4, 8, 16, 32, 64
Input Leakage for Mux when Off (at 25 °C) - 10 - pA
Off-Channel Mux Isolation - 120 - dB
Open Circuit Detect Current 100 300 - nA
Common Mode Rejection dc, Gain = 1

dc, Gain = 64

50, 60 Hz
Input Capacitance - 60 - pF
Guard Drive Output - 20 - µA

Voltage Reference Input

Range (VREF+) - (VREF-) 1 2.5 (VA+)-(VA-) V
CVF Current (Note 6, 7) - 50 - nA
Common Mode Rejection dc

50, 60 Hz
Input Capacitance 11 - 22 pF

System Calibration Specifications

Full Scale Calibration Range Bipolar/Unipolar Mode 3 - 110 %FS
Offset Calibration Range Bipolar Mode -100 - 100 %FS
Offset Calibration Range Unipolar Mode -90 - 90 %FS

VA-

VA- + 0. 7--

-

-

-

-

-

-

-

-

-

1200

200

130
120

120
120

50

1

90

VA+

VA+ - 1 . 7

-

-

-

-

-

-

-

-

-

V
V

nA
pA

pA/√Hz
pA/√Hz

dB
dB
dB

dB
dB

Notes: 5. The voltage on the analog inputs is amplified by the PGIA, and becomes V

the differential outputs of the amplifier. In addition to the input common mode + signal requirements for
the analog input pins, the differential outputs of the amplifier must remain between (VA- + 0.1 V) and
(VA+ - 0.1 V) to avoid saturation of the output stage.

6. See the section of the data sheet which discusses input models.

7. Input current on AIN+ or AIN- (with Gain = 1), or VREF+ or VREF- may increase to 250 nA if operated
within 50 mV of VA+ or VA-. This is due to the rough charge buffer being saturated under these
conditions.

DS289F1 5

± Gain*(AIN+ - AIN-)/2 at

CM

ANALOG CHARACTERISTICS (Continued)

(See Notes 1 and 2.)

Parameter

Power Supplies

DC Power Supply Currents (Normal Mode) I

Power Consumption Normal Mode (Notes 8 and 9)

Standby
Sleep

Power Supply Rejection (Note 10)

dc Positive Supplies
dc Negative Supply

8. All outputs unloaded. All input CMOS levels.

9. Power is specified when the instrumentation amplifier (Gain ≥ 2) is on. Analog supply current is reduced

by approximately 1/2 when the instrumentation amplifier is off (Gain = 1).

10. Tested with 100 mV change on VA+ or VA-.

A+, IA-

I

D+

CS5531/32/33/34

CS5531/32/33/34-AS CS5532/34-BS

Min Typ

-

-

-

-

-

-

-

7

0.5

40

5

500

115
115

Max

9
1

50

-

-

-

-

Min Typ

-

-

-

13

0.5

70

-

-

500

-

115

-

115

Max

4

15

1

80

Unit

mA
mA

mW

-

mW

-

µW

-

-

dB
dB

6 DS289F1

TYPICAL RMS NOISE (nV), CS5531/32/33/34-AS

(See notes 11, 12 and 13)

CS5531/32/33/34

Output Word

Rate (Sps)

7.5 1.94 171719264279155
15 3.88 24 25 27 36 59 111 218
30 7.75 34 35 39 51 84 157 308
60 15.5 48 49 54 72 118 222 436

120 31 68 70 77 102 167 314 616
240 62 115 160 276 527 1040 2070 4150
480 122 163 230 392 748 1480 2950 5890

960 230 229 321 554 1060 2090 4170 8340
1,920 390 344 523 946 1840 3650 7290 14600
3,840 780 1390 2710 5390 10800 21500 43000 86100

Notes: 11. Wideband noise aliased into the baseband. Referred to the input. Typical values shown for 25 °C.

12. For Peak-to-Peak Noise multiply by 6.6 for all ranges and output rates.

13. Word rates and -3dB points with FRS = 0. When FRS = 1, word rates and -3dB points scale by 5/6.

-3 dB Filter

Frequency (Hz)

x64 x32 x16 x8 x4 x2 x1

Instrumentation Amplifier Gain

TYPICAL NOISE FREE RESOLUTION(BITS), CS5532/34-AS (See Notes 14 and 15)

Output Word

Rate (Sps)

7.5 1.94 1920212222 22 22
15 3.88 19 20 21 21 21 22 22
30 7.75 18 19 20 21 21 21 21
60 15.5 18 19 20 20 20 21 21

120 31 17181920202020
240 62 16171717171717
480 122 16 17 17 17 17 17 17

960 230 15 16 16 16 16 16 16
1,920 390 151515151515 15
3,840 780 131313131313 13

-3 dB Filter

Frequency (Hz)

x64 x32 x16 x8 x4 x2 x1

Instrumentation Amplifier Gain

14. Noise Free Resolution listed is for Bipolar operation, and is calculated as LOG((Input Span)/(6.6xRMS
Noise))/LOG(2) rounded to the nearest bit. For Unipolar operation, the input span is 1/2 as large, so one
bit is lost. The input span is calculated in the analog input span section of the data sheet. The Noise
Free Resolution table is computed with a value of 1.0 in the gain register. Values other than 1.0 will
scale the noise, and change the Noise Free Resolution accordingly.

15. “Noise Free Resolution” is not the same as “Effective Resolution”. Effective Resolution is based on the
RMS noise value, while Noise Free Resolution is based on a peak-to-peak noise value specified as 6.6
times the RMS noise value. Effective Resolution is calculated as LOG((Input Span)/(RMS
Noise))/LOG(2).

Specifications are subject to change without notice.

DS289F1 7

TYPICAL RMS NOISE (nV), CS5532/34-BS

(See notes 16, 17, 18 and 19)

CS5531/32/33/34

Output Word

Rate (Sps)

7.5 1.94 8.5 9 1015265099
15 3.88 12 13 15 21 37 70 139
30 7.75 17 18 21 30 52 99 196
60 15.5 24 25 29 42 73 140 277

120 31 34 36 42 59 103 198 392
240 62 80 136 260 514 1020 2050 4090
480 122 113 194 369 730 1450 2900 5810

960 230 159 274 523 1030 2060 4110 8230
1,920 390 260 470 912 1810 3620 7230 14500
3,840 780 1360 2690 5380 10800 21500 43000 86000

Notes: 16. The -B devices provide the best noise specifications.

17. Wideband noise aliased into the baseband. Referred to the input. Typical values shown for 25 °C.

18. For Peak-to-Peak Noise multiply by 6.6 for all ranges and output rates.

19. Word rates and -3dB points with FRS = 0. When FRS = 1, word rates and -3dB points scale by 5/6.

-3 dB Filter

Frequency (Hz)

x64 x32 x16 x8 x4 x2 x1

Instrumentation Amplifier Gain

TYPICAL NOISE FREE RESOLUTION(BITS), CS5532/34-BS

(See Notes 20 and 21)

Output Word

Rate (Sps)

7.5 1.94 2021222323 23 23
15 3.88 20 21 22 22 22 22 22
30 7.75 19 20 21 22 22 22 22
60 15.5 19 20 21 21 21 21 21

120 31 1819202121 21 21
240 62 1717181818 18 18
480 122 17 17 17 17 17 17 17

960 230 16 16 17 17 17 17 17
1,920 390 16161616161616
3,840 780 13131313131313

20. Noise Free Resolution listed is for Bipolar operation, and is calculated as LOG((Input Span)/(6.6xRMS
Noise))/LOG(2) rounded to the nearest bit. For Unipolar operation, the input span is 1/2 as large, so one
bit is lost. The input span is calculated in the analog input span section of the data sheet. The Noise
Free Resolution table is computed with a value of 1.0 in the gain register. Values other than 1.0 will scale
the noise, and change the Noise Free Resolution accordingly.

21. “Noise Free Resolution” is not the same as “Effective Resolution”. Effective Resolution is based on the
RMS noise value, while Noise Free Resolution is based on a peak-to-peak noise value specified as 6.6
times the RMS noise value. Effective Resolution is calculated as LOG((Input Span)/(RMS
Noise))/LOG(2).

-3 dB Filter

Frequency (Hz)

Specifications are subject to change without notice.

x64 x32 x16 x8 x4 x2 x1

Instrumentation Amplifier Gain

8 DS289F1

CS5531/32/33/34

5 V DIGITAL CHARACTERISTICS (VA+, VD+ = 5 V ±5%; VA-, DGND = 0 V;

See Notes 2 and 22.)

Parameter Symbol Min Typ Max Unit

High-Level Input Voltage All Pins Except SCLK

SCLK

Low-Level Input Voltage All Pins Except SCLK

SCLK

High-Level Output Voltage A0 and A1, I

SDO, I

Low-Level Output Voltage A0 and A1, I

SDO, I

= -1.0 mA

out

= -5.0 mA

out

= 1.0 mA

out

= 5.0 mA

out

Input Leakage Current I

SDO 3-State Leakage Current I

Digital Output Pin Capacitance C

V

IH

V

IL

V

OH

V

OL

in

OZ

out

0.6 VD+

(VD+) - 0.45--

0.0

-0.8

0.0

(VA+) - 1.0

--V

(VD+) - 1.0

- - (VA-) + 0.4

-±1±10µA

--±10µA

-9-pF

VD+
VD+

0.6

0.4

V

V

V

3 V DIGITAL CHARACTERISTICS (T

= 25 °C; VA+ = 5V ±5%; VD+ = 3.0V±10%; VA-, DGND =

A

0V; See Notes 2 and 22.)

Parameter Symbol Min Typ Max Unit

High-Level Input Voltage All Pins Except SCLK

SCLK

Low-Level Input Voltage All Pins Except SCLK

SCLK

High-Level Output Voltage A0 and A1, I

SDO, I

Low-Level Output Voltage A0 and A1, I

SDO, I

= -1.0 mA

out

= -5.0 mA

out

= 1.0 mA

out

= 5.0 mA

out

Input Leakage Current I

SDO 3-State Leakage Current I

Digital Output Pin Capacitance C

22. All measurements performed under static conditions.

V

IH

0.6 VD+

(VD+) - 0.45

V

IL

0.0

0.0

V

OH

(VA+) - 1.0

-VD+

V

VD+

-0.8

V

0.6

-- V

(VD+) - 1.0

V

OL

- - (VA-) + 0.4

V

0.4

in

OZ

out

-±1±10µA

--±10µA

-9-pF

DS289F1 9

DYNAMIC CHARACTERISTICS

Parameter Symbol Ratio Unit

Modulator Sampling Rate f

Filter Settling Time to 1/2 LSB (Full Scale Step Input)

Single Conversion mode (Notes 23, 24, and 25)
Continuous Conversion mode, OWR < 3200 Sps
Continuous Conversion mode, OWR ≥ 3200 Sps

CS5531/32/33/34

s

t

s

t

s

t

s

MCLK/16 Sps

1/OWR

5/OWR

sinc5

SC

+ 3/OWR

5/OWR

s
s
s

23. The ADCs use a Sinc5 filter for the 3200 Sps and 3840 Sps output word rate (OWR) and a Sinc5 filter
followed by a Sinc
(FRS = 0) word rate associated with the Sinc

3

filter for the other OWRs. OWR

5

filter.

refers to the 3200 Sps (FRS = 1) or 3840 Sps

sinc5

24. The single conversion mode only outputs fully settled conversions. See Table 1 for more details about
single conversion mode timing. OWR

is used here to designate the different conversion time

SC

associated with single conversions.

25. The continuous conversion mode outputs every conversion. This means that the filter’s settling time
with a full scale step input in the continuous conversion mode is dictated by the OWR.

ABSOLUTE MAXIMUM RATINGS

(DGND = 0 V; See Note 26.)

Parameter Symbol Min Typ Max Unit

DC Power Supplies (Notes 27 and 28)

Positive Digital

Positive Analog

Negative Analog

Input Current, Any Pin Except Supplies (Notes 29 and 30) I

Output Current I

Power Dissipation (Note 31) PDN - - 500 mW

Analog Input Voltage VREF pins

AIN Pins

Digital Input Voltage V

Ambient Operating Temperature T

Storage Temperature T

VD+
VA+

VA-

IN

OUT

V

INR

V

INA

IND

A

stg

-0.3

-0.3

+0.3

-

-

-

+6.0
+6.0

-3.75

V
V
V

--±10mA

--±25mA

(VA-) -0.3
(VA-) -0.3--

(VA+) + 0.3
(VA+) + 0.3VV

-0.3 - (VD+) + 0.3 V

-40 - 85 °C

-65 - 150 °C

Notes: 26. All voltages with respect to ground.

27. VA+ and VA- must satisfy {(VA+) - (VA-)} ≤ +6.6 V.

28. VD+ and VA- must satisfy {(VD+) - (VA-)} ≤ +7.5 V.

29. Applies to all pins including continuous overvoltage conditions at the analog input (AIN) pins.

30. Transient current of up to 100 mA will not cause SCR latch-up. Maximum input current for a power
supply pin is ±50 mA.

31. Total power dissipation, including all input currents and output currents.

WARNING: Operation at or beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes.

10 DS289F1

CS5531/32/33/34

SWITCHING CHARACTERISTICS

(VA+ = 2.5 V or 5 V ±5%; VA- = -2.5V±5% or 0 V; VD+ = 3.0 V ±10% or 5 V ±5%;DGND = 0 V; Levels: Logic 0 = 0
V, Logic 1 = VD+; C

Master Clock Frequency (Note 32)

Master Clock Duty Cycle 40 - 60 %

Rise Times (Note 33)

Fall Times (Note 33)

Start-up

Oscillator Start-up Time XTAL = 4.9152 MHz (Note 34) t

Serial Port Timing

Serial Clock Frequency SCLK 0 - 2 MHz

Serial Clock Pulse Width High

SDI Write Timing

CS

Enable to Valid Latch Clock t

Data Set-up Time prior to SCLK rising t

Data Hold Time After SCLK Rising t

SCLK Falling Prior to CS

SDO Read Timing

to Data Valid t

CS

SCLK Falling to New Data Bit t

Rising to SDO Hi-Z t

CS

= 50 pF; See Figures 1 and 2.)

L

Parameter Symbol Min Typ Max Unit

MCLK

External Clock or Crystal Oscillator

Any Digital Input Except SCLK

SCLK

Any Digital Output

Any Digital Input Except SCLK

SCLK

Any Digital Output

Pulse Width Low

Disable t

t

rise

t

fall

ost

t
t

1

2

3

4

5

6

7

8

9

1 4.9152 5 MHz

-

-

-

-

-

-

50

50

-

-

1.0

100

-

-

-

1.0

100

-

-20-ms

250
250

-

-

-

-

50 - - ns

50 - - ns

100 - - ns

100 - - ns

--150ns

--150ns

--150ns

µs
µs
ns

µs
µs
ns

ns
ns

Notes: 32. Device parameters are specified with a 4.9152 MHz clock.

33. Specified using 10% and 90% points on waveform of interest. Output loaded with 50 pF.

34. Oscillator start-up time varies with crystal parameters. This specification does not apply when using an
external clock source.

DS289F1 11

CS

CS5531/32/33/34

t3

CS

SDO

SDI

SCLK

t7

MSB

MSB-1

Figure 1. SDI Write Timing (Not to Scale)

MSB MSB-1

LSB

t6t4 t5 t1

t2

t9

LSB

t8

SCLK

t2

t1

Figure 2. SDO Read Timing (Not to Scale)

12 DS289F1

2. GENERAL DESCRIPTION

CS5531/32/33/34

The CS5531/32/33/34 are highly integrated ∆Σ
Analog-to-Digital Converters (ADCs) which use
charge-balance techniques to achieve 16-bit
(CS5531/33) and 24-bit (CS5532/34) perfor­mance. The ADCs are optimized for measuring
low-level unipolar or bipolar signals in weigh
scale, process control, scientific, and medical ap­plications.

To accommodate these applications, the ADCs
come as either two-channel (CS5531/32) or four­channel (CS5533/34) devices and include a very
low noise chopper-stabilized programmable gain
instrumentation amplifier (PGIA, 6 nV/√Hz @ 0.1
Hz) with selectable gains of 1×, 2×, 4×, 8×, 16×,
32×, and 64×. These ADCs also include a fourth
order ∆Σ modulator followed by a digital filter
which provides twenty selectable output word rat es
of 6.25, 7.5, 12.5, 15, 25, 30, 50, 60, 100, 120, 200,
240, 400, 480, 800, 960, 1600, 1920, 3200, and 3840
Samples per second (MCLK = 4.9152 MHz).

To ease communication between the ADCs and a
micro-controller, the converters include a simple

three-wire serial interface which is SPI and Mi­crowire compatible with a Schmitt Trigger input
on the serial clock (SCLK).

2.1. Analog Input

Figure 3 illustrates a block diagram of the
CS5531/32/33/34. The front end consists of a mul­tiplexer, a unity gain coarse/fine charge input buffer,
and a programmable gain chopper-stabilized instru­mentation amplifier. The unity gain buffer is acti­vated any time conversions are performed with a
gain of one and the instrumentation amplifier is ac­tivated any time conversions are performed with
gain settings greater than one.

The unity gain buffer is designed to accommodate
rail to rail input signals. The common-mode plus
signal range for the unity gain buffer amplifier is
VA- to VA+. Typical CVF (sampling) current for
the unity gain buffer amplifier is about 50 nA
(MCLK = 4.9152 MHz, see Figure 4).

The instrumentation amplifier is chopper stabi­lized and operates with a chop clock frequency of

AIN2+

AIN2-

AIN1+

AIN1-

AIN4+

AIN4-

AIN1+

AIN1-

*
*
*

CS5531/32

M

U
X

CS5533/34

M

U
X

VREF+

IN+

1000 Ω

22 nF

1000 Ω

X1

C1 PIN
C2 PIN

X1

IN-

IN+

IN-

IN+

IN-

GAIN is the gain setting of the PGIA (i.e. 2, 4, 8, 16, 32, 64)

X1

XGAIN

X1

VREF-

X1

Differential

th

4 Order

∆Σ

Modulator

X1

Sinc

Digital

Filter

5

Programmable

Digita l Filte r

Sinc

3

Serial

Port

Figure 3. Multiplexer Configuration

DS289F1 13

CS5531/32/33/34

MCLK/128. The CVF (sampling) current into the
instrumentation amplifier is typically 1200 pA over

-40°C to +85°C (MCLK=4.9152 MHz). The com­mon-mode plus signal range of the instrumentation
amplifier is (VA-) + 0.7 V to (VA+) - 1.7 V.

Figure 4 illustrates the input models for the ampli­fiers. The dynamic input current for each of the
pins can be determined from the models shown.

Gain=2,4,8,16,32,64

AIN

V≤8mV

os

i=fV C

n

os

AIN

V≤12 mV

os

i=fV C

osn

Figure 4. Input models for AIN+ and AIN- pins

MCLK

f=

Gain = 1

MCLK

f=

128

16

=3.9pF

C

φ

Fine

1

φ

Coarse

1

C=14pF

age applied to the VREF+ and VREF- pins on the
part. See section 2.3.5 for more details.

After reset, the unity gain buffer is engaged. With a

2.5V reference this would make the full scale input
range default to 2.5 V. By activating the instrumen­tation amplifier (i.e. a gain setting other than 1) and
using a gain setting of 32, the full scale input range
can quickly be set to 2.5/32 or about 78 mV. Note
that these input ranges assume the calibration regis­ters are set to their default values (i.e. Gain = 1.0 and
Offset = 0.0).

2.1.2. Multiplexed Settling Limitations

The settling performance of the CS5531/32/33/34
in multiplexed applications is affected by the sin­gle-pole low-pass filter which follows the instru­mentation amplifier (see Figur e 3). To achieve data
sheet settling and linearity specifications, it is rec­ommended that a 22 nF C0G capacitor be used. Ca­pacitors as low as 10 nF or X7R type capacitors can
also be used with some minor increase in distortion
for AC signals.

2.1.3. Voltage Noise Density Performance

Figure 5 illustrates the measured voltage noise den­sity versus frequency from 0.01 Hz to 10 Hz of a
CS5532-BS. The device was powered with ±2.5 V
supplies, using 120 Sps OWR, the 64x gain range,
bipolar mode, and with the input short bit enabled.

Note: The C=3.9pF and C = 14pF capacitors are for

input current modeling only. For physical
input capacitance see ‘Input Capacitance’
specification under Analog Characteristics.

2.1.1. Analog Input Span

The full scale input signal that the converter can dig­itize is a function of the gain setting and the refer­ence voltage connected between the VREF+ and

100

Hz

√

10

nV/

1

0.01 0.1 1 10

Freque ncy (Hz)

Gain = 64

VREF- pins. The full scale input span of the convert­er is ((VREF+) - (VREF-))/(GxA), where G is the
gain of the amplifier and A is 2 for VRS = 0, or A is
1 for VRS = 1. VRS is the Voltage Reference Select
bit, and must be set according to the differential volt-

Figure 5. Measured Voltage Noise Density

2.1.4. No Offset DAC

An offset DAC was not included in the CS553X
family because the high dynamic range of the con-

14 DS289F1

CS5531/32/33/34

verter eliminates the need for one. The offset regis­ter can be manipulated by the user to mimic the
function of a DAC if desired.

2.2. Overview of ADC Register Structure and Operating Modes

The CS5531/32/33/34 ADCs have an on-chip con­troller, which includes a number of user-accessible
registers. The registers are used to hold offset and
gain calibration results, configure the chip's operat­ing modes, hold conversion instructions, and to
store conversion data words. Figure 6 depicts a
block diagram of the on-chip controller’s internal
registers.

Each of the converters has 32-bit registers to func­tion as offset and gain calibration registers for each
channel. The converters with two channels have
two offset and two gain calibration registers, the
converters with four channels have four offset and
four gain calibration registers. These registers hold
calibration results. The contents of these registers

can be read or written by the user. This allows cal­ibration data to be off-loaded into an external EE­PROM. The user can also manipulate the contents
of these registers to modify the offset or the gain
slope of the converter.

The converters include a 32-bit configuration reg­ister which is used for setting options such as the
power down modes, resetting the converter, short­ing the analog inputs, and enabling diagnostic test
bits like the guard signal.

A group of registers, called Channel Setup Regis­ters, are used to hold pre-loaded conversion in­structions. Each channel setup register is 32 bits
long, and holds two 16-bit conversion instructions
referred to as Setups. Upon power up, these regis­ters can be initialized by the system microcontrol­ler with conversion instructions. The user can then
instruct the converter to perform single or multiple
conversions or calibrations with the converter in
the mode defined by one of these Setups.

Offset Registers (4 x 32) Gain Registers (4 x 32)

Offset1(1x32)

Offset 2 (1 x 32)

Offset 3 (1 x 32)

Offset 4 (1 x 32)

Configuration Register (1 x 32)

Power Save Select
Reset System
Input Short
Guard Signal
Voltage Reference Select
Output Latch
Output Latch Select
Offset/Gain Se lect
Filter Rate Select

Gain 1 (1 x 32)

Gain 2 (1 x 32)

Gain 3 (1 x 32)

Gain 4 (1 x 32)

Figure 6. CS5531/32/33/34 Register Diagram

Channel Setup

Registers (4 x 32)

Setup 1
(1 x 16)

Setup 3
(1 x 16)

Setup 5
(1 x 16)

Setup 7
(1 x 16)

Channel Select
Gain

Word Rate
Unipolar/Bipo lar
Output Latch
Delay T ime
Open Circuit Detect

Offset/Gain Pointer

Setup 2
(1 x 16)

Setup 4
(1 x 16)

Setup 6
(1 x 16)

Setup 8
(1 x 16)

Write Only

Command

Register (1 × 8)

Conversion Data

Register (1 x 32)

Data (1 x 32)

Read Only

Serial

Interface

CS
SDI
SDO
SCLK

DS289F1 15

CS5531/32/33/34

Using the single conversion mode, an 8-bit com­mand word can be written into the serial port. The
command includes pointer bits which ‘point’ to a
16-bit command in one of the Channel Setup Reg­isters which is to be executed. The 16-bit Setups
can be programmed to perform a conversion on any
of the input channels of the converter. More than
one of the 16-bit Setups can be used for the same
analog input channel. This allows the user to con­vert on the same signal with either a different con­version speed, a different gain range, or any of the
other options available in the channel setup regis­ters. Alternately, the user can set up the registers to
perform different conversion conditions on each of
the input channels.

The ADCs also include continuous conversion ca­pability. The ADCs can be instructed to continu­ously convert, referencing one 16-bit command
Setup. In the continuous conversions mode, the
conversion data words are loaded into a shift regis­ter. The converter issues a flag on the SDO pin
when a conversion cycle is completed so the user
can read the register, if need be. See the section on
Performing Conversions for more details.

The following pages document how to initialize the
converter, perform offset and gain calibrations, and
how to configure the converter for the various con­version modes. Each of the bits of the configuration
register and of the Channel Setup Registers is de­scribed. A list of examples follows the description
section. Also the Command Register Quick Refer-
ence can be used to decode all valid commands (the
first 8-bits into the serial port).

2.2.1. System Initialization

The CS5531/32/33/34 provide no power-on-reset
function. To initialize the ADCs, the user must per­form a software reset by resetting the ADC’s serial
port with the Serial Port Initialization sequence.
This sequence resets the serial port to the command
mode and is accomplished by transmitting at least
15 SYNC1 command bytes (0xFF hexadecimal),

followed by one SYNC0 command (0xFE hexa­decimal). Note that this sequence can be initiated at
anytime to reinitialize the serial port. To complete
the system initialization sequence, the user must
also perform a system reset sequence which is as
follows: Write a logic 1 into the RS bit of the con­figuration register. This will reset the calibration
registers and other logic (but not the serial port). A
valid reset will set the RV bit in the configuration
register to a logic 1. After writing the RS bit to a
logic 1, wait 20 microseconds, then write the RS bit
back to logic 0. While this involves writing an en­tire word into the configuration register, the RV bit
is a read only bit, therefore a write to the configu­ration register will not overwrite the RV bit. After
clearing the RS bit back to logic 0, read the config­uration register to check the state of the RV bit as
this indicates that a valid reset occurred. Reading
the configuration register clears the RV bit back to
logic 0.

Completing the reset cycle initializes the on-chip
registers to the following states:

Configuration Register: 00000000(H)
Offset Registers: 00000000(H)
Gain Registers: 01000000(H)
Channel Setup Registers: 00000000(H)

Note: Previous datasheets stated that the RS bit

would clear itself back to logic 0 and therefore
the user was not required to write the RS bit
back to logic 0. The current data sheet
instruction that requires the user to write into
the configuration register to clear the RS bit
has been added to insure that the RS bit is
cleared. Characterization across multiple lots
of silicon has indicated some chips do not
automatically reset the RS bit to logic 0 in the
configuration register, although the reset
function is completed. This occurs only on
small number of chips when the VA- supply is
negative with respect to DGND. This has not
caused an operational issue for customers
because their start-up sequence includes
writing a word (with RS=0) into the
configuration register after performing a

16 DS289F1