Cirrus Logic CS5529-AS, CS5529-AP Datasheet
CS5529
16-Bit, Programmable
Features
l Delta-Sigma Analog-to-Digital Converter
- Linearity Error: 0.0015%FS
- Noise Free Resolution: 16-Bits
l 2.5 V Bipolar/Unipolar Buffered Input Range
l 6-Bit Output Latch
l Eight Digital Filters
- Selectable Output Word Rates
- Output Settles in One Conversion Cycle
- 50/60 Hz ±3 Hz Simultaneous Rejection
l Simple three-wire serial interface
- SPI™ and Microwire™ Compatible
- Schmitt Trigger on Serial Clock (SCLK)
l System/Self-Calibration with R/W Registers
l Power Supply Configurations
- VA+ = +5 V; VA- = 0 V; VD+ = +3 V to +5 V
- VA+ = +2.5 V; VA- = -2.5 V; VD+ = +3 V to +5 V
l Low Power Consumption: 2.5 mW
∆Σ
ADC with 6-Bit Latch
General Description
The 16-bit CS5529 is a low-power programmable ∆Σ Analog-to-Digital Converter (ADC) which includes
coarse/fine charg e buf fers, a fou rt h or der ∆Σ modulator,
a calibration microcontroller, a digital filter with programmable decimation rates, a 6-bit output latch, and a threewire serial interface. The ADC is designed to operate
from single or dual analog supplie s and a single digital
supply.
The digital filter is programmable with output update
rates between 1.88 Hz to 101 Hz. These output rates are
specified for XIN = 32.768 kHz . Output word rate s can be
increased by approximately 3X by using XIN = 100 kHz.
The filter is designed to settle to full accuracy for the selected output word rate in one conversion. When
operated at word rates of 1 5 Hz or less, the fi lt er re ject s
both 50 Hz and 60 Hz simultaneously.
Low power, single conversion settling time, programmable output rates, and the ability to handle ne gative inpu t
signals make th is sing le or dual s upp ly pro duct a n ideal
solution for isolated and non-isolated applications.
AIN+
AIN-
VREF+
VREF-
VA+
VA- DGND
1X
1X
Latch
A0 A1 D0 D1 D2 D3
Differential
4th Order
Delta-Sigma
Modulator
Calibration
Memory
ORDERING INFORMATION
See page 27.
Digital Filte r
Clock
Calibration µC
Gen.
XIN XOUT
VD+
Calibration
Register
Control
Register
Output
Register
CS
SCLK
SDI
SDO
Cirrus Logic, Inc.
Crystal Semiconductor Products Division
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.crystal.com
Copyright Cirrus Logic, Inc. 1999
(All Rights Reserved)
MAR ‘99
DS246F1
1
TABLE OF CONTENTS
TABLE OF CONTENTS ................. ....... ...... ....... ...... ...... ....... ...... ....... ...... ............ 2
TABLE OF FIGURES ........................................................... ...... ....... ...... ....... ..... 3
CHARACTERISTICS/SPECIFICATIONS ................................................ ............4
ANALOG CHARACTERISTICS................................................................... 4
5 V DIGITAL CHARACTERISTICS .............................................................6
3 V DIGITAL CHARACTERISTICS .............................................................6
DYNAMIC CHARACTERISTICS ................................................................. 6
ABSOLUTE MAXIMUM RATINGS.............................................................. 7
SWITCHING CHARACTERISTICS ................................................. ....... ..... 8
GENERAL DESCRIPTION ................................................................................10
Analog Input ............................................................................................. 10
Analog Input Model ............................................................................10
Voltage Reference Input Model ..........................................................10
Serial Port ................................................................................................. 11
Command Register Descriptions ........................................................12
Serial Port Interface ...........................................................................13
Serial Port Initialization ....................................................................... 15
System Initialization ................................. ...... ....... ............................. 1 5
Configuration Register ..............................................................................15
Latch Output Pins ...............................................................................15
Power Consumption ...........................................................................15
Output Word Rate ..............................................................................16
Digital Filter ........................................................................................16
Clock Generator ................................................................................. 16
Reset System ................. ....... ...... ....... ...... ...... ....... ............................. 16
Port Flag .............................................................................................17
Calibration .......................................................................................... 17
Configuration Register Descriptions ................................................. 20
Performing Conversions ...........................................................................21
Performing Conversions with PF bit = 0 ............................................. 21
Performing Conversions with PF bit = 1 ............................................. 21
Output Coding .................................................................................... 22
Power Supply Arrangements .................................................................... 23
PCB Layout .............................................................................................. 24
PIN DESCRIPTIONS ......................................................................................... 25
Clock Generator.........................................................................................25
Control Pins and Serial Data I/O................................................................25
Measurement and Reference Inputs ......................................................... 26
Power Supply Connections........................................................................26
SPECIFICATION DEFINITIONS ........................................................................ 27
ORDERING GUIDE ............................................................................................ 27
PACKAGE DIMENSIONS ................................................................................. 28
CS5529
Calibration Registers ................................................................... 17
Offset Register ......................................................................17
Gain Register ........................................................................18
Self Calibration ............................................................................ 18
System Calibration .......................................................................18
Limitations in Calibration Range ..................................................19
Calibration Tips ............................................................................ 19
Single Conversion ........................................................................ 21
Continuous Conversions ..............................................................21
2 DS246F1
TABLE OF FIGURES
Input models for AIN+ and AIN- pins......................................................... 11
Input model for VREF+ and VREF- pins. .................................................. 11
CS5529 Register Diagram. ....................................................................... 11
Command and Data Word Timing............................................................. 14
Filter Response (Normalized to Output Word Rate = 1)............................ 16
Self Calibration of Offset. .......................................................................... 18
Self Calibration of Gain. ............................................................................ 18
System Calibration of Offset...................................................................... 18
System Calibration of Gain........................................................................ 19
CS5529 Configured with a +5.0 V Analog Supply..................................... 23
CS5529 Configured with ±2.5 V Analog Supplies..................................... 23
CS5529
SPI™ is a trademark of Motorola Inc., Microwire™ is a trademark of National Semiconductor Corp.
Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product infor-
mation describes products which are in development and subj ect to development changes. Cirrus Logic, In c. has made best effor ts to ensure that the information contained in thi s document is accura te and reliabl e. However, the i nformation is subje ct to change withou t notice and i s provided “AS IS” witho ut
warranty of any k in d (express or implied ) . No responsibility is ass u med by Cirrus Logic, Inc. for the use of this in f ormation, nor for infringements of patents or
other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets.
No part of this publication may be copied, reprod uced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user.
However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a
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and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list
of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.
DS246F1 3
CHARACTERISTICS/SPECIFICATIONS
CS5529
ANALOG CHARACTERISTICS (T
VREF- = 0.0 V, F
(See Notes 1 and 2.)
= 32.768 kHz, OWR (Output Word Rate) = 15 Hz, Bipolar Mode, Input Range = ±2.5 V.)
CLK
Parameter Min Typ Max Unit
= 25 °C; VA± = ±2.5 V ±5%, VD + = 5 V ±5%, VR EF+ = 2.5 V,
A
Accuracy
Linearity Error - ±0.0015 ±0.003 %FS
No Missing Codes 16 - - Bits
Bipolar Offset (Note 3) - ±1 ±2 LSB
Unipolar Offset (Note 3) - ±2 ±4 LSB
Offset Drift (Notes 3 and 4) - 11 - nV/°C
Bipolar Gain Error - ±8 ±31 ppm
Unipolar Gain Error - ±16 ±63 ppm
Gain Drift (Note 4) - 1 - ppm/°C
Noise (Notes 5 and 6)
Output Word Rate (Hz) -3 dB Filter Frequency (Hz) Noise (µV)
1.88 1.64 4.5
3.76 3.27 5.0
7.51 6.55 7.0
15.0 12.7 15
30.0 25.4 45
61.6 50.4 190
84.5 70.7 900
101.1 84.6 3000
16
16
Notes: 1. Applies after system calibration at any temperature within -40 °C ~ +85 °C.
2. Specifications guaranteed by design, characterization, and/or test.
3. Specification applies to the device only and does not include any effects by external parasitic
thermocouples.
4. Drift over specified temperature range after calibration at power-up at 25 °C.
5. Wideband noise aliased into the baseband. Referred to the input. Typical values shown for 25 °C.
6. For peak-to-peak noise multiply by 6.6 for all ranges and output rates.
Specifications are subject to change without notice.
4 DS246F1
CS5529
ANALOG CHARACTERISTICS (Continued)
Parameter Min Typ Max Unit
Analog Input
Common Mode + Signal on AIN+ or AIN- (Bipolar/Unipolar Mode)
Single Supply
Dual Supply
Common Mode Rejection dc
50, 60Hz
Input Capacitance - 10 - pF
CVF Current AIN+, AIN- (Note 7) - 16 - nA
System Calibration Specifications
Full Scale Calibration Range, with VREF = 2.5 V (Note 8) 1.0 - 3.5 V
Offset Calibration Range (Bipolar/Unipolar Mode) - - ±1.25 V
Voltage Reference Input
Range {(VREF+) - (VREF-)} (Note 9) 1.0 2.5 5 V
REF+ VA- - VA+ V
REF- VA- - VA+ V
Common Mode Rejection dc
50, 60 Hz
Input Capacitance - 16 - pF
CVF Current (Note 7) - 8 - nA
Power Supplies
DC Power Supply Currents (Normal Mode)
I
A+
I
D+
Power Consumption Normal Mode (Note 10)
Low Power Mode
Standby
Sleep
Power Supply Rejection dc Positive Supplies
dc Negative Supply
0.0
VA-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
120
120
110
130
360
95
2.5
1.4
1
500
80
80
VA+
VA+
-
-
-
-
450
150
2.875
2.2
-
-
-
-
dB
dB
dB
dB
µA
µA
mW
mW
mW
µW
dB
dB
V
V
Notes: 7. See the section of the data sheet which discusses Analog Input Models.
8. The minimum Full Scale Calibration Range (FSCR) is limited by the maximum allowed gain register
value (with margin). The maximum FSCR is limited by the
“Analog Input” section for details. Also see “Limitations in Calibration Range”.
9. VREF must be less than or equal to supply voltages.
10. All outputs unloaded. All inputs CMOS levels.
DS246F1 5
∆Σ
modulator’s 1’s density range. See
CS5529
5 V DIGITAL CHARACTERISTICS (T
= 25 °C; VA± = ±2.5V
A
and 11.)
Parameter Symbol Min Typ Max Unit
High-Level Input Voltage: All Pins Except XIN, SCLK
XIN
SCLK
Low-Level Input Voltage: All Pins Except XIN, SCLK
XIN
SCLK
High- L evel O u t put Voltage: All Pins Except SDO (Note 12)
SDO, I
Low-Level Output Voltage: All Pins Except SDO, I
SDO, I
= -5.0mA
out
= 1.6mA
out
= 5.0mA
out
Input Leakage Current I
3-State Leakage Current I
Digital Output Pin Capacitance C
Notes: 11. All measurements performed under static conditions.
12. I
= -100 µA unless stated otherwise. (VOH = 2.4 V @ I
out
out
±
5%, VD+ = 5V ± 5% .)(See Notes 2
V
IH
V
IH
IH
IL
IL
IL
OH
OH
OL
OL
in
OZ
out
(VD+)-0.45
V
V
V
V
V
V
V
V
= -40 µA).
0.6VD+
(VD+)-0.9
-
-
-
(VD+)-1.0
(VD+)-1.0--
-
-
-
-
-
-
-
-
-
-
-
0.8
2.0
0.6
-
-
-
-
0.4
0.4
-±1±10µA
--±10µA
-9-pF
V
V
V
V
V
V
V
V
V
V
3 V DIGITAL CHARACTERISTICS (T
= 25 °C; VA± = ±2.5 V ±5%, VD+ = 3.0 V ±5%.)
A
(See Notes 2 and 11.)
Parameter Symbol Min Typ Max Unit
High-Level Input Voltage: All Pins Except XIN, SCLK
XIN
SCLK
Low-Level Input Voltage: All Pins Except XIN, SCLK
XIN
SCLK
High-Level Output Voltage: All Pins Except SDO, I
SDO, I
Low-Level Output Voltage: All Pins Except SDO, I
SDO, I
= -400 µA
out
= -5.0 mA
out
= 400 µA
out
= 5.0 mA
out
Input Leakage Current I
3-State Leakage Current I
Digital Output Pin Capacitance C
DYNAMIC CHARACTERISTICS
Parameter Symbol Ratio Units
V
IH
V
IH
V
IH
V
IL
V
IL
V
IL
V
OH
V
OH
V
OL
V
OL
in
OZ
out
0.6VD+
(VD+)-0.9
(VD+)-0.45
-
-
-
(VD+)-0.3
(VD+)-1.0--
-
-
-±1±10µA
--±10µA
-9-pF
-
-
-
-
-
-
-
-
-
-
-
0.16 VD+
0.5
0.6
-
-
0.3
0.4
V
V
V
V
V
V
V
V
V
V
Modulator Sampling Frequency f
Filter Settling Time to 1/2 LSB (Full Scale Step) t
s
s
XIN/4 Hz
1/f
out
s
6 DS246F1
CS5529
ABSOLUTE MAXIMUM RATINGS (DGND = 0 V) (See Note 13.)
Parameter Symbol Min Typ Max Unit
DC Power Supplies (Notes 14 and 15)
Positive Digital
Positive Analog
Negative Analog
Input Current, Any Pin Except Supplies (Notes 16 and 17) I
Output Current I
Power Dissipation (Note 18) PD N - - 8 mW
Analog Input Voltage AIN and VREF pins V
Digital Input Voltage V
Ambient Operating Temperature T
Storage Temperature T
Notes: 13. All voltages with respect to ground.
14. VA+ and VA- must satisfy {(VA+) - (VA-)} ≤ +6.0 V.
15. VD+ and VA- must satisfy {(VD+) - (VA-)} ≤ +7.75 V.
16. Applies to all pins including continuous overvoltage conditions at the analog input (AIN) pins.
17. Transient current of up to 100mA will not cause SCR latch-up. Maximum input current for a power
supply pin is ±50 mA.
18. Total power dissipation, including all input currents and output currents.
VD+
VA+
VA-
IN
OUT
INA
IND
A
stg
-0.3
-0.3
-6.0
-
-
-
+6.0
+6.0
+0.3
--±10mA
--±25mA
(VA-) + (-0.3) - (VA+)+0.3 V
-0.3 - (VD+)+0.3 V
-40 - +85 °C
-65 - +150 °C
V
V
V
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
DS246F1 7
CS5529
SWITCHING CHARACTERISTICS (T
Input Levels: Logic 0 = 0 V, Logic 1 = VD+; C
= 50pF)
L
= 25 °C; VA ± = ±2.5 V ±5%, VD+ = 3 V ±5% or 5 V ±5%;
A
Parameter Symbol Min Typ Max Unit
Master Clock Frequency: External Clock or Internal Oscillator
XIN 30 32.768 100 kHz
(Note19)
Master Clock Duty Cycle 40 - 60 %
Rise Times (Note 20)
Any Digital Input Except SCLK
SCLK
Any Digital Output
Fall Times (Note 20)
Any Digital Input Except SCLK
SCLK
Any Digital Output
t
t
rise
rise
-
-
-
-
-
-
50
50
-
-
-
-
1.0
100
-
1.0
100
-
µs
µs
ns
µs
µs
ns
Start-up
Oscillator Start-up Time XTAL = 32.768 kHz (Note 21) t
Power-on Reset Period t
ost
por
-500-ms
- 1002 - XIN
cycles
Serial Port Timing
Serial Clock Frequency SCLK 0 - 2 MHz
Serial Clock Pulse Width High
Pulse Width Low
t
1
t
2
250
250
-
-
-
-
ns
ns
SDI Write Timing
CS Enable to Valid Latch Clock t
Data Set-up Time prior to SCLK rising t
Data Hold Time After SCLK Rising t
SCLK Falling Prior to CS
Disable t
3
4
5
6
50 - - ns
50 - - ns
100 - - ns
100 - - ns
SDO Read Timing
CS to Data Valid t
SCLK Falling to New Data Bit t
CS
Rising to SDO Hi-Z t
7
8
9
--150ns
--150ns
--150ns
Notes: 19. Device parameters are specified with 32.768 kHz clock, however, clocks up to 100 kHz can be used for
increased throughput.
20. Specified using 10% and 90% points on waveform of interest. Output loaded with 50 pF.
21. Oscillator start-up time varies with crystal parameters. This specification does not apply when using an
external clock source.
8 DS246F1
CS
CS5529
SCLK
CS
SDI
SCLK
t3
MSB
t3
t1
t2
Continuous Running SCLK Timing (Not to Scale)
MSB-1
t2
t6
LSB
t6t4 t5 t1
SDI Write Timing (Not to Scale)
CS
SDO
t7
MSB MSB-1
t8
t2
LSB
t9
SCLK
t1
SDO Read Timing (Not to Scale)
DS246F1 9
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