Cirrus Logic CS5525-BS, CS5525-BP, CS5525-AS, CS5525-AP Datasheet
CS5525
CS5526
16-Bit/20-Bit Multi-Range ADC with 4-Bit Latch
Features
l
Delta-Sigma A/D Converter
- Linearity Error: 0.0015%FS
- Noise Free Resolution: 18-bits
l
Bipolar/Unipolar Input Ranges
- 25 mV, 55 mV, 100 mV, 1 V, 2.5 V and 5 V
l
Chopper Stabilized Instrumentation Amplifier
l
On-Chip Charge Pump Drive Circuitry
l
4-Bit Output Latch
l
Simple three-wire serial interface
- SPI™ and Microwire™ Compatible
- Schmitt Trigger on Serial Clock (SCLK)
l
Programmable Output Word Rates
- 3.76 Hz to 202Hz (XIN = 32.768 kHz)
- 11.47 Hz to 616 Hz (XIN = 100 kHz)
l
Output Settles in One Conversion Cycle
l
Simultaneous 50/60 Hz Noise Rejection
l
System and Self-Calibration with
Read/Write Registers
l
Single +5 V Analog Supply
+3.0 V or +5 V Digital Supply
l
Low Power Mode Consumption: 4 mW
- 1.8 mW in 1 V, 2.5 V, and 5 V Input Ranges
General Description
The 16-bit CS5525 and the 20-bit CS5526 ar e highl y integrated
instrumentation amplifier, a PGA (programmable gain
amplifier), eight digital filters, and self and system calibration circuitry.
The converters are designed to provide their own negative supply which enables their on-chip instrumentation
amplifiers to measure bipolar ground-referenced si gnals
≤
±100 mV. By directly supplying NBV with -2.5 V and
with VA+ at 5 V,
can be measured.
The digital filters provide programmable output update
rates between 3.76 Hz to 202 Hz (XIN = 32.768 kHz).
Output word rates can be increased by appr oximately 3X
by using XIN = 100 kHz. Each filter is designed to settle
to full accuracy for its output update rate in one conversion cycle. The filters with word rates of 15 Hz or less
(XIN = 32.768 kHz) reject both 50 and 6 0 Hz (
interference simultaneously.
Low power, single conversion settling time, programmable output rates, and the ability to handle negative input
signals make these single supply products ideal solutions for isolated and n on-isolated applicati ons.
ORDERING INFORMATION
∆Σ
A/D converters which include an
See page 26.
±2.5 V signals (with respect to groun d)
±3 Hz) line
VA+ AGND VREF+ VREF- VD+DGND
AIN+
AIN-
NBV
A0
A1
A2
A3
Cirrus Logic, Inc.
Crystal Semiconductor Products Division
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.crystal.com
+
X20
-
Latch
Programmable
Gain
Calibration
Memory
CPD
Differential
4th Order
Delta-Sigma
Modulator
Calibration µC
Copyright Cirrus Logic, I nc. 1998
Digital Filter
Clock
Gen.
XIN XOUT
(All Rights Reserv ed)
Calibration
Register
Control
Register
Output
Register
CS
SCLK
SDI
SDO
JAN ‘98
DS202F1
1
CS5525 CS5526
ANALOG CHARACTERISTICS (T
NBV = -2.1 V, FCLK = 32.768 kHz, OWR (Output Word Rate) = 15 Hz, Bipolar Mode, Input Range = ±100 mV;
See Notes 1 and 2.)
Parameter
= 25 °C; VA+, VD+ = 5 V ±5%; VREF+ = 2.5 V, VREF- = AGND,
A
CS5525 CS5526
Min T yp Max Min Typ Max Unit
Accuracy
Linearity Error No Missing Codes 16 - - 20 - - Bits
Bipolar Offset (Note 3) Unipolar Offset (Note 3) Offset Drift (Notes 3 and 4) - 20 - - 20 - nV/°C
Bipolar Gain Error Unipolar Gain Error Gain Drift (Note 4) - 1 3 - 1 3 ppm/°C
±
0.0015±0.003 -
±
1±2 -
±
2
±
8
±
16
±
4-±32
±
31 -
±
62 -
±
0.0007±0.0015 %FS
±
16 ±32 LSB
±
64 LSB
±
8
±
16
±
31 ppm
±
62 ppm
Voltage Reference Input
Range (VREF+) - (VREF-) 1 2.5 3.0 1 2.5 3.0 V
Common Mode Rejection dc
50, 60 Hz
Input Capacitance - 16 - - 16 - pF
CVF Current (Note 5) - 0.6 - - 0.6 - µA/V
-
-
110
130
-
-
-
-
110
130
-
-
dB
dB
Notes: 1. Applies after system calibration at any temperature within -40 °C ~ +85 °C.
2. Specification s gu aranteed by design, characterization, and/or test.
3. Specification applies to the device only and does not include any effects by external parasitic
thermocouples. LSB = LSB
4. Drift over specified temperature range after calibration at power-up at 25 °C.
5. See the section of the data sheet which discusses input models on page 15.
for the CS5525, and LSB20 for the CS5526.
16
RMS NOISE (Notes 6 and 7)
Output Rate
(Hz)
3.76 3.27 90 nV 90 nV 130 nV 1.0 µV 2.0 µV 4.0 µV
7.51 6.55 110 nV 130 nV 190 nV 1.5 µV 3.0 µV 7 µV
15.0 12.7 170 nV 200 nV 250 nV 2.0 µV 5.0 µV 10 µV
30.1 25.4 250 nV 300 nV 500 nV 4.0 µV 10 µV 15 µV
60.0 50.4 500 nV 1.0 µ V 1.5 µV 15 µV 45 µV 85 µV
123.2 (Note 8) 103.6 2.0 µV 4.0 µ V 8.0 µV 72 µV 190 µV 350 µV
168.9 (Note 8) 141.3 10 µV 20.0 µV 30 µV 340 µV 900 µV 2.0 mV
202.3 (Note 8) 169.2 30 µV 55 µV 105 µV 1.1 mV 2.4 mV 5.3 mV
Notes: 6. Wideband noise aliased int o the baseband. Referred to the input . Typical values shown for 25 °C.
7. For Peak-to-Peak Noise multipl y by 6.6 for all ranges and output rat es.
8. For input ranges <100 mV and output word rates >60 Hz, 32.768 kHz chopping frequency is used.
-3 dB Filter
Frequency
25 mV 55 mV 100 mV 1 V 2.5 V 5 V
Specifications are su bject to change without notice.
Input Range, (Bipolar/Unipolar Mode)
2 DS202F1
CS5525 CS5526
ANALOG CHARACTERISTICS (Continued)
Parameter Min Typ Max Unit
Analog Input
Common Mode + Signal on AIN+ or AIN- Bipolar/Unipolar Mode
NBV = -1.8 to -2.5 V Range = 25 mV , 55 mV, or 100 mV
Range = 1 V, 2.5 V, or 5 V
NBV = AGND Range = 25 mV, 55 mV, or 100 mV
Range = 1 V, 2.5 V, or 5 V
Common Mode Rejection dc
50, 60 Hz
Input Capacitance - 10 - pF
CVF Current on AIN+ or AIN- (Note 5)
Range = 25 mV, 55 mV, or 100 mV
Range = 1 V, 2.5 V, or 5 V
System Calibration Specifications
Full Scale Calibration Range Bipolar/Unipolar Mode (Note 9)
25 mV
55 mV
100 mV
1 V
2.5 V
5 V
Offset Calibration Range Bipolar/Unipolar Mode
25 mV
55 mV
100 mV (Note 10)
1 V
2.5 V
5 V
Power Supplies
DC Power Supply Currents (Normal Mode) I
Power Consumption Normal Mode (Note 11)
Low Power Mode
St andby
Sleep
Power Supply Rejection dc Positive Supplies
dc NBV
I
NBV
-0.150
NBV
1.85
0.0
-
-
-
-
17.5
38.5
70
0.70
1.75
3.50
-
-
-
-
-
-
A+
I
D+
-
-
-
-
-
-
-
-
-
-
-
-
-
120
120
100
1.2
-
-
-
-
-
-
-
-
-
-
-
-
1.3
15
400
7.5
4.0
1.2
500
95
110
0.950
VA+
2.65
VA+
-
-
300
-
32.5
71.5
105
dB
dB
pA
µA/V
mV
mV
mV
1.30
3.25
VA+
±12.5
±27.5
±50
mV
mV
mV
±0.5
±1.25
±2.50
1.7
30
550
10
6.5
-
-
-
-
mA
µA
µA
mW
mW
mW
µW
dB
dB
V
V
V
V
V
V
V
V
V
V
Notes: 9. The minimum Full Scale Calibration Range (FSCR) is limited by the maximum allowed gain register
value (with margin). The maximum FSCR is limited by the
∆Σ
modulator’s 1’s density range.
10. The maximum full scale signal can be limited by saturation of circuitry within the internal signal path.
11. All outputs unloaded. All input CMOS levels.
DS202F1 3
CS5525 CS5526
5 V DIGITAL CHARACTERISTICS (T
= 25 °C; VA+, VD+ = 5 V ±5%; GND = 0;
A
See Notes 2 and 12.))
Parameter Symbol Min Typ Max Unit
High-Level Input Voltage All Pins Except XIN and SCLK
XIN
SCLK
Low-Level Input Voltage All Pins Except XIN and SCLK
XIN
SCLK
High-Level Output Voltage
All Pins Except CPD and SDO (Note 13)
CPD, I
SDO, I
= -4.0 mA
out
= -5.0 mA
out
Low-Level Output Voltage
All Pins Except CPD and SDO, I
CPD, I
SDO, I
= 1.6 mA
out
= 2 mA
out
= 5.0 mA
out
Input Leakage Current I
3-State Leakage Current I
Digital Output Pin Capacitance C
V
IH
0.6 VD+
3.5
(VD+) - 0.4 5
V
IL
-
0.0
-
V
OH
(VA+) - 1.0
(VD+) - 1.0
(VD+) - 1.0
V
OL
-
-
-
in
OZ
out
-±1±10µA
--±10µA
-9-pF
-
-
-
-
-
-
-
-
-
-
-
-
-
VD+
-
0.8
1.5
0.6
-
-
-
0.4
0.4
0.4
V
V
V
V
V
V
V
V
V
V
V
V
Notes: 12. All measurements performed under static conditions.
13. I
3.0 V DIGITAL CHARACTERISTICS (T
= -100 µA unless stated otherwise. (VOH = 2.4 V @ I
out
= 25 °C; VA+ = 5 V ±5%; VD+ = 3.0 V ±10%; GND = 0;
A
See Notes 2 and 12.))
Parameter Symbol Min Typ Max Unit
High-Level Input Voltage All Pins Except XIN and SCLK
XIN
SCLK
Low-Level Input Voltage All Pins Except XIN and SCLK
XIN
SCLK
High-Level Output Voltage
All Pins Except CPD and SDO, I
CPD, I
SDO, I
= -400 µA
out
= -4.0 mA
out
= -5.0 mA
out
Low-Level Output Voltage
All Pins Except CPD and SDO, I
CPD, I
SDO, I
= 400 µA
out
= 2 mA
out
= 5.0 mA
out
Input Leakage Current I
3-State Leakage Current I
Digital Output Pin Capacitance C
out
V
IH
V
IL
V
OH
V
OL
in
OZ
out
= -40 µA.)
0.6 VD+
0.54 VA+
(VD+) - 0.4 5
0.0
(VA+) - 0.3
(VD+) - 1.0
(VD+) - 1.0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
VD+
-
0.16 VD+
1.5
0.6
-
-
-
0.3
0.4
0.4
V
V
V
V
V
V
V
V
V
V
V
V
-±1±10µA
--±10µA
-9-pF
4 DS202F1
DYNAMIC CHARACTERISTICS
Parameter Symbol Ratio Unit
Modulator Sampling Frequency f
Filter Settling Time to 1/2 LSB (Full Scale S tep) t
CS5525 CS5526
s
s
XIN/2 Hz
1/f
out
s
RECOMMENDED OPERATING CONDITIONS
(AGND, DGND = 0 V; See Note 14.))
Parameter Symbol Min Typ Max Unit
DC Power Supplies Positive Digital
Positive Analog
Analog Reference Voltage (VREF+) - (VREF-) VRef
VD+
VA+
diff
2.7
4.75
5.0
5.0
5.25
5.25
1.0 2.5 3.0 V
V
V
Negative Bias Voltage NBV -1.8 -2.1 -2.5 V
Notes: 14. All voltages with respect to ground.
ABSOLUTE MAXIMUM RATINGS (AGND, DGND = 0 V; See Note 14.)
Parameter Symbol Min Max Unit
DC Power Supplies (Note 15)
Positive Digital
Positive Analog
Negative Bias Voltage Negative Potential NBV +0.3 -3.0 V
Input Current, Any Pin Except Supplies (Note 16 and 17) I
Output Current I
Power Dissipation (Note 18) PDN - 500 mW
Analog Input Voltage VREF pins
AIN Pins
Digital Input Voltage V
Ambient Operating Temperature T
Sto rage Temperature T
VD+
VA+
IN
OUT
V
INR
V
INA
IND
A
stg
-0.3
-0.3
+6.0
+6.0
V
V
-±10mA
-±25mA
-0.3
NBV - 0.3
(VA+) + 0.3
(VA+) + 0.3
V
V
-0.3 (VD+) + 0.3 V
-40 85 °C
-65 150 °C
Notes: 15. No pin should go more negative than NBV - 0.3 V.
16. Applies to all pins including continuous overvoltage conditions at the anal og input (AIN) pins.
17. Transient current of up to 100 mA will not cause SCR latch-up. Maximum input current for a power
supply pin is ±50 mA.
18. Total power dissipation, including all input currents and output currents.
WARNING: Operat ion at or beyond these limits may result in permanent damage to the device.
Normal operation is not guar anteed at these extremes.
DS202F1 5
CS5525 CS5526
SWITCHING CHARACTERISTICS (T
Input Levels: Logic 0 = 0 V, Logic 1 = VD+; C
= 50 pF.))
L
= 25 °C; VA+ = 5 V ±5%; VD+ = 3.0 V ±10% or 5 V ± 5%;
A
Parameter Symbol Min Typ Max Unit
Master Clock Frequency (Note 19)
Internal Clock
External Clock
XIN
30
30
32.768
32.768
36
100
kHz
Master Clock Duty Cycle 40 - 60 %
Rise Times (Note 20)
Any Digital Input Except SCLK
SCLK
Any Digital Output
Fall Times (Note 20)
Any Digital Input Except SCLK
SCLK
Any Digital Output
t
t
rise
fall
-
-
-
-
-
-
50
50
-
-
-
-
1.0
100
-
1.0
100
-
µs
µs
ns
µs
µs
ns
Start-up
Oscillator Start-up Time XTAL = 32.768 kHz (Note 21) t
Power-on Reset Period t
ost
por
- 500 - ms
- 1003 - XIN
cycles
Serial Port Timing
Serial Clock Frequency SCLK 0 - 2 MHz
SCLK Falling to CS
Falling for continuous running SCLK
t
0
100 - - ns
(Note 22)
Serial Clock Pulse Width High
Pulse Width Low
t
1
t
2
250
250
-
-
-
-
ns
ns
SDI Write Timing
CS Enable to Valid Latch Clock t
Data Set-up Time pr io r to S C L K rising t
Data Hold Time After SCLK Rising t
SCLK Falling Prior to CS
Disable t
3
4
5
6
50 - - ns
50 - - ns
100 - - ns
100 - - ns
SDO Read Timi ng
CS to Data Valid t
SCLK Falling to New Data Bit t
Rising to SDO Hi-Z t
CS
7
8
9
- - 150 ns
- - 150 ns
- - 150 ns
Notes: 19. Device parameters are specified with a 32.768 kHz clock; however , clocks up to 100 kHz can be used
for increased th roughput.
20. Specified using 10% and 90% points on waveform of interest. Output loaded with 50 pF.
21. Oscillator start-up time varie s wi th cr yst al par ameter s. Thi s s pecifi cati on do es not appl y when using an
external clock source.
22. Applicable when SCLK is cont inuously running.
6 DS202F1
CS
CS
SCLK
CS5525 CS5526
t
0
t
t
t
3
1
t
2
Continuous Running SCLK Timing (Not to Scale)
t
3
6
CS
SDO
SCLK
SCLK
t
7
MSB
MSB
MSB-1 LSBSDI
t
4
t
5
t
1
t
2
t
6
SDI Write Timing (Not to Scale)
t
9
MSB-1 LSB
t
8
t
2
t
1
SDO Read Timing (Not to Scal e)
DS202F1 7
CS5525 CS5526
GENERAL DESCRIPTION
The CS5525 and CS55 26 ar e 16 -bit an d 20- bit pin
compatible converters which include a chopperstabilized instrumentation amplifier input, and an
on-chip programmable gain amplifier. They are
both optimized for measuring low-level unipolar or
bipolar signals in pro cess control and med ical applicatio ns .
The CS552 5/26 also include a fou rth order deltasigma modulator, a calibration microcontroller,
eight digital filters, a 4-bit analog latch, and a serial
port. The digital fil ters provide an y one of ei ght
different outpu t update rates.
The CS5525/26 include a CPD (Charge Pump
Drive) output (shown in Figure 1). CPD provides a
negative bias voltage to the on-chip instrumentation amplifier when used with a combination of external diodes and capacitors. This enables the
CS5525/26 to me asure negative voltag es with re-
spect to ground, making the converters ideal for
thermocou p l e te mperature measurement s .
Theory of Operation
The CS5525/26 A/D converters are designed to operate from a single +5 V analog supply and provide
several different input ranges. See the Analog
Characteristics section on page 3 for details.
Figure 1 illustrates the CS5525/26 connected to
generate their o wn negative bias supply using the
on-chip CPD (Charge Pump Drive). This enables
the CS5525/ 26 to measure ground referenc ed signals with magnitudes down to NBV (Negative Bias
Voltage, approximately -2.1 V in this example).
Figure 2 illustrates a charge pump circuit when the
converters are p owered from a +3.0 V di gital sup ply. Alternative ly, the ne gative bi as supply c an be
generated from a negative supply voltage or a resistive divider as illustrated in Fig ure 3.
+5V
Analog
Supply
2.5V
Up to ± 100 mV Input
10 k
Ω
0.1 µF
Ω
10 k
Note: Cold-junction
measurement is performed
by a second A/D or via a
multiplexer.
Logic Outputs:
A0 - A3 Switch from VA+ to AGND.
0.1 µF0.1
BAV199
20
19
3
4
1
16
15
7
6
10 µF
10
Ω
213
VA+
VREF+
VREF-
AIN+
AINAGND
A3
A2
A1
A0
1N4148
+
VD+
CS5525
CS5526
CPD
8
*5MΩ
0.015 µF
1N4148
XOUT
XIN
CS
SCLK
SDI
SDO
DGNDNBV
10
32.768 ~ 100 kHz
9
18
11
17
14
125
*
Optional, see Charge
Pump Drive section.
Charg e-pump ne twork
for VD+ = 5V only and
XIN = 32.768 kHz.
Optional
Source
Serial
Interface
µ
F
Clock
Data
Figure 1. CS5525/26 Configured to use on-chip charge pump to supply NBV.
8 DS202F1
CS5525 CS5526
F
Figure 4 illustrates the CS5525/26 connected to
measure ground referenced unipolar signals of a
positive polarity using the 1 V, 2.5 V, and 5 V input
voltage ranges on the converter. For the 25 mV, 55
mV, and 100 mV ranges the signal must have a
common mo de nea r +2.5 V (NBV = 0V).
The CS5525/26 are optimized for the measurement
of thermocouple outputs, but they are also well
suited for the measurement of ratiometric bridge
transducer outputs. Figure 5 illustrates the
CS5525/26 c onnected to measure the output of a
ratiometric differential bridge transducer while operating from a single +5 V supply .
2N5087
or similar
NBV
10µF
+
Figure 2. Charge Pump Drive Circuit for VD+ = 3 V. Figure 3. Alternate NBV Circuits.
-5V
34.8K
30.1K
2.0K
NBV
2.1K
-5V
+
10
µ
10
+5V
Analog
Supply
2.5V
0 to +5V Input
CM = 0 to VA+
0.1 µF
+
-
20
19
3
4
1
16
15
7
6
VREF+
VREF-
AIN+
AIN-
AGND
A3
A2
A1
A0
Ω
213
VA+
5
CS5525
CS5526
CPD
8
VD+
XOUT
XIN
CS
SCLK
SDI
SDO
DGNDNBV
12
10
32.768 ~ 100 kHz
9
18
11
17
14
0.1
Optional
Clock
Source
Serial
Data
Interface
Figure 4. CS5525/26 Configured for ground-referenced Unipolar Signals.
µ
F
DS202F1 9
+5V
Analog
Supply
CS5525 CS5526
10
Ω
0.1 µF
213
CS5525
CS5526
CPD
8
VD+
XOUT
SCLK
SDO
DGNDNBV
XIN
CS
SDI
12
10
32.768 ~ 100kHz
9
18
11
17
14
VA+
20
VREF+
19
30mV
F.S.
+
3
16
15
7
6
4
1
VREFAIN+
AINAGND
A3
A2
A1
A0
5
0.1 µF
Optional
Clock
Source
Serial
Data
Interface
Figure 5. CS5525/26 Configured for Single Supply Bridge Measurement.
System Initialization
When powe r t o the CS5525/26 is ap pl ie d, they are
held in a reset cond ition until their 32 .768 kHz oscillators have started and their start-up counter-timer elapses. Due to the high Q of a 32.768 kHz
crystal, the oscillators take 400-600 ms to start. The
converter’s counter-timer counts no more than
1024 oscillator clock cycles to make sure the oscillator is fully stable. During this time-out period the
serial port logic is reset and the RV (Re set Valid)
bit in the configuration register is set. A reset can be
initiate d at an y tim e by wri ti ng a l og ic 1 t o the R S
(Reset System) bit in the configuration register.
This aut omatic all y sets th e RV bit u ntil th e RS b it
is writte n to lo gic 0, and the c on fig ura tion regi st er
is read. After a reset, the on-chip registers are initialized to the following s tates and the conv erters
are ready to perform conversion s.
Command Operation
The CS5525/26 include a microcontroller with five
registers used t o co ntr ol th e conve rter. Ea ch regi ster is 24-bits in length except the 8 -bit command
register (command, configuration, offset, gain, and
conversion data). After a system initialization or reset, the serial port is initialized to the command
mode and t he converter stays in thi s mode until a
valid 8-bit command is received (the first 8-bits
into the serial port). Table 1 lists all t h e va lid commands. Once a valid 8-bit command (a read or a
write comma nd word) is received and i nterpreted
by the comma nd register, the seria l port ent ers the
data mode. In data mode the next 24 serial clock
pulses shift data e it he r i nto or out of the se rial port
(72 serial clock pul ses a re needed if set- up re gi ster
is selected). See Table 2 for configuring the
CS5525/26.
configuration register: 000040(H)
offset register: 000000(H)
gain register: 800000(H)
10 DS202F1
CS5525 CS5526
Reading/Writing On-Chip Registers
The CS5525/26’s offset, gain, and configuration
registers are read/writable while the conversion
data register is read only.
CC, and PS/R bi ts must be logic 0 and the CB (MSB)
bit must be a logi c 1. The r egister to be written is selected with the RSB2-RSB0 bits of the command
word. Figure 6 illustrates the serial sequence necessary to write to, or read from the serial port.
To perform a read from a specific register, the R/W
bit of the command word must be a logic 1. The SC,
CC, and PS/R
bits must be logic 0 and the CB
(MSB) bit must be a logic 1. The register to be written is selected with the RSB2-RSB0 bits of the
command word.
If the Set -up R egist ers ar e ch osen wi th t he R SB2RSB0 bits, the re gisters are re ad or written in t he
following sequ ence: Offset, Gain and Config uration. Th is is a ccomp lish ed by follow ing o ne 8-b it
command word with three 2 4-bit data words for a
total of 72 dat a bits.
To perform a writ e to a specific registe r, the R/W
bit of the command word must be a lo gic 0. The SC,
Command Register
D7(MSB)D6D5D4D3D2D1D0
CB SC CC R/W RSB2 RSB1 RSB0 PS/R
BIT NAME VALUE FUNCTION
D7 Command Bit, CB 0
D6 Single Conversion, SC 0
D5 Continuous Conversions,
CC
D4 Read/Write, R/W 0
D3-D1 Register Select Bit,
RSB2-RSB0
D0 Power Save/Run, PS/R 0
000
001
010
011
100
101
110
111
Table 1. Command Set
1
1
0
1
1
1
Null command (no operation). All command bits, including
CB must be 0.
Logic 1 for executable commands.
Single Conversion not active.
Perform a conversion.
Continuous Conversions not active.
Perform conversions continuously.
Write to selected register.
Read from selected register.
Offset Register
Gain Register
Configuration Register
Conversion Data Register (read only)
Set-up Registers (Offset, Gain, Configuration)
Reserved
Reserved
Reserved
Run
Power Save
DS202F1 11
CS5525 CS5526
Confi
guration Register
D23(MSB) D22 D21 D20 D19 D1 8 D17 D16 D15 D14 D13 D12
A3 A2 A1 A0 NU CFS NU LPM WR2 WR1 WR0 U/B
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
G2 G1 G0 PD RS RV PF PSS DF CC2 CC1 CC0
BIT NAME VALUE FUNCTION
D23-D20 Latch Outputs, A3-A0 0000 R* L atch Output Pins A3-A0 mimic the D23-D20 Register bits.
D19 Not Used, NU 0 R Must always be logic 0.
D18 Chop Frequency Select,
CFS
D17 Not Used, NU 0 R Must always be logic 0.
D16 Low Power Mode, LPM 0
D15-D13 Word Rate, WR2-0
Note: For
XIN = 32.768kHz
D12 Unipolar/Bipolar, U/B 0
D11-D9 Gain Bits, G2-G0 000
D8 Pump Disable, PD 0
D7 Reset System, RS 0
D6 Reset Valid , RV 0
D5 Port Flag, PF 0
D4 Power Save Select, PSS 0
D3 Done Flag, DF 0
D2-D0 Ca libration Control Bits,
CC2-CC0
0
1
1
000
001
010
011
100
101
110
111
1
001
010
011
100
101
110/111
1
1
1R
1
1
1
000
001
010
011
100
101
110
111
R 256 Hz Amplifier chop frequency
32768 Hz Amplifier chop frequency
R Normal Mode
Reduced Power mode
R 15.0 Hz (2182 XIN cycles)
30.1 Hz (1090 XIN cycles)
60.0 Hz (546 XIN cycles)
123.2 Hz (266 XIN cycles)
168.9 Hz (194 XIN cycles)
202.3 Hz (162 XIN cycles)
3.76 Hz (8722 XIN cycles)
7.51 Hz (4362 XIN cycles)
R Bipolar Measurement mode
Unipolar Measurement mode
R 100 mV (assumes VREF = 2.5V)
55 mV
25 mV
1V
5.0 V
2.5 V
Not Used.
R Charge Pump Enabled
For PD = 1, the CPD pin goes to a Hi-Z output state.
R Normal Operation
Activate a Reset cycle. To return to Normal Operation write bit to zero.
No reset has occurred or bit has been cleared (read only).
Valid Reset has occurred. (Cleared when read.)
R Port Flag mode inactive
Port Flag mode active
R Standby Mode (Oscillator active, allows quick power-up)
Sleep Mode (Oscillator inactive)
R Done Flag bit is cleared (read only).
Calibration or Conversion cycle completed (read only).
R Normal Operation (no calibration)
Offset -- Self-Calibration
Gain -- Self-Calibration
Offset Self-Calibration followed by Gain Self-Calibration
Not used.
Offset -- System Calibration
Gain -- System Calibration
Not Used.
* R indicates the bit value after the part is reset
Table 2. Configuration Register
12 DS202F1
CS
SCLK
CS5525 CS5526
SDI
CS
SCLK
SDI
SDO
Command Time
8 SCLKs
Command Time
8 SCLKs
MSB
Write Cycle
MSB
Read Cycle
LSB
Data Time 24 SCLKs
(or 72 SCLKs for Set-up Registers)
LSB
Data Time 24 SCLKs
(or 72 SCLKs for Set-up Registers)
SCLK
SDI
t *
Command Time
8 SCLKs
SDO
* td = XIN/OWR clock cycles for each conversion except the
first conversion which will take XIN/OWR + 7 clock cycles
d
SDO Continuous Conversion Read (PF bit = 1)
8 SCLK s Clear SDO Flag
MSB
Data Time
24 SCLKs
XIN/OWR
Clock Cycles
LSB
Figure 6. Command and Data Word Timing.
DS202F1 13
CS5525 CS5526
Analog Input
Figure 7 illustr ates a blo ck diagr am of t he analog input signal path inside the CS5525/26. The front end
consists of a chopper-stabilized instrumentation amplifier with 20X gain and a programmable gain section. The instrumentation amplifie r is powered from
VA+ and from the NBV (Negative Bias Volt age) pin
allowing the CS5525/26 to be operated in either of
two analog input configurations. The NBV pin can
be biased to a negative voltage between -1.8 V and
-2.5 V, or tied to AGND. The choice of the operating
mode for the NBV voltage depends upon the input
signal and its common mode voltage.
For the 25 mV, 55 mV, and 100 mV input ranges, the
input signals to AIN+ and AIN- are amplified by the
20X instrumentation amplifier. For ground referenced signals with magnitudes less then 100 mV, the
NBV pin should be biased with -1.8 V to -2.5 V. If
NBV is tied between -1. 8 V and -2.5 V, the (Com mon Mode + Signal) input on AIN+ and AIN- must
stay between -0.150 V and 0.950 V to ensure proper operation. Alternatively, NBV can be tied to
AGND where the input (Common Mode + Signal)
on AIN+ and AIN- must stay b etween 1.85 V and
2.65 V to ensure tha t the ampl ifier ope rates prop erly.
For the 1 V, 2.5 V, and 5 V input ranges, the instrumentation amplifi er is bypassed and the input signals are directly connected to the Programmable
Gain block. With NBV tied between -1.8 V and
-2.5 V, the (Common Mode + Signal) input on
AIN+ and AIN- must stay between NBV and VA+.
Alternatively, NBV can be tied to AGND where
the input (Com mon Mode + Sig nal) on AIN+ and
AIN- pins can span the entire range between
AGND and VA+.
The CS5525/26 can accommodate full scale ranges
other than 25 mV, 55 mV, 100 mV, 1 V, 2.5 V and
5 V by performin g a syste m calibr ation wi thin the
limits specified. See the Calibration section fo r
more details. Another way to change the full scale
range is to increase or to decrease the voltage reference to ot her than 2.5 V. Se e the Vo ltage Refer-
ence sectio n for more detail s.
Three factor s set the op erating limits for t he input
span. They include: instrumentation amplifier satu-
ration, modulator 1’s density, and a lower reference
voltage. When the 25 mV, 55 mV or 100 mV range
is selected, the input signal (including the common
mode voltage and the amplifier offset voltage)
must not caus e the 20 X amp lifier to saturat e in ei ther its inp ut s tag e o r outpu t s tage . To pre vent sat uration the absolute voltages on AIN+ and AINmust stay within the limits specified (refer to the
‘Analog Input’ table on pag e 3). Addit ional ly, t he
differential output voltage of the amplifier must not
exceed 2.8 V. The equation
ABS(VIN + VOS) x 20 = 2.8 V
defines the diffe rential output li mit, where
VIN = (AIN+) - (AIN-)
is the differentia l input volt age and VOS is the absolute maximum offset voltage for the instrumentation amplifier (VOS will not exceed 40 mV). If the
VREF+
AIN+
AIN-
NBV
14 DS202F1
X20
Figure 7. Block Diagram of Analog Signal Path
Programmable
Gain
Differential 4th
order delta-
sigma modulator
VREF-
Digital Filter
CS5525 CS5526
F
Input Range
± 25 mV
± 55 mV
± 100 mV
± 1.0 V - 2.5V 2.5 ± 1.0 V ± 1.5 V
± 2.5 V - 2.5V 1.0 ± 2.5 V ± 5.0 V
± 5.0 V - 2.5V 0.5 ± 5.0 V 0V, VA+
Note: 1. The converter ’s actual input range, the delta-sigma’s nominal full scale input, and the delta-sigma’s
(1)
maximum full scale input all scale directly with the value of the voltage reference. The values in the
table assume a 2.5 V VREF voltage.
Table 3. Relationship between Full Scale Input, Gain Factors, and Internal Analog Signal Limitations
differential output voltage from the amplifier exceeds 2.8 V, the amplifier may saturate, which will
cause a measure ment error.
The input voltage into the modulator must not
cause the mo dulat or to exce ed a lo w of 20 perce nt
or a high of 80 percent 1’s density. The nominal full
scale input span of the modu lator (from 3 0 pe rcent
Max. Differential Output
20X Amplifier
(2)
2.8 V
(2)
2.8 V
(2)
2.8 V
VREF Gain Factor
2.5V 5 ± 0.5 V ± 0.75 V
2.5V 2.272727... ± 1.1 V ± 1.65 V
2.5V 1.25 ± 2.0 V ±3.0 V
Note: Residual nois e appear s in the conve rter’ s base band f or
output wor d rat es gr eater t han 60 Hz if CFS is logic 0. By s etting CFS to logic 1, the amplifier’s chop frequency chops at
32768 Hz eliminating the residual noise, but increasing the
current.
For physical inp ut capac itance see ‘Input Capac itance’ specification under ‘Analog Characteristics’ on page 3.
Note that C=48 pF is for i nput curr ent modeli ng only.
25mV, 55mV, and 100mV Ranges
∆-Σ Nominal
Differential Input
(1)
(1)
∆-Σ
Max. Input
to 70 percent 1’s density) is determined by the
VREF voltage divi de d by the Gain Factor. See Ta ble 3 to determine if the CS5525/26 are being used
properly. For example, in the 55 mV rang e to determine the nominal input voltage to the modulator,
divide VREF (2.5 V) by the Gain Factor (2.2727).
When a sma ller voltage referen ce is used, the re -
AIN
V ≤ 25mV
os
i = fV C
osn
CFS = 0 , f = 256 Hz
CFS = 1 , f = 32.768 kHz
C = 48p
sulting code widths are smaller causing the converter output codes to exhibit more changing codes
for a fixed amount of noi se. T able 3 i s based u pon
a VREF = 2.5 V. For other values of VREF, the values in Table 3 must be scale d a cc ordingly.
Figure’s 8 and 9 il lustrate the inp ut m odels f or t he
AIN and VREF pins. The dynamic input current for
each of the pins can be determined from the models
shown and is dependent upon the setting of the CFS
(Chop Frequency Select) bit. The effective input
AIN+
Figure 8. Input models for AIN+ and AIN- pins
1V, 2.5 V, and 5V Ranges
AIN-
i = [(V ) - (V )] fC
n
AIN+ AIN-
f = 32. 7 68 kH z
VREF+
VREF-
C = 32pF
C = 16pF
impedance for the AIN+ and AIN- pins remains
i = [(VREF+) - (VREF-)] fC
constant for the three low level measurement ranges (25 mV, 55 mV, and 100 mV). The input current
Figure 9. Input model for VREF+ and VREF- pins.
n
f = 32.768 kHz
is lowest w it h the CF S bit cleared to logic 0.
DS202F1 15
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