CIRRUS LOGIC CS5510, CS5511, CS5512, CS5513 Service Manual

CS5510/11/12/13

16-bit and 20-bit, 8-pin

Features

z Delta-sigma Analog-to-digital Converter

– Linearity Error: 0.0015% FS
– Noise-free Resolution: Up to 17 Bits

Differential Bipolar Analog Inputs

z

z V
z 50/60 Hz Simultaneous Rejection

z 16 to 326 Sps Output Word Rate
z On-chip Oscillator (CS5511/13)
z Power Supply Configurations:

z

Input Range from 250 mV to 5 V

REF

(CS5510/12)

– V+ = 5 V, V- = 0 V
– Multiple Dual-supply Arrangements

Low Power Consumption

– Normal Mode, 2.5 mW
– Sleep Mode, 10 µW

∆Σ

ADC

General Description

The CS5510/11/12/13 are low-cost, easy-to-use, ∆Σ an­alog-to-digital converters (ADCs) which use charge­balance techniques to achieve 16-bit (CS5510/11) and
20-bit (CS5512/13) performance. The ADCs are avail­able in a space-efficient, 8-pin SOIC package and are
optimized for measuring signals in weigh scale, process
control, and other industrial applications.

To accommodate these applications, the ADCs include
a fourth-order ∆Σ modulator and a digital filter. When
configured with an external master clock of 32.768 kHz,
the filter in the CS5510/12 provides better than 80 dB of
simultaneous 50 and 60 Hz line rejection, and outputs
conversion words at 53.5 Sps. The CS5511/13 include
an on-chip oscillator which eliminates the need for an ex­ternal clock source.

Low-power, flexible supply configurations, compact pi­nout, and ease of use make these products ideal
solutions for cost-conscience and space-constrained
applications.

Low-cost, Compact, 8-pin Package

z

z Lead-free Device Package Options

V+

AIN+

AIN-

VREF

1X

~0.8X

Differential

4th-order

Delta-sigma

Modulator

V-

ORDERING INFORMATION

See page 23.

Oscillator

(CS5511/13 only)

Digital Filter

Clock

Gen.

Output
Control

Logic

(CS5510/12 only)

CS

SDO

SCLK

http://www.cirrus.com

Copyright © Cirrus Logic, Inc. 2005

(All Rights Reserved)

AUG ‘05

DS337F3

TABLE OF CONTENTS

1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 4

ANALOG CHARACTERISTICS................................................................................................4

DIGITAL CHARACTERISTICS.................................................................................................5

DYNAMIC CHARACTERISTICS .............................................................................................. 6

ABSOLUTE MAXIMUM RATINGS ...........................................................................................6

SWITCHING CHARACTERISTICS - CS5510/12 .....................................................................7

SWITCHING CHARACTERISTICS - CS5511/13 .....................................................................8

2. GENERAL DESCRIPTION ..................................................................................................... 10

2.1 Analog Input ........ .......................................... ...................................................................10

2.1.1 Analog Input Model ................... .... ... ... ... .... .......................................... ... ... .........10

2.2 Voltage Reference Input .................................................................................................. 10

2.2.1 Voltage Reference Input Model ...........................................................................11

2.3 Power Supply Arrangements ........................... ... .... ... ... ... .... ... ... ... ... ................................ 11

2.3.1 Digital Logic Levels .......... ... ... ... .......................................................................... 11

2.4 Clock Generator .. ... ... .......................................... .............................................................14

2.4.1 External Clock Source for CS5510/12 .................................... ............................ 14

2.4.2 Internal Oscillator for CS5511/13 ........................................................................14

2.5 Performing Conversions ............................................ ... ... .... ......................................... ... 15

2.5.1 Reading Conversions - CS5510/12 .....................................................................16

2.5.2 Reading Conversions - CS5511/13 .....................................................................16

2.5.3 Output Coding ............................................... ... ... .... ... ... ...................................... 17

2.5.4 Digital Filter ......... ... ....................................... ... ... .... ... ... ... ................................... 18

2.5.5 Multiplexed Applications ...................................................................................... 19

2.6 Digital Off-chip System Calibration .................................................................................. 20

2.7 Power Consumption, Sleep and Reset ............................................................................ 20

2.8 PCB Layout ......... .......................................... ...................................................................20

3. PIN DESCRIPTIONS ..............................................................................................................21

4. SPECIFICATION DEFINITIONS .............................................................................................22

5. ORDERING INFORMATION ................................................................................................... 23

6. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION ............................ 23

7. REVISION HISTORY .............................................................................................................23

8. PACKAGE DIMENSIONS ....................................................................................................... 24

CS5510/11/12/13

Contacting Cirrus Logic Support

For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find the one nearest to you go to www.cirrus.com

IMPORTANT NOTICE
Cirrus Logic, Inc. and it s subs i dia ri e s (“Ci r ru s”) be li eve tha t t he in for mat i o n cont ai n ed in t hi s document i s acc ur at e and re l i abl e . Ho wev er , th e in fo rmation is subject

to change without noti ce and is provi ded “AS I S” with out warran ty of any kind ( express or implied ). Cust omers are a dvised to obtain the latest version of relevant
information to verify, before placing orders, tha t inform atio n bei ng relied on is curr ent and com plete. Al l prod ucts are sold s ubject to the ter ms and co nditio ns of sale
supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus
for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third
parties. This document is the property of Ci rrus and by furnishing this information, Cirrus gr ants no license, express or implied under any paten ts, mask work rights,
copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives con­sent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent
does not extend to other copying such as copying for ge neral distribution, advertising or promotional purposes, or for creating any work for res al e.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP­ERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE
IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DE­VICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UND ERSTOOD
TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO AN Y CI RR US PRODUCT THAT IS USED
IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICA­TIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER
AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH
THESE USES.

Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks
or service marks of their respective owners.

2 DS337F3

LIST OF FIGURES

Figure 1. SDO Read Timing CS5510/12 (Not to Scale).................................................................. 9

Figure 2. SDO Read Timing CS5511/13 (Not to Scale).................................................................. 9

Figure 3. Input models for AIN+ and AIN- pins. ............................................................................ 10

Figure 4. CS5512/13 Measured Noise-Free Bits vs. VREF.......................................................... 11

Figure 5. Input model for VREF pin............................................................................................... 11

Figure 6. CS5510/11/12/13 Configured with a +5.0 V Analog Supply.......................................... 12

Figure 7. CS5510/11/12/13 Configured with ±2.5 V Analog Supplies..................................... ... ... 12

Figure 8. CS5510/11/12/13 Configured with V+ = +3.3 V and V- = -1.7 V;

or V+ = +3.0 V and V- = -2.0 V. .................................................................................... 13

Figure 9. CS

Figure 10. SDO Digital Output Levels........................................................................................... 14

Figure 11. Serial Port Output Drive Logic. .................................................................................... 14

Figure 12. External (CMOS Compatible) Clock Source................................................................ 15

Figure 13. Using a Microcontroller as a Clock Source............................................ ... .... ... ............ 15

Figure 14. Typical Linearity Error for CS5510............................................................................... 15

Figure 15. Typical Linearity Error for CS5512............................................................................... 15

Figure 16. Data Word Timing for the CS5510............................................................................... 16

Figure 17. Data Word Timing for the CS5511............................................................................... 17

Figure 18. Data Word Timing for the CS5512............................................................................... 17

Figure 19. Data Word Timing for the CS5513............................................................................... 17

Figure 20. Digital Filter Response................................................................................................. 19

and SCLK Digital Input Levels................................................................................. 14

CS5510/11/12/13

LIST OF TABLES

Table 1. CS5512/13 Output Conversion Data Register Description (Flags + 20 bits).................. 18

Table 2. CS5510/11 Output Conversion Data Register Description (Flags + 16 bits).................. 18

Table 3. CS5510/11/12/13 Output Coding.............. ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ......... 18

Table 4. Digital Filter Response at 32.768 kHz.................... ... ... .......................................... ... ... ... 19

Table 5. Device Ordering Information ........................................................................................... 23

DS337F3 3

CS5510/11/12/13

1. CHARACTERISTICS AND SPECIFICATIONS

ANALOG CHARACTERISTICS

(TA = 25° C; V+ = 5 V ±5%; V- = 0 V; VREF = 2.5 V (relative to V-);
CS5510/12, SCLK = 32.768 kHz; CS5511/13, f
CS5510/12; OWR = 107 Sps ± 50% for CS5511/13)
(See Note 1.)

Accuracy

Linearity Error (CS5510/11) - ±0.0015 ±0.003 % FS
Linearity Error (CS5512/13) - ±0.0007 ±0.0015 % FS
No Missing Codes (CS5510/11) 16 - - Bits
No Missing Codes (CS5512/13) 20 - - Bits
Bipolar Offset (CS5510/11) (Note 2) - ±3 ±7 LSB
Bipolar Offset (CS5512/13) (Note 2) - ±40 ±100 LSB
Offset Drift Over Temperature (Notes 2 and 3) - 60 - nV/°C
Gain Drift Over Temperature (Note 3) - 1 - ppm/°C

Analog Input

Common Mode + Signal on AIN+ or AIN-

Input Range (Bipolar) |(AIN+ - AIN-)/(VREF - V-)| 72 80 88 % VREF
Common Mode Rejection dc

Input Capacitance - 12 - pF
CVF Current AIN+, AIN- (Note 6) - 10 - nA

Parameter Min Typ Max Unit

Dual Supply V- - V+ V

50, 60Hz (CS5510/12)

= 64 kHz ±32 kHz; OWR (Output Word Rate) = 53.5 Sps for

osc

-

-

120
120

-

-

16
20

dB
dB

Typical Noise (Notes 4, 5 and 7)

Output Word Rate (Hz) -3 dB Filter Frequency (Hz) Noise (µV RMS)

53.5 12.5 7.5

Notes: 1. Specifications guaranteed by design, characterization, and/or test.

2. Specif ica tio n applie s to th e de vice on ly and does not include any effects by external parasitic

thermocouples.

3. Drift over specified temperature range after power-up at 25° C.

4. Wideband noise aliased into the baseband. Referred to the input. Typical values shown for 25° C.

5. For peak-to-peak noise multiply by 6.6.

6. See the section of the data sheet which discusses Analog Input Models.

7. For CS5511/13, OWR = 107 Sps ± 50%.

Specifications are subject to change without notice.

4 DS337F3

CS5510/11/12/13

ANALOG CHARACTERISTICS (Continued)

Parameter Min Typ Max Unit

Voltage Reference Input

Range {(VREF) - (V-)} (Note 8) 0.250 2.5 (V+) - (V-) V
Input Capacitance - 7 - pF
CVF current - 6 - nA

Power Supplies

Supply Voltages {(V+) - (V-)} 4.75 5 5.25 V
DC Power Supply Currents (Note 9)

I

V+

CS5510

CS5511
CS5512
CS5513

I

V-

CS5510

CS5511
CS5512
CS5513

Power Consumption (Note 10)
CS5510

CS5511
CS5512
CS5513

Sleep (Note 11)
Power Supply Rejection dc Positive Supply

dc Negative Supply

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

275
290
360
385
275
290
360
385

1.4

1.5

1.8

1.9
10

85
85

360
380
470
500
360
380
470
500

1.9

2.0

2.5

2.7

-

-

-

µA
µA
µA
µA
µA
µA
µA
µA

mW
mW
mW
mW

µW

dB
dB

Notes: 8. VREF is referenced to V- and must be less than or equal to V+.

9. Due to curren t th ro ug h th e CS

pin, IV+ and IV- may not always be the same value.

10. All outputs unloaded. All inputs CMOS levels (> (V+ - 0.6 V) or < (V- + 0.6 V)).

11. CS must be inactive (logic high) during sleep to meet this power specification.

DIGITAL CHARACTERISTICS

(TA = 25° C; V+ = 5 V ±5 %; V- = 0 V) (See Notes 1 and 12.)

Parameter Symbol Min Typ Max Unit

High-Level Input Voltage:
Low-Level Input Voltage: (Note 13)

Input Current: (Note 14)
High-Level Output Voltage: SDO, I

Low-Level Output Voltage: (Note 14) SDO, I
Input Leakage Current SCLK I

3-State Leakage Current SCLK I

Notes: 12. All measurements performed under static conditions.

13. V

14. The CS

is 0.5 (V+ - V-) + 0.6 V + V-.

L1

signal provides the sink current path for the SDO pin when CS is low. The external drive logic

, therefore, must be able to handle the logic-low current drive levels for all devices attached to

to CS
SDO. The voltage specified for SDO is relative to CS
Figure 11 for more details.

CS and SCLK V

CS

SCLK

CS I

= 5.0mA V

source

= 1.0mA V

sink

IH

CS

Low

V

IL

CS

OH
OL
in

OZ

. See Section 2.3.1, “Digital Logic Levels” and

Low

V+ - 0.45 - - V

-

-

- -1.0mA

-

-

V

L1

V

L1

V
V

(V+) - 0.6 - - V

--(CS

) + 0.6 V

Low

- ±0.015 ±10 µA

-- ±10µA

DS337F3 5

DYNAMIC CHARACTERISTICS

Parameter Symbol Ratio Units

Modulator Sampling Frequency CS5510/12

CS5511/13

Output Word Rate CS5510/12

CS5511/13

Filter Settling Time to 1/2 LSB (Full Scale Step) t

ABSOLUTE MAXIMUM RATINGS

(V- = 0 V) (See Note 15.)

Parameter Symbol Min Typ Max Unit

f

s

f

s

OWR
OWR

s

CS5510/11/12/13

SCLK/4

f

/4

osc

SCLK/612

f

/612

osc

4/OWR s

Hz
Hz

Sps
Sps

Notes: 15. All voltages with respect to V-.

16. V+ and V- must satisfy 0.0V ≤ {(V+) - (V-)} ≤ +6.0 V.

17. Applies to all pins including continuous overvoltage conditions at the analog input (AIN) pins.

18. Transient current of up to 100 mA will not cause SCR latch-up. Maximum input current for a power
supply pin is ±50 mA.

19. Total power dissipation, including all input currents and output currents.

WARNING: Operation at or beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes.

6 DS337F3

CS5510/11/12/13

SWITCHING CHARACTERISTICS - CS5510/12

(TA = 25° C; V+ = 5 V ±5%; V- = 0 V; Input Levels: Logic 0 = 0 V, Logic 1 = V+; CL = 50 pF)

Parameter Symbol Min Typ Max Unit

Master Clock Timing

Master Clock Frequency (CS5510) (Note 20) SCLK 10 32.768 130 kHz
Master Clock Frequency (CS5512) (Note 20) SCLK 10 32.768 200 kHz
Master Clock Duty Cycle 40 - 60 %
Rise Times (Note 21)

CSB

SCLK

SDO

Fall Times (Note 21)

CSB

SCLK

SDO

Serial Port Timing

Serial Clock Frequency (CS5510) (Note 22) SCLK 10 32.768 130 kHz
Serial Clock Frequency (CS5512) (Note 22) SCLK 10 32.768 200 kHz
SCLK High to Enter Sleep (Note 22) t
SCLK Low to Exit Sleep (Note 22) t
Serial Clock Pulse Width High

Pulse Width Low

SDO Read Timing

CS to Data Valid

SCLK Falling to New Data Bit t

CS Rising to SDO Hi-Z
CS Falling to SCLK Rising

t

rise

t

fall

SLP

WAKE

t

1

t

2

t

3
4

t

5

t

11

-

-

-

-

-

-

50

50

-

-

-

-

1.0
10

-

1.0
10

-

µs
µs
ns

µs
µs
ns

200 - 2000 µs

10 - - µs

2
2

-

-

60
60

µs
µs

--150ns

--150ns

--150ns

200 - - ns

Notes: 20. Device parameters are specified with 32.768 kHz clock; however, clocks up to 130 kHz (CS5510) or

200 kHz (CS5512) can be used for increased throughput. Higher clock rates will result in degraded
linearity specifications, as shown in Figures 14 and 15.

21. Specified using 10% and 90% points on waveform of interest. Output loaded with 50 pF.

22. On the CS5510/12, the serial clock input (SCLK) provides the master clock to operate the converter as
well as the serial data clock used to read conversion data. If SCLK is held high (logic 1) for t
the CS5510/12 enters sleep. To exit from sleep mode, SCLK must be held low (logic 0) for t

or longer,

SLP

WAKE

or

longer.

DS337F3 7

CS5510/11/12/13

SWITCHING CHARACTERISTICS - CS5511/13

(TA = 25° C; V+ = 5 V ±5%; V- = 0 V; Input Levels: Logic 0 = 0 V, Logic 1 = V+; CL = 50 pF)

Parameter Symbol Min Typ Max Unit

Internal Oscillator Timing

Internal Oscillator Frequency (Note 23) f

osc

Internal Oscillator Drift Over Temperature - - -0.02 - %/°C

Serial Port Timing

Serial Clock Frequency (Note 24) SCLK - - 2 MHz
SCLK High to Enter Sleep (Notes 24 and 25) t
SCLK Low to Exit Sleep (Notes 24 and 25) t
Rise Times (Note 26)

SLP

WAKE

t

rise

CSB

SCLK

SDO

Fall Times (Note 26)

t

fall

CSB

SCLK

SDO

Serial Clock Pulse Width High

Pulse Width Low

t

6

t

7

SDO Read Timing

CS to Data Valid

SCLK Falling to New Data Bit t

CS Rising to SDO Hi-Z
CS Falling to SCLK Rising

t

8
9

t

10

t

11

32 64 100 kHz

200 - 2000 µs

10 - - µs

-

-

-

-

-

-

200
200

50

50

-

-

-

-

-

-

1.0
10

-

1.0
10

-

-

-

µs
µs
ns

µs
µs
ns

ns
ns

--150ns

--150ns

--150ns

200 - - ns

Notes: 23. The internal oscillator in the CS5511/13 provides the master clock for performing conversions. Data is

retrieved from the serial port using the SCLK input pin.

24. The minimum SCLK rate for the CS5511/13 assumes that SCLK is logic 0 when idle. When data is being
read from the ADC, SCLK must be burst at a minimum rate of 10 kHz and with a minimum of a 10
percent duty cycle. Rates slower than this can potentially put the ADC into sleep as the sleep mode is
entered after SCLK is logic 1 for t

SLP

time.

25. On the CS5511/13, the serial clock (SCLK) is used to transfer data from the CS5511 /13. If SCLK is held
high (logic 1) for t
be held low (logic 0) for t

or longer, the CS5511/13 enters sleep mode. To exit from sleep mode, SCLK must

SLP

WAKE

or longer.

26. Specified using 10% and 90% points on waveform of interest. Output loaded with 50 pF.

8 DS337F3