Cirrus Logic CS5504-BS, CS5504-BP Datasheet

Low Power, 20-Bit A/D Converter

CS5504

Features

l

Delta-Sigma A/D Converter

- 20-bit No Missing Codes

- Linearity Error: ±0.0007%FS

l

2 Differential Inputs

- Pin Selectable Unipolar/Bipolar Ranges

- Common Mode Rejection

105 dB @ dc
120 dB @ 50, 60 Hz

l

Either 5V or 3.3V Digital Interface

l

On-chip Self-Calibration Circuitry

l

Output Update Rates up to 200/second

l

Low Power Consumption: 4.4 mW

I

Description

The CS5504 is a 2-channel, fully differential 20-bit, seri­al-output CMOS A/D converter. The CS5504 uses
charge-balanced (delta-sigma) techniques to provide a
low cost, high resolution measurement at output word
rates up to 200 samples per second.

The on-chip digital filter offers superior line rejection at
50 Hz and 60 Hz when the device is operated from a

32.768 kHz clock (outpu t word rate = 20 Hz.).
The CS5504 has on-chip self-calibration circuitry which

can be initiated at any time or temperature to ensure
minimum offset and full-scale errors.

Low power, high resolution and small package size
make the CS5504 an ideal solution for loop-powered
transmitters, panel meters, weigh scales and battery­powered instrument s.

ORDERING INFORMATION

CS5504-BP -40° to +85° C 20-pin Plastic DIP
CS5504-BS -40° to +85° C 20-pin SOIC

AIN1+

AIN1-

AIN2+

AIN2-

A0

VREF+ VREF- DGND VD+

12 13 16

8

10

9

11

1

MUX

4th-Order

Delta-Sigma

Modulator

Calibration SRAM

VA+

14

Digital

Filter

VA-

15

17

Serial

Interface

Logic

Calibration µC

OSC

35

CONV XIN

XOUT

2

CS

18

SCLK

19

SDATA

20

DRDY

4

CAL

7

BP/UP

6

Cirrus Logic, Inc.
Crystal Semiconductor Products Division

P.O. Box 17847, Austin, Texas 78760
[phone] FAX: [phone]
http://www.crystal.com

Copyright  Cirrus Logic, I nc. 1997

(All Rights Reserv ed)

MAR ‘95

DS126F1

1

CS5504

ANALOG CHARACTERISTICS

3.3V ± 5%; VREF+ = 2.5V, VREF- = 0V; f

(TA = T

= 32.768kHz; Bipolar Mode; R

CLK

MIN

to T

; VA+ = 5V ± 10%; VA- = -5V ± 10%; VD+ =

MAX

= 1kΩ with a 10nF to GND

source

at AIN.) (Notes 1, 2)

Parameter* Min Typ Max Units

Specified Temperature Range -40 to +85 °C

Accuracy

Linearity Error - 0.0007 0.0015

±

%FS
Differential Nonlinearity (No Missing Codes) 20 - - Bits
Full Scale Error (Note 3) -

Full Scale Drift (Note 4) ­Unipolar Offset (Note 3) ­Unipolar Offset Drift (Note 4) ­Bipolar Offset (Note 3) ­Bipolar Offset Drift (Note 4) -

±

4

±

8

±

8

±

8

±

4

±

4

±

32

-LSB

±

32

-LSB

±

16

-LSB

LSB

LSB

LSB

Noise (Referred to Output) - 2.6 - LS B

Analog Input

Analog Input Range: Unipolar (Note 5)

Bipolar

Common Mode Rejection: dc

50, 60- Hz (Note 2)

-

-

-

120

0 to +2.5

±

2.5

105

-

-

-

-

-

dB

dB
Off Channel Isolation - 120 - dB
Input Capacitance - 15 - pF
DC Bias Current (Note 1) - 5 - nA

Power Supplies

DC Power Supply Currents: I

Total

I

Analog

I

Digital

-

-

-

465
425

40

600

-

-

µ

µ

µ

Power Dissipation (Note 6) - 4.4 6.0 mW
Power Supply Rejection - 80 - dB

Notes: 1. Both source resistance and shunt capacitance are critical in determining the CS5504’s source

impedance requirements. Refer to the text s ection

Analog Input Impedance Considerations

.

2. Specifications guaranteed by design, characterization and/or test.

3. Applies after cali bration at the temperature of interest.

4. Total drift over the specified temperature range since calibration at power-up at 25 °C

5. Common mode voltage may be at any value as long as AIN+ and AIN- remain within the VA+ and
VA- supply voltages.

6. All outputs unloaded. All inputs CMOS levels.

rms

V
V

A
A
A

* Refer to the Specification Definitions immediately following the Pin Description Section.

Specifications are subject to change without notice.

2 DS126F1

DYNAMIC CHARACTERISTICS

Parameter Symbol Ratio Units

CS5504

Modulator Sampling Frequency f
Output Update Rate (CONV = 1) f
Filter Corner Frequency f
Settling Time to 1/2 LSB (FS Step) t

5V DIGITAL CHARACTERISTICS

(TA = T

MIN

to T

; VA+, VD+ = 5V ± 10%; VA- = -5V ± 10%;

MAX

DGND = 0.) (Notes 2, 7)

Parameter Symbol Min Typ Max Units

High-Level Input Voltage: XIN

All Pins Except XIN

Low-Level Input Voltage: XIN

All Pins Except XIN
High-Level Output Voltage (Note 8) V
Low-Level Output Voltage I

= 1.6 mA V

out

Input Leakage Current I
3-State Leakage Current I
Digital Output Pin Capacitance C

V

IH

V

IH

V

IL

V

IL

OH

OL
in

OZ

out

Notes: 7. All measurements are performed under static conditions.

= -100 µA. This guarantees the ability to drive one TTL load. (VOH = 2.4V @ I

8. I

out

f

s

out

-3dB
s

3.5

2.0

-

-

/2 Hz

clk

f

/1622 Hz

clk

f

/1928 Hz

clk

1/f

out

-

-

-

-

-

-

1.5

0.8

(VD+)-1.0 - - V

--0.4V

-

--

±

1

±

10

±10µ

-9-pF

= -40 µA).

out

s

V
V

V
V

µ

A
A

3.3V DIGITAL CHARACTERISTICS

(TA = T

MIN

to T

; VA+ = 5V ± 10%; VD+ = 3.3V ± 5%;

MAX

VA- = -5V ±10%; GND = 0V.) (Notes 2, 7)

Parameter Symbol Min Typ Max Units

High-Level Input Voltage: XIN

All Pins Except XIN

Low-Level Input Voltage: XIN

All Pins Except XIN
High-Level Output Voltage I
Low-Level Output Voltage I

= -400 µA

out

= 400 µA

out

Input Leakage Current I
3-State Leakage Current I
Digital Output Pin Capacitance C

V

IH

V

IH

V

IL

V

IL

V

OH

V

OL
in

OZ

out

0.7VD+

0.6VD+

-

-

-

-

-

-

-

-

0.3VD+

0.16VD+VV

V
V

(VD+)-0.3 - - V

--0.3V

-

--

±1 ±10 µA

±10 µA

-9-pF

DS126F1 3

CS5504

5V SWITCHING CHARACTERISTICS

VA- = -5V ± 10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; C

(TA = T

to T

MIN

= 50 pF.) (Note 2)

L

; VA+, VD+ = 5V ± 10%;

MAX

Parameter Symbol Min Typ Max Units

Master Clock Frequency Internal Oscillator

External Clock

XIN

f

clk

30.0
30

32.768

-

53.0
330

Master Clock Duty Cycle 40 - 60 %
Rise Times: Any Digital Input (Note 9)

Any Digital Output

Fall Times: Any Digital Input (Note 9)

Any Digital Output

t

rise

t

fall

-

-

-

-

50

20

-

1.0

-

-

1.0

-

Start-Up

Power-On Reset Period (Note 10) t
Oscillator Start-up Time XTAL = 32.768 kHz (Note 11) t
Wake-up Period (Note 12) t

res

osu

wup

-10-ms

- 500 - ms

- 1800/f

clk

-s

Calibration

CONV Pulse Width (CAL=1) (Note 13) t
CONV and CAL High to Start of Calibration t
Start of Calibration to End of Calibration t

ccw

scl
cal

100 - - ns

--2/f

- 3246/f

clk

+200 ns

clk

-s

Conversion

Set Up Time A0 to CONV High t
Hold Time A0 after CONV High t
CONV Pulse Width t
CONV High to Start of Conversion t
Set Up Time BP/UP stable prior to DRDY falling t
Hold Time BP/UP stable after DRDY falls t
Start of Conversion to End of Conversion (Note 14) t

sac
hca

cpw

scn
bus

buh

con

50 - - ns
100 - - ns
100 - - ns

--2/f

82/f

clk

--s

+200 ns

clk

0--ns

- 1624/f

clk

-s

Notes: 9. Specified using 10% and 90% points on waveform of interest.

10. An internal power-on-reset is activated whenever power is applied to the device.

11. Oscillator start-up time varies with the crystal parameters. This specification does not apply when
using an external clock source.

12. The wake-up period begins onc e the oscillator starts ; or when using an external f

, after the

clk

power-on reset time elapses.

13. Calibration can also be initiated by pulsi ng CAL high while CONV =1.

14. Conversion time will be 1622/f

if CONV remains high continuous ly.

clk

kHz
kHz

µ

s

ns

µ

s

ns

4 DS126F1

CS5504

3.3V SWITCHING CHARACTERISTICS

5%; VA- = -5V ± 10%; Input Levels: Logic 0 = 0V, Logic 1 = V D+; C

(TA = T

MIN

to T

; VA+ = 5V ± 10%; VD+ = 3.3V

MAX

= 50 pF.) (Note 2)

L

Parameter Symbol Min Typ Max Units

Master Clock Frequency Internal Oscillator

External Clock

XIN

f

clk

30.0
30

32.768

-

53.0
330

Master Clock Duty Cycle 40 - 60 %
Rise Times: Any Digital Input (Note 9)

Any Digital Output

Fall Times: Any Digital Input (Note 9)

Any Digital Output

t

rise

t

fall

-

-

-

-

50

20

-

1.0

-

-

1.0

-

Start-Up

Power-On Reset Period (Note 10) t
Oscillator Start-up Time XTAL = 32.768 kHz (Note 11) t
Wake-up Period (Note 12) t

res

osu

wup

-10-ms

- 500 - ms

- 1800/f

clk

-s

Calibration

CONV Pulse Width (CAL=1) (Note 13) t
CONV and CAL High to Start of Calibration t
Start of Calibration to End of Calibration t

ccw

scl
cal

100 - - ns

--2/f

- 3246/f

clk

+200 ns

clk

-s

Conversion

Set Up Time A0 to CONV High t
Hold Time A0 after CONV High t
CONV Pulse Widh t
CONV High to Start of Conversion t
Set Up Time BP/UP stable prior to DRDY falling t
Hold Time BP/UP stable after DRDY falls t
Start of Conversion to End of Conversion (Note 14) t

sac
hca

cpw

scn
bus

buh

con

50 - - ns
100 - - ns
100 - - ns

--2/f

82/f

clk

--s

+200 ns

clk

0--ns

- 1624/f

clk

-s

kHz
kHz

µ

s

ns

µ

s

ns

±

DS126F1 5

XIN

XIN/2

CAL

CONV

STATE

t

ccw

t

scl

t

cal

Calibration StandbyStandby

Figure 1. Calibration Timing (Not to Scale)

CS5504

XIN

XIN/2

A0

t

sac

t

hca

CONV

t

DRDY

cpw

BP/UP

t

STATE

t

scn

t

con

bus

Conversion StandbyStandby

t

buh

Figure 2. Conversion Timing (Not to Scale)

6 DS126F1

CS5504

5V SWITCHING CHARACTERISTICS

(TA = T

MIN

VA- = -5V ± 10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; C

Parameter Symbol Min Typ Max Units

Serial Clock f
Serial Clock Pulse Width High

Pulse Width Low
Access Time: CS Low to data valid (Note 15) t
Maximum Delay Time: (Note 16)

SCLK falling to new SDATA bit t

Output Float Delay: CS high to output Hi-Z (Note 17)

SCLK falling to Hi-Z

Notes: 15. If

CS is activated asynchronously to DRDY, CS will not be recognized if it occurs when DRDY is high
for 2 clock cycles. The propagation delay time may be as great as 2 f
guarantee proper clocking of SDATA when usi ng asynchronous
sooner than 2/f

+ 200 ns after CS goes low.

clk

16. SDATA transitions on the falling edge of S CLK. Note that a rising SCLK must occur to enable the
serial port shifting mechanism before falli ng edges can be recognized.

CS is returned high before all data bits are output, the SDATA output will complete the current data

17. If
bit and then go to high impedance.

to T

= 50 pF.) (Note 2)

L

sclk

t

ph

t

pl

csd

dd

t

fd1

t

fd2

; VA+, VD+ = 5V ± 10%;

MAX

0-2.5MHz

200
200

- 60 200 ns

- 150 310 ns

-

-

clk

CS, SCLK should not be taken hi gh

-

-

60

160

-

-

150
300

cycles plus 200 ns. To

ns
ns

ns
ns

3.3V SWITCHING CHARACTERISTICS

(TA = T

MIN

to T

5%; VA- = -5V ± 10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; C

Parameter Symbol Min Typ Max Units

Serial Clock f
Serial Clock Pulse Width High

Pulse Width Low

Access Time: CS Low to data valid (Note 15) t

sclk

t

ph

t

pl

csd

Maximum Delay Time: (Note 16)

SCLK falling to new SDATA bit t

Output Float Delay: CS high to output Hi-Z (Note 17)

SCLK falling to Hi-Z

t
t

dd

fd1
fd2

; VA+ = 5V ± 10%; VD+ = 3.3V

MAX

= 50 pF.) (Note 2)

L

0 - 1.25 MHz

200
200

- 100 200 ns

- 400 600 ns

-

-

-

-

70

320

-

-

150
500

±

ns
ns

ns
ns

DS126F1 7

DRDY

CS

SCLK(i)

t

csd

CS5504

t

fd1

MSB-1MSB MSB-2SDATA(o) Hi-Z

t

dd

DRDY

CS

SDATA(o) Hi-Z

SCLK(i)

t

csd

MSB-1MSB LSB+2 LSB+1 LSB

t

dd

Figure 3. Timing Relationships; Serial Da ta Rea d (Not to Scale)

t

ph

t

pl

t

fd2

8 DS126F1

RECOMMENDED OPERATING CONDITIONS (DGND = 0V) (Note 18)

Parameter Symbol Min Typ Max Units

DC Power Supplies:

Positive Digital
(VA+) - (VA-)
Positive Analog
Negative Analog

Analog Reference Voltage

(Note 19)

VD+

V

diff

VA+

VA-

(VREF+)-

(VREF-)

Analog Input Voltage: (Note 20)

Unipolar
Bipolar

VAIN
VAIN0-((VREF+)-(VREF-))

Notes: 18. All vol tages with respect to ground.

19. The CS5504 can be operated wi th a reference voltage as low as 100 mV; but wi th a
corresponding reduction in noise-free resolution. The common mode voltage of the voltage reference
may be any value as long as +VREF and -VREF remain inside the supply values of VA+ and VA-.

20. The CS5504 can accept input voltages up to the analog supplies (VA+ and VA-). In unipolar mode

the CS5504 will output all 1’s if the dc input magnitude ( (AIN+)-(AIN-)) exceeds ((VREF+) -(VREF-))
and will output all 0’s if the input becomes more negativ e than 0 Volts. In bi polar mode the CS5504
will output all 1’s if the dc input magnitude ((AIN+)-(AIN-)) exceeds ((VREF+)-(VREF-)) and will output
all 0’s if the input becomes more negative in magnitude than -((VREF+)-(VREF-)).

3.15

4.5

4.5
0

5.0
10

5.0

-5.0

1.0 2.5 3.6 V

-

-

(VREF+)-(VREF-)
(VREF+)-(VREF-)VV

5.5
11
11

-5.5

CS5504

V
V
V
V

ABSOLUTE MAXIMUM RATINGS*

Parameter Symbol Min Typ Max Units

DC Power Supplies: Digital G round (Note 21)

Positive Digital (Note 22)
Positive Analog

Negative Analog
Input Current, Any Pin Except Supplies (Notes 23, 24) I
Output Current I

Power Dissipation (Total) (Note 25) - - 500 mW
Analog Input Voltage AIN and VREF pins V
Digital Input Voltage V
Ambient Operating Temperature T
Storage Temperature T

Notes: 21. No pin s hould go more positive than (VA+)+0.3V.

22. VD+ must always be less than (VA+) +0.3V, and can never exceed +6.0 V.

23. Applies to all pins including continuous overvoltage conditions at the analog input (AIN) pin.

24. Transient currents of up to 100mA will not caus e SCR latch-up. Maximum input current for a power
supply pin is ± 50 mA.

25. Total power dissipation, i ncluding all input c urrents and output currents.

* WARNING: Operation at or beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes.

DGND

VD+
VA+

VA-

in

out

INA
IND

A

stg

-0.3

-0.3

-0.3

+0.3

--

--

-

-

-

-

(VD+)-0.3

6.0 or VA+
12

-6.0

±

10

±

25

mA
mA

(VA-)-0.3 - (VA+)+0 .3 V

-0.3 - (VD+)+0.3 V

-40 - 85 °C

-65 - 150 °C

V
V
V
V

DS126F1 9

CS5504

GENERAL DESCRIPTION

The CS5504 is a low power, 20-bit, monolithic
CMOS A/D converter designed specifically for
measurement of dc signals. The CS5504 in­cludes a delta-sigma charge-balance converter, a
voltage reference, a calibration micro controller
with SRAM, a digital filter a nd a seria l interface.

The CS5504 is optimized to operate from a

32.768 kHz crystal but can be driven by an ex­ternal clock whose frequency is between 30 kHz
and 330 kHz. When the digital filter is operated
with a 32.768 kHz clock, the filter has zeros pre­cisely at 50 and 60 Hz line frequencies and
multiples thereof.

The CS5504 uses a "start convert" command to
latch the input channel selection and to start a
convolution cycle on the digital filter. Once the
filter cycle is completed, the output port is up­dated. When operated with a 32.768 kHz clock
the ADC converts and updates its output port at
20 samples/sec. The output port operates in a
synchronous externally-clocked interface format.

tion of this command will not occur until the
complete wake-up period elapses. If no com­mand is given, the device enters the standby
state.

Calibration

After the initial application of power, the
CS5504 must enter the calibration state prior to
performing accurate conversions. During calibra­tion, the chip executes a two-step process. The
device first performs an offset calibration and
then follows this with a gain calibration. The
two calibration steps determine the zero refer­ence point and the full scale reference point of

the converter’s transfer function. From these
points it calibrates the zero point and a gain
slope to be used to properly scale the output
digital codes when doing conversions.

The calibration state is entered whenever the
CAL and CONV pins are high at the same time.
The state of the CAL and CONV pins at power­on are recognized as commands, but will not be
executed until the end of the 1800 clock cycle
wake-up period.

THEORY OF OPERATION

If CAL and CONV become active (high) during
the 1800 clock cycle wake-up time, the con-

Basic Converter Operation

verter will wait until the wake-up period elapses
before executing the calibration. If the wake-up

The CS5504 A/D converter has three operating
states. These are stand-by, calibration, and con­version. When power is first applied, an internal
power-on reset delay of about 10 ms resets all of
the logic in the device. The oscillator must then
begin oscillating before the device can be con­sidered functional. After the power-on reset is

time has elapsed, the converter will be in the
standby mode waiting for instruction and will
enter the calibration cycle immediately if CAL
and CONV become active. The calibration lasts
for 3246 clock cycles. Calibration coefficients
are then retained in the SRAM (static RAM) for
use during conversion.

applied, the device enters the wake-up period for
1800 clock cycles after clock is present. This
allows the delta-sigma modulator and other cir­cuitry (which are operating with very low

The states of A0 and BP/UP are ignored during
calibration but should remain stable throughout
the calibration period to minimize noise.

currents) to reach a stable bias condition prior to
entering into either the calibration or conversion
states. During the 1800 cycle wake-up period,
the device can accept an input command. Execu-

10 DS126F1

When conversions are performed in unipolar
mode or in bipolar mode, the converter uses the
same calibration factors to compute the digital