Datasheet CS5471-BS Datasheet (Cirrus Logic)

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CS5471

Dual-Channel Delta-Sigma Analog-to-Digital Converter

Features

l Synchronous Sampling l On-chip 1.2 V Reference (25 ppm/°C typ.) l Power Supply Configurations:

– VA+ = +3 V; VA- = -2 V; VD+ = +3 V – Supply tolerances ±10%

l Power Consumption

– 10 mW Typical at VD+ = +3 V

l Simple Four-wire Serial Interface l Charge Pump Driver output generates

negative power supply.

l Ground-Referenced Bipolar Inputs

VA+

Description

The CS5471 is a highly integrated Delta-Sigma (∆Σ) Analog-to-Digital Converter (ADC) developed for the Power Measurement Industry. The CS5471 combines two ∆Σ ADCs, decimation filters, and a serial interface on a single chip. The CS5471 interfaces directly to a current transformer or shunt to measure current, and resistive divider or transformer to measure voltage. The product features a serial interface for communication with a micro-controller or DSP. The product is initialized and fully functional upon reset, and includes a Voltage Reference.

ORDERING INFORMATION:

CS5471-BS -40°C to +85°C 20-pin SSOP

RESET

VD+

GAIN

IIN IIN

VIN

VREFIN

VREFOUT

x1, 20

Voltage

Reference

AGND

4th Order∆ΣModulator

2nd Order∆ΣModulator

Preliminary Product Information

P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com

Decimation Filter

CLOCK

VA-

This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.

XIN

Pulse Output

Serial

Interface

Regulator

DGND

OWRS

SDO

FSO

SCLK

CPD

DS480PP5

JUL ‘01

TABLE OF CONTENTS

3. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 3

ANALOG CHARACTERISTICS ................................................................................................ 3

DIGITAL CHARACTERISTICS ................................................................................................. 4

RECOMMENDED OPERATING CONDITIONS ....................................................................... 5

ABSOLUTE MAXIMUM RATINGS ........................................................................................... 5

SWITCHING CHARACTERISTICS .......................................................................................... 6

4. GENERAL DESCRIPTION ....................................................................................................... 7

4.1 Theory of Operation ........................................................................................................... 7

4.2 Performing Measurements ................................................................................................. 7

4.3 High Rate Digital Filters ..................................................................................................... 8

4.4 Serial Interface ................................................................................................................... 8

4.5 System Initialization ........................................................................................................... 9

4.6 Analog Inputs ..................................................................................................................... 9

4.7 Voltage Reference ............................................................................................................. 9

4.8 Using the Charge Pump Drive Pin ..................................................................................... 9

4.9 PCB Layout ...................................................................................................................... 10

5. PIN DESCRIPTION.................................................................................................................. 11

6. PACKAGE DIMENSIONS........................................................................................................ 13

CS5471

LIST OF FIGURES

Figure 1. Serial Port Timing............................................................................................................. 6

Figure 2. Typical Connection Diagram ............................................................................................7

Figure 3. Serial Port Data Transfer ................................................................................................. 8

Figure 4. Close-up of One Frame.................................................................................................... 9

Figure 5. Generating VA- with a Charge Pump ............................................................................. 10

Contacting Cirrus Logic Support For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:

http://www.cirrus.com/corporate/contacts/sales/cfm

Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.

1. CHARACTERISTICS AND SPECIFICATIONS

CS5471

ANALOG CHARACTERISTICS (T

= -40 °C to +85 °C; +2.7V < VA+ < +3.5V; +2.7V < VD+ < +3.5V;

VA- = -2 V ±10%; External VREF+ = 1.2 V; XIN = 4.000 MHz; AGND, DGND = 0.0V.) (See Notes 1 and 2)

Parameter Symbol Min Typ Max Unit

Accuracy (All Channels)

Total Harmonic Distortion THD 74 - - dB

Common Mode Rejection (DC, 50, 60 Hz) CMRR 80 - - dB

Common Mode + Signal on Input VA- - VA+ V

Input Sampling Rate - XIN/4 - Hz

Analog Inputs (Current Channel)

Differential Input Voltage Range Gain=20 [ (v

IIN+) - (vIIN-) ] Gain=1

Bipolar Offset Gain=20

Gain=1

IIN -

VOS VOS

±40

±800

0.500 10

mV mV

Crosstalk (Channel-to-Channel) (50, 60 Hz) - - -120 dB

Input Capacitance Gain=20

Gain=1

IC IC

pF pF

Effective Input Impedance (Note 3)

Gain=20

Gain=1

Noise (Referred to Input) 0-60 Hz Gain=20

Gain=1

0-1 kHz Gain=20

Gain=1

0-2 kHz Gain=20

Gain=1

EII EII

500

600

2.5 50

3.75 75

kΩ kΩ

µV µV µV µV µV µVrms

Analog Inputs (Voltage Channel)

Differential Input Voltage Range [ (v

VIN+) - (vVIN-) ]

VIN - ±800 - mV

Bipolar Offset Gain=1 VOS - 20 25 mV

Crosstalk with Current Channel (50, 60 Hz) - - -120 dB

Input Capacitance IC - - 0.2 pF Effective Input Impedance (Note 3) EII - 3 4 MΩ

Noise (Referred to Input) 0-60 Hz 0-1 kHz 0-2 kHz

20 50 75

µV µV µV

Dynamic Characteristics

High Rate Filter Output Word Rate OWRS = “0”

OWRS = “1”

OWR OWR

XIN/2048 XIN/1024

Hz Hz

rms

0-pk

rms

Notes: 1. Specifications guaranteed by design, characterization, and/or test.

2. Analog signals are relative to AGND and digital signals to DGND unless otherwise noted.

3. Effective Input Impedance (EII) varies with clock frequency (XIN) and Input Capacitance (IC) EII = 1/(IC*XIN/4)

CS5471

ANALOG CHARACTERISTICS (Continued)

Parameter Symbol Min Typ Max Unit

Reference Output

Output Voltage REFOUT 1.15 - 1.25 V

Temperature Coefficient - 20 50 ppm/°C Load Regulation (Output Current 1µA Source or Sink) ∆V

Power Supply Rejection PSRR 60 - - dB

Reference Input

Input Voltage Range VREF+ 1.15 1.2 1.25 V

Input Capacitance - - 10 pF

Input CVF Current - - 1 µA

Power Supplies

Power Supply Currents I

A+

D+

PSCA

PSCD

Power Consumption (Note 4) PC - - 15 mW

Power Supply Rejection (DC, 50, 60 Hz)

PSRR 60 - - dB

(see Note 5)

-610mV

1.5

2.5

mA mA

Notes: 4. All outputs unloaded. All inputs CMOS level.

5. Definition for PSRR: VREFIN tied to VREFOUT, VA+ = VD+ = 3V, AGND = DGND = 0V, VA- = -2V (using charge-pump circuit with CPD). In addition, a 106.07 mV rms (60 Hz) sinewave is imposed onto the VA+ and VD+ pins. The “+” and “-” input pins of both input channels are shorted to VA-. Instantaneous digital output data words are then collected for the channel under test. From these data samples, the rms value (standard deviation) of the digital sinusoidal output signal is calculated, and this rms value is converted into the rms value of the sinusoidal voltage (measured in mV) that would need to be applied at the channel’s inputs, in order to cause the same digital sinusoidal output. This voltage is then defined as Veq. PSRR is then (in dB)



106.07

------------- ---

log⋅=





DIGITAL CHARACTERISTICS (T

PSRR 20

= -40 °C to +85 °C; +2.7V < VA+ < +3.5V; +2.7V < VD+ < +3.5V;

VA- = -2 V ±10%; AGND, DGND = 0.0 V) (See Note 6)

Parameter Symbol Min Typ Max Unit

High-Level Input Voltage V

Low-Level Input Voltage V

High-Level Output Voltage I

Low-Level Output Voltage I

= -5.0 mA V

out

= 5.0 mA V

out

Input Leakage Current (Note 7) I

3-State Leakage Current I

Digital Output Pin Capacitance C

out

0.6 VD+ - VD+ V

0.0 - 0.8 V

(VD+) - 1.0 - - V

--0.4V

-±1±10µA

--±10µA

-9-pF

Notes: 6. All measurements performed under static conditions.

7. For OWRS and GAIN

pins, input leakage current is 30 µA (Max).

CS5471

RECOMMENDED OPERATING CONDITIONS (AGND, DGND = 0.0 V)

Parameter Symbol Min Typ Max Unit

DC Power Supplies Positive Digital

Positive Analog

Negative Analog

Voltage Reference Input VREF+ - 1.2 - V

ABSOLUTE MAXIMUM RATINGS (AGND, DGND = 0.0 V; See Note 8.)

Parameter Symbol Min Typ Max Unit

DC Power Supplies Positive Digital

Positive Analog

Negative Analog

Input Current, Any Pin Except Supplies (Note 9 and 10) I

Output Current I

Power Dissipation (Note 11) PDN - - 500 mW

Analog Input Voltage All Analog Pins V

Digital Input Voltage All Digital Pins V

Ambient Operating Temperature T

Storage Temperature T

VD+

VA+

VA-

VD+

VA+

VA-

OUT

INA

IND

stg

2.7

-2.2

-0.3

-2.5

--±10mA

--±25mA

VA- - 0.3 - (VA+) + 0.3 V

-0.3 - (VD+) + 0.3 V

-40 - 85 °C

-65 - 150 °C

3.0

-2.0

3.5

-1.8

+3.5 +3.5

-0.3

V V V

Notes: 8. All voltages with respect to AGND.

9. Applies to all pins including continuous over-voltage conditions at the analog input (AIN) pins.

10. Transient current of up to 100 mA will not cause SCR latch-up. Maximum input current for a power supply pin is ±50 mA.

11. Total power dissipation, including all input currents and output currents.

WARNING: Operation at or beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes.

CS5471

SWITCHING CHARACTERISTICS (T

= -40 °C to +85 °C; VA+, VD+ = 3.0 V ±10%; VA- = -2 V

±10%; DGND = AGND = 0.0 V; Logic Levels: Logic 0 = 0.0 V, Logic 1 = VD+; CL = 50pF))

Parameter Symbol Min Typ Max Unit

Master Clock Frequency (Note 12) XIN 3 4.000 5 MHz

Master Clock Duty Cycle - 40 - 60 %

Rise Times Any Digital Input (Note 13)

Any Digital Output

Fall Times Any Digital Input (Note 13)

Any Digital Output

rise

fall

1.0

µs

Serial Port Timing

Serial Clock Frequency (Note 12)

OWRS = “0” OWRS = “1”

Serial Clock Pulse Width High (Note 12)

Pulse Width Low (Note 12)

SCLK falling to New Data Bit t

FSO Falling to SCLK Rising Delay (Note 12) t

FSO Pulse Width (Note 12) t

SE Rising to Output Enabled t

SE Falling to Output in Tri-state t

SCLK SCLK

500

1000

0.5

kHz kHz

SCLK SCLK

- - 50 ns

-0.5-SCLK

-1-SCLK

- - 50 ns

Notes: 12. Device parameters are specified with a 4.000 MHz clock, OWRS = 1.

13. Specified using 10% and 90% points on wave-form of interest. Output loaded with 50 pF.

SDO

SCLK

FSO

MSB(V1) MSB(V1) - 1 LSB(I2)

Figure 1. Serial Port Timing

CS5471

2. GENERAL DESCRIPTION

The CS5471 is designed for single-phase power meter applications and interfaces to a current transformers or shunt to measure current, and a resistive divider or transformer to measure voltage.

The CS5471 combines two ∆Σ modulators and decimation filters, one channel assigned for current input that has programmable input gain amplifiers, and one channel assigned for voltage input.

The CS5471 includes two decimation filters that output data at a 2000 Hz or 4000 Hz output word rate (OWR) when the input frequency at XIN =

4.096 MHz.

The device outputs data on a serial output port.

2.1 Theory of Operation

The CS5471 is designed to operate from a single +3V supply and provides a ±40 mV and ±800 mV input range for the current channel and ±800 mV range for the voltage channel. These voltages represent the maximum zero-to-peak voltage levels that can be presented to the inputs. The CS5471 is designed to accommodate common mode + signal levels from VA- to VA+. Figure 2 illustrates the CS5471 typical inputs and power supply connections.

2.2 Performing Measurements

The converter outputs are transferred in 16-bit signed (two’s complement) data formats as a per-

+3 V

VA+

REFIN

VD+

PHASE

Optional External

Refe rence

1.2 V

-2 V

REFOUT

VIN

IIN

NOTE:

Current input channel

actually measures voltage.

IIN

AGND

VA-

DGND

Figure 2. Typical Connection Diagram

centage of full scale. Table 1 below illustrates the ideal relationship between the differential voltage presented any one of the input channels and the corresponding output code. Note that for the current channels, the state of the GAIN input pin is assumed to driven low, such that the PGA gain on the current channels is 1x. If the PGA gain of the current channels is set to 20x, then a +40 mV differen-

tial voltage presented across the “IIN+” and “IIN-” pins will cause a (nominal) output code of 32767.

CS5471



Hz()

-------------- --------

 

If the OWRS pin is set to logic high, then the transfer function is

256–

–

1–

Input Voltage

(mV

0-pk)

+800 7FFF 32767

0.0122 to 0.0366 0001 1

-0.0122 to 0.0122 0000 0

-0.0122 to -0.0366 FFFF -1

-800 8000 -32768

Table 1. Nominal Relationship for Differential Input

Voltage vs. Output Code, for all channels. (Assume PGA

Output Code

(hexadecimal)

gain is set to 1x.)

Output Code

(decimal)

2.3 High Rate Digital Filters

If the OWRS pin is set to logic low, the high-rate filters are implemented as fixed sinc3 filters with the following transfer function:

This filter samples the modulator bit stream at XIN/8 Hz and decimates to XIN/2048 Hz.

128–

–

1–

Hz()



-------------- --------

 

The above filter samples the modulator bit stream at XIN/8 Hz and decimates to XIN/1024 Hz.

2.4 Serial Interface

The CS5471 communicates with a target device via a master serial data output port. Output data is provided on the SDO output synchronous with the SCLK output.

A third output, FSO, is a framing signal used to signal the start of output data. These three outputs will be driven as long as the SE (serial enable) input is held high. Otherwise, these outputs will be high impedance.

SCLK

FSO

Each data segment

is 16 bits long.

SDO

Channel 1 (V)

Channel 1 (I)

64 0-value bits

Figure 3. Serial Port Data Transfer

SCLK

FSO

CS5471

96 SCLK Cycles

. . .

1215 1413 01234567891011 1514 13 12 11 10 9 8 7 6 5 4 3 2 1

SDO

Figure 4. Close-up of One Frame

Data out (SDO) changes as a result of SCLK falling, and always outputs valid data with SCLK rising. When data is being transferred, the SCLK frequency is either 1/8 of the XIN input frequency (when OWRS is held low) or 1/4 of the XIN input frequency (when OWRS is held high). Any other time, SCLK is held low. (See Figures 3 and 4.)

The framing signal (FSO) output is normally low, but produces a high level pulse lasting one SCLK period when the instantaneous voltage/current data samples are about to be transmitted out of the serial interface (after each A/D conversion cycle). Note that SCLK is not active during FSO high.

For 96 SCLK periods after FSO falls, SCLK is active and SDO produces valid output. Six channels of 16 bit data are output, MSB first. First, the voltage and current measurements are output (in that order). This is followed by four more 16-bit words of zero-value data. SCLK will then be held low until the next sample period.

2.5 System Initialization

When power to the CS5471 is applied, the chip must be held in a reset condition using the RESET input.

A hardware reset is initiated when the RESET pin is forced low with a minimum pulse width of 50 ns.

. . .

Channel 1 ( I )Channel 1 ( V )

All 0’s

2.6 Analog Inputs

The analog inputs of the CS5471 are bipolar voltage inputs: One voltage channel input pair (VIN+ and VIN-) and current channel input pair (IIN+ and IIN-). The CS5471 accommodates a full scale range of ±40 mV or ±800 mV on the Current Channel and ±800 mV on the Voltage Channel.

2.7 Voltage Reference

The CS5471 is specified for operation with a +1.2 V reference between the VREFIN and AGND pins. The converter includes an internal 1.2 V reference (50 ppm/°C drift) that can be used by connecting the VREFOUT pin to the VREFIN pin of the device. If higher accuracy/stability is required, an external reference can be used.

2.8 Using the Charge Pump Drive Pin

The low, stable analog power consumption and superior supply rejection of the CS5471 allow for the use of a simple charge-pump negative supply generator. The use of a negative supply alleviates the need for level shifting of the analog inputs. The CPD pin and capacitor C1 provide the necessary analog supply current as shown in Figure 5. The Schottky diodes D1 and D2 are chosen for their low forward voltages and high-speed capabilities. The capacitor C2 provides the required charge storage

CS5471

AGND

BAT 85

40 nF

CPD

VA-

BAT 85

1µF

Figure 5. Generating VA- with a Charge Pump

and bypassing of the negative supply. The CPD output signal provides the charge pump driver signal. The frequency of the charge pump driver signal is synchronous to XIN. The nominal average frequency is 1 Mhz. The level on the VA- pin is fed back internally so that the CPD output will regulate the VA- level to -2/3 of VA+ level.

12.5%. Therefore, the value of C1 should be reduced by 12.5%, making the new value for C1 to be 35 nF. For more information about the operation of this type of charge pump circuit, the reader can refer to Cirrus Logic, Inc.’s application note AN152:

Using the CS5521/24/28, and CS5525/26 Charge Pump Drive for External Loads.

2.9 PCB Layout

For optimal performance, the CS5460A should be placed entirely over an analog ground plane with both the VA- and DGND pins of the device connected to the analog plane. Place the analog-digital plane split immediately adjacent to the digital portion of the chip.

Note: Refer to the CDB5460A Evaluation Board for

suggested layout details and Applications Note 18 for more detailed layout guidelines. Before layout, please call for our Free Schematic Review Service.

Note the value of C1 in Figure 5. The 40 nF value is recommended when the input frequency presented to the XIN pin is 4.00 MHz. If the user decides to use an XIN frequency that is significantly different than 4.00 MHz (if the XIN frequency is increased/decreased by more than 5% of 4.00 MHz, then it is recommended that the user should alter the value of C1. The percentage change in the value of C1 (with respect to a reference value of 40 nF) should be inversely proportional to the percentage change in the XIN frequency. For example, if the XIN frequency is increased from 4.00 MHz to 4.5 MHz, this represents a percentage increase of

3. PIN DESCRIPTION

CS5471

Serial Clock Output SCLK VD+ Digital Supply

Serial Data Output SDO DGND Digital Ground

Frame Sync FSO CPD Charge Pump Drive

Serial Port Enable SE XIN Master Clock

Current Input Gain GAIN RESET Reset

Analog Ground AGND OWRS Output Word Rate Select

Reference Input VREFIN VIN+ Differential Voltage Input 1

Reference Output VREFOUT VIN- Differential Voltage Input 1

Positive Analog Supply VA+ IIN+ Differential Current Input 1

Negative Analog Supply VA- IIN- Differential Current Input 1

Clock Generator

XIN - Master Clock Input

Control Pins and Serial Data I/O

SE - Serial Port Enable.

When SE is low, the output pins of the serial port are 3-stated.

813

10 11

SDO - Serial Port Output.

Data will be at a rate determined by SCLK.

FSO - Frame Signal Output.

Framing signal output for data transfer from SDO pin.

SCLK - Serial Clock Output.

A clock signal on this pin determines the output rate of data for SDO pin. Rate of SCLK is determined by XIN frequency and state of OWRS input pin.

RESET - Reset.

When reset is taken low, all internal registers are set to their default states.

GAIN - Input Gain Control.

Sets input gain for current channel. A logic high sets internal gain to 1, a logic low level sets the gain to

20. If no connection is made to this pin, it will default to logic low level (through internal 200K resistor to DGND).

OWRS - Output Word Rate Select.

When OWRS is set to logic low, the output word rate (OWR) at SDO pin is XIN/2048 (Hz). When set to logic high, the OWR at SDO pin is XIN/1024 (Hz). If no connection is made to this pin, then OWRS will default to logic low level (through internal 200K resistor to DGND).

Measurement and Reference Input

IIN+, IIN- - Differential Current Input.

Differential analog input pins for current channel.

VIN+, VIN- - Differential Voltage Inputs.

Differential analog input pins for voltage channel.

VREFOUT - Voltage Reference Output.

The on-chip voltage reference is output from this pin. The voltage reference has a nominal magnitude of

1.2 V and is referenced to the AGND pin on the converter.

VREFIN - Voltage Reference Input.

The voltage input to this pin establishes the voltage reference for the on-chip modulator.

Power Supply Connections

VA+ - Positive Analog Supply.

The positive analog supply is nominally +3 V ±10% relative to AGND.

CS5471

VA- - Negative Analog Supply.

The negative analog supply is nominally -2 V ±10% relative to AGND.

AGND - Analog Ground.

The analog ground pin for input signals.

VD+ - Positive Digital Supply.

The positive digital supply is nominally +3 V ±10% relative to DGND.

DGND - Digital Ground.

The digital ground is typically at the same level as AGND.

CPD - Charge Pump Drive

This output pin drives the external charge pump circuitry to create a negative supply voltage.

4. PACKAGE DIMENSIONS

20L SSOP PACKAGE DRAWING

CS5471

∝

SIDE VIEW

TOP VIEW

INCHES MILLIMETERS NOTE

DIM MIN NOM MAX MIN NOM MAX

A -- -- 0.084 -- -- 2.13 A1 0.002 0.006 0.010 0.05 0.13 0.25 A2 0.064 0.068 0.074 1.62 1.73 1.88

b 0.009 -- 0.015 0.22 -- 0.38 2,3

D 0.272 0.2834 0.295 6.90 7.20 7.50 1

E 0.291 0.307 0.323 7.40 7.80 8.20 E1 0.197 0.209 0.220 5.00 5.30 5.60 1

e 0.022 0.026 0.030 0.55 0.65 0.75

L 0.025 0.03 0.041 0.63 0.75 1.03

∝

0° 4° 8° 0° 4° 8°

SEATING

PLANE

END VIEW

JEDEC #: MO-150

Controlling Dimension is Millimeters.

Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold

mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side.

2. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be

0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not reduce dimension “b” by more than 0.07 mm at least material condition.

3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.

Datasheet CS5471-BS Datasheet (Cirrus Logic)

Specifications and Main Features

Frequently Asked Questions

User Manual

Features

Description

1. CHARACTERISTICS AND SPECIFICATIONS

ANALOG CHARACTERISTICS (T

DIGITAL CHARACTERISTICS (T

RECOMMENDED OPERATING CONDITIONS (AGND, DGND = 0.0 V)

ABSOLUTE MAXIMUM RATINGS (AGND, DGND = 0.0 V; See Note 8.)

SWITCHING CHARACTERISTICS (T

Figure 1. Serial Port Timing

2. GENERAL DESCRIPTION

2.1 Theory of Operation

2.2 Performing Measurements

Figure 2. Typical Connection Diagram

2.3 High Rate Digital Filters

2.4 Serial Interface

Figure 3. Serial Port Data Transfer

Figure 4. Close-up of One Frame

2.5 System Initialization

2.6 Analog Inputs

2.7 Voltage Reference

2.8 Using the Charge Pump Drive Pin

Figure 5. Generating VA- with a Charge Pump

2.9 PCB Layout

3. PIN DESCRIPTION

4. PACKAGE DIMENSIONS