Cirrus Logic CS5460-BS Datasheet

CS5460

Single Phase Bi-Directional Power/Energy IC

Features

l Energy Data Linearity: 0.1% of Reading over

1000:1 Dynamic Range

l On-Chip Functions: Energy, I ∗ V,

I

and V

RMS

Conversion

l Complies with IEC 687/1036, JIS
l Power Consumption <12 mW
l Interface Optimized for Shunt Sensor
l Phase Compensation
l Ground-Referenced Signals wi th Single

Supply

l System Calibration
l On-chip 2.5 V Reference (60 ppm/°C drift)
l Simple Three-wire Serial Interface
l Watch Dog Timer
l Power Supply Monitor
l Power Supply Configurations

- VA+ = +5 V; VA- = 0V; VD+ = +3 V to +5 V

- VA+ = +2.5 V; VA- = -2.5 V; VD+ = +3 V

, Energy to Pulse-Rate

RMS

Description

The CS5460 is a h ighly integrated ∆Σ Analog-to -Digital
Converter (ADC) which combines two ∆Σ ADCs, high
speed power calculation functions, and a serial interface
on a single chip. It is desi gned to accurately measure
and calculate: Energ y, Instantaneous Power, I

for single phase 2 or 3-wire po wer meter a pplica-

V

RMS

tions. The CS5460 interfaces to a low cost shunt or
transformer to measure c urrent, and r esistive divid er or
transformer to measure voltage. The CS5460 features a
bi-directional serial interface for communication with a
micro-controller and a fixed-width programmable fre­quency output that is proportional to energy. The product
is initialized and ful ly functional upon power-u p, and in­cludes facilities for system-level calibration under control
of the user program.

ORDERING INFORMATION:

CS5460-BS -40°C to +85°C 24-pin SSOP

RMS

, and

VA+ VD+

IIN+

IIN-

VIN+

VIN-

VREFIN

VREFOUT

PGA
x10,x50

x10

x1

Voltage

Reference

VA-

4 Order

Modulator

2 Order

Modulator

Preliminary Product Information

P.O. Box 17847, Austin, Texas 78760
[phone] FAX: [phone]
http://www.cirrus.com

RESET

Watch Dog

Timer

Serial

Interface

E-to-F

Calibration

SRAM

DGND

th

∆Σ

nd

∆Σ

Power

Monitor

PFMON

System

Clock

Digital

Filter

Digital

Filter

/K

High Pass

Calculation

I ,V )

RMS RMS

High Pass

Generator

XIN

XOUT

Filter

Power

Engine

(Energy

I * V

Filter

Clock

CPUCLK

This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.

Copyright  Cirrus Logic, Inc. 2000

(All Rights Reserved)

CS
SDI
SDO

SCLK
INT

EDIR
EOUT

JUL ‘00

DS279PP6

1

TABLE OF CONTENTS

1. CHARACTERISTICS AND SPECIFICATIONS............................. ...... ....... ...... ....... ..... 4

ANALOG CHARACTERISTICS ...............................................................................4

5 V DIGITAL CHARACTERISTICS ......................................................................... 5

3 V DIGITAL CHARACTERISTICS ......................................................................... 6

ABSOLUTE MAXIMUM RATINGS ..........................................................................6

SWITCHING CHARACTERISTICS ... ....... ...... ............................................. ....... ..... 7

2. GENERAL DESCRIPTION ........................................................................................... 9

2.1 Theory of Operation........................................................................................... 9

2.2 Performing Measurements ................................................................................9

2.2.1 Single Computation Cycle (C = 0).......................................................... 11

2.2.2 Multiple Computation Cycles (C = 1)......................................................11

2.3 High Rate Digital Filters...................................................................................11

2.4 Pulse-Rate Output ...........................................................................................12

3. SERIAL PORT OVERVIEW........................................................................................15

3.1 Command Word (Write Only) ..........................................................................16

3.1.1 Start Conversions...................................................................................16

3.1.2 SYNC0 Command..................................................................................16

3.1.3 SYNC1 Command..................................................................................16

3.1.4 Power-up/Halt Control............................................................................ 16

3.1.5 Power-down Control...............................................................................17

3.1.6 Calibration Control .................................................................................17

3.1.7 Register Read/Write Command ............................................................. 18

3.2 Serial Port Interface.........................................................................................19

3.3 Serial Port Initialization....................................................................................19

3.4 System Initialization......................................................................................... 21

CS5460

4. REGISTER DESCRIPTION ........................... ...... ...... ....... .......................................... 2 2

4.1 Configuration Register ....................................................................................22

4.2 Current Offset Register and Voltage Offset Register ...................................... 23

4.3 Current Gain Register and Voltage Gain Register .......................................... 24

4.4 Cycle Count Register ...................................................................................... 24

4.5 Pulse-Rate Register ........................................................................................24

4.6 I,V,P,E Signed Output Register Results .........................................................24

4.7 IRMS, VRMS Unsigned Output Register Results ...........................................25

4.8 Timebase Calibration ...................................................................................... 25

4.9 Status Register and Mask Register ................................................................25

Contacting Cirrus Logic Support

For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:

http://www.cirrus.com/corporate/contacts/

Microwire is a trademark of National Semiconductor Corporation.
Preliminary product inf o rmation describes products whi ch are in production, but f or wh i ch ful l characterization data is not yet available. Advance produ ct i nf or -

mation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information
contained in this document i s accurat e and reli able. However , t he infor mation is subje ct to chang e without noti ce and is provi d ed “AS IS” without warrant y of

any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other ri g ht s
of third parties. This document is the pro perty of Cirrus Logi c, Inc. and i mplie s no licen se under patents, copyrights, tr ademarks, or trade secre ts. No part of
this publication may be copied, reproduced , stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or
otherwise) without the pr i or writ ten consent of Cirrus Logic, Inc. Ite ms f rom any Ci rrus L ogi c websi t e or disk may be printed for use by the user. However, no
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photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Furthermore, no part of this publication ma y be used as a basis for manufacture
or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing
in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trade­marks and service marks can be found at http://www.cirrus.com.

2 DS279PP6

CS5460

5. FUNCTIONAL DESCRIPTION ................................................................................... 28

5.1 Interrupt and Watchdog Timer......................................................................... 28

5.1.1 Interrupt.................................................................................................. 28

5.1.1.1 Clearing the Status Register ........................................................ 28

5.1.1.2 Typical use of the INT pin............................................................. 28

5.1.1.3 INT Active State ........................................................................... 28

5.1.1.4 Exceptions.................................................................................... 28

5.1.2 Watch Dog Timer................................................................................... 28

5.2 Oscillator Characteristics................................................................................. 29

5.3 Analog Inputs .................................................................................................. 29

5.4 Voltage Reference........................................................................................... 30

5.5 Performing Calibrations................................................................................... 30

5.5.1 System Calibration................................................................................. 30

5.5.2 Calibration Tips...................................................................................... 31

5.6 Phase Compensation ...................................................................................... 31

5.7 Input Current Protection.................................................................................. 31

5.8 PCB Layout ..................................................................................................... 32

6. PIN DESCRIPTION.................................................... ....... ...... ....... ...... ....... ................ 33

7. SPECIFICATION DEFINITIONS................................................................................. 34

8. PACKAGE DIMENSIONS .......................................................................................... 35

LIST OF FIGURES

Figure 1. SDI Write Timing (Not to Scale).......................................................................................8

Figure 2. SDO Read Timing (Not to Scale)..................................................................................... 8

Figure 3. Typical Connection Diagram (One-Phase 2-Wire)......................................................... 10

Figure 4. Typical Connection Diagram (One-Phase 3-Wire)......................................................... 10

Figure 5. Data Flow....................................................................................................................... 11

Figure 6. Voltage Input Filter Roll-off ............................................................................................ 12

Figure 7. Current Input Filter Roll-off............................................................................................. 12

Figure 8. Multi-Phase System....................................................................................................... 14

Figure 9. CS5460 Register Diagram............................................................................................. 15

Figure 10. Command and Data Word Timing ............................................................................... 20

Figure 11. Oscillator Connection................................................................................................... 29

Figure 12. System Calibration of Offset........................................................................................ 30

Figure 13. System Calibration of Gain.......................................................................................... 30

LIST OF TABLES

Table 1. Specification with MCLK = 4.096 MHz, K = 1, and N = 4000............................................ 9

Table 2. Internal Registers Default Value ..................................................................................... 21

Table 3. CPU Clock (and K) Restrictions...................................................................................... 29

DS279PP6 3

1. CHARACTERISTICS AND SPECIFICATIONS

CS5460

ANALOG CHARACTERISTICS (T

VA- = AGND; MCLK = 4.096 MHz, K = 1; N = 4000, OWR = 4.0 kHz.)(See Notes 1, 2, and 3)

Parameter Symbol Min Typ Max Unit

= -40 °C to +85 °C; VA+, VD+ = +5 V ±10%; VREFIN = 2.5 V;

A

Accuracy (Both Channels)

Total Harmonic Distortion THD 74 - - dB
Common Mode Rejection (DC, 50, 60 Hz) CMRR 80 - - dB
Offset Drift (Without the High Pass Filter) - 5 - nV/°C
Full Scale DC Calibration Range (Note 4) FSCR 25 - 100 %F.S.
Input Sampling Rate DCLK = MCLK/K - DCLK/4 - Hz

Analog Inputs (Current Channel)

Differential Input Voltage Range {(IIN+) - (IIN-)} (Gain = 10)

(Gain = 50)

Common Mode + Signal on IIN+ or IIN- (Gain = 10 or 50) -0.25 - VA+ V
Crosstalk with Voltage Channel at Full Scale (50, 60 Hz) - - -115 dB
Input Capacitance (Gain = 10)

(Gain = 50)

Effective Input Impedance (Note 5)

(Gain = 10)

(Gain = 50)

Noise (Referred to Input) (Gain = 10)

(Gain = 50)

IIN 0

IC -

EII

30
30

-

0

-

-

-

-

5

25

-

-

-

-

±250

±50

-

-

-

-

20

4

mV(dc)
mV(dc)

pF
pF

kΩ
kΩ

µV

rms

µV

rms

Accuracy (Current Channel)

Bipolar Offset Error (Note 1) VOS - - ±0.001 %F.S.
Full-Scale Error (Note 1) FSE - - ±0.001 %F.S.

Analog Inputs (Voltage Channel)

Differential Input Voltage Range {(VIN+) - (VIN-)} VIN 0 - ±250 mV(dc)
Common Mode + Signal on VIN+ or VIN- -0.25 - VA+ V

Crosstalk with Current Channel at Full Scale (50, 60 Hz) - - -70 dB
Input Capacitance IC - 0.2 - pF
Effective Input Impedance (Note 5) EII 5 - - MΩ
Noise (Referred to Input) - - 250 µV

rms

Accuracy (Voltage Channel)

Bipolar Offset Error (Note 1) VOS - - ±0.01 %F.S.
Full-Scale Error (Note 1) FSE - - ±0.01 %F.S.

Notes: 1. Applies after system calibration

2. Specifications guaranteed by design, characterization, and/or test.

3. Analog signals are relative to VA- and digital signals to DGND unless otherwise noted.

4. The minimum FSCR is limited by the maximum allowed gain register value.

5. Effective Input Impedance (EII) varies with clock frequency (DCLK) and Input Capacitance (IC)
EII = 1/(IC*DCLK/4)

4 DS279PP6

CS5460

ANALOG CHARACTERISTICS (Continued)

Parameter Symbol Min Typ Max Unit

Dynamic Characteristics

Phase Compensation (Voltage Channel at 60 Hz) -2.4 - +2.5 °
High Rate Filter Output Word Rate (Both Channels) OWR - DCLK/1024 - Hz
High Pass Filter Pole Frequency -3 dB - 0.5 - Hz

Reference Output

Output Voltage REFOUT 2.4 - 2.6 V
Temperature Coefficient - 25 60 ppm/°C
Load Regulation (Output Current 1 µA Source or Sink) ∆V

R

Output Noise Voltage (0.1 Hz to 512 kHz) eN - 100 - µV

Reference Input

Input Voltage Range VREFIN 2.4 2.5 2.6 V
Input Capacitance - 4 - pF
Input CVF Current - 25 - nA

Power Supplies

Power Supply Currents (Normal Mode) I

I

(VD+ = 5 V)

D+

(VD+ = 3 V)

I

D+

Power Consumption Normal Mode (VD+ = 5 V)

A+

PSCA
PSCD
PSCD

PC -

(Note 6) Normal Mode (VD+ = 3 V)

Standby

Sleep

Power Supply Rejection (50, 60 Hz)

(Gain = 10)
(Gain = 50)

PSRR
PSRR

Power Monitor Thresholds PM 2.3 2.7 V

-610mV

rms

-

-

-

-

-

-

1.3

2.9

1.7
21

11.6

6.75
10

25

-

-

-

mA
mA
mA

mW

-

-

-

mW
mW

µW

-­56
70

dB
dB

Notes: 6. All outputs unloaded. All inputs CMOS level.

5 V DIGITAL CHARACTERISTICS (T

= -40 °C to +85 °C; VA+, VD+ = 5 V ±10% VA-, DGND = 0

A

V) (See Notes 2 and 7)

Parameter Symbol Min Typ Max Unit

High-Level Input Voltage All Pins Except XIN and SCLK

XIN

SCLK

Low-Level Input Voltage All Pins Except XIN and SCLK

XIN

SCLK

High-Level Output Voltage I
Low-Level Output Voltage I

= +5 mA V

out

= -5 mA V

out

Input Leakage Current I
3-State Leakage Current I
Digital Output Pin Capacitance C

V

V

OH
OL

in

OZ

out

IH

0.6 VD+

(VD+) - 0.5

0.8 VD+

IL

-

-

-

(VD+) - 1.0 - - V

--0.4V

-±1±10µA

--±10µA

-5-pF

-

-

-

-

-

-

-

-

-

0.8

1.5

0.2 VD+

V
V
V

V

DS279PP6 5

CS5460

3 V DIGITAL CHARACTERISTICS (T

= -40 °C to +85 °C; VA+ = 5 V ±10%, VD+ = 3 V ±10%; VA-,

A

DGND = 0 V) (See Notes 2 and 7)

Parameter Symbol Min Typ Max Unit

High-Level Input Voltage All Pins Except XIN and SCLK

XIN

SCLK

Low-Level Input Voltage All Pins Except XIN and SCLK

XIN

SCLK

High-Level Output Voltage I
Low-Level Output Voltage I

= +5 mA V

out

= -5 mA V

out

Input Leakage Current I
3-State Leakage Current I
Digital Output Pin Capacitance C

V

V

OH
OL

in

OZ

out

IH

IL

0.6 VD+

(VD+) - 0.5

0.8 VD+

-

-

-

-

-

-

-

-

-

(VD+) - 1.0 - - V

--0.4V

-±1±10µA

--±10µA

-5-pF

-

-

-

0.48

0.3

0.2 VD+

V
V
V

V

Notes: 7. All measurements performed under static conditions.

ABSOLUTE MAXIMUM RATINGS (DGND = 0 V; See Note 8)

Parameter Symbol Min Typ Max Unit

DC Power Supplies (Notes 9 and 10)

Positive Digital

Positive Analog

Negative Analog

Input Current, Any Pin Except Supplies (Note 11 and 12) I
Output Current I
Power Dissipation (Note 13) PDN - - 500 mW

Analog Inpu t Voltage All Analog Pins V
Digital Input Voltage All Digital Pins V
Ambient Operating Temperature T
Storage Temperature T

VD+
VA+

VA-

IN

OUT

INA
IND

A

stg

-0.3

-0.3
+0.3

-

-

-

+6.0
+6.0

-6.0

--±10mA

--±25mA

- 0.3 - (VA+) + 0.3 V

-0.3 - (VD+) + 0.3 V

-40 - 85 °C

-65 - 150 °C

V
V
V

Notes: 8. All voltages with respect to ground.

9. VA+ and VA- must satisfy {(VA+) - (VA-)} < +6.0 V.

10. VD+ and VA- must satisfy {(VD+) - (VA-)} < +6.0 V.

11. Applies to all pins including continuous over-voltage conditions at the analog input (AIN) pins.

12. Transient current of up to 100 mA will not cause SCR latch-up. Maximum input current for a power
supply pin is ±50 mA.

13. Total power dissipation, including all input currents and output currents.

WARNING: Operation at or beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes.

6 DS279PP6

CS5460

SWITCHING CHARACTERISTICS (T

= -40 °C to +85 °C; VA+ = 5.0 V ±10%; VD+ = 3.0 V ±10%

A

or 5.0 V ±10%; VA- = 0.0 V; Logic Levels: Logic 0 = 0.0 V, Logic 1 = VD+; CL = 50pF))

Parameter Symbol Min Typ Max Unit

Master Clock Frequency Internal Gate Oscillator (Note 14) MCLK 2.5 4.096 20 MHz
Master Clock Duty Cycle 40 - 60 %
CPUCLK Duty Cycle (Note 15) 40 60 %
Rise Times Any Digital Input Except SCLK (Note 16)

SCLK

Any Digital Output

Fall Times Any Digital Input Except SCLK (Note 16)

SCLK

Any Digital Output

t

t

rise

fall

-

-

-

-

-

-

50

50

-

-

-

-

1.0

100

-

1.0

100

-

µs
µs
ns

µs
µs
ns

Start-up

Oscillator Start-up Time XTAL = 4.096 MHz (Note 17) t

ost

-60-ms

Serial Port Timing

Serial Clock Frequency SCLK - - 2 MHz
Serial Clock Pulse Width High

Pulse Width Low

t

1

t

2

200
200

-

-

-

-

ns
ns

SDI Write Timing

CS Enable to Valid Latch Clock t
Data Set-up Time Prior to SCLK Rising t
Data Hold Time After SCLK Rising t
SCLK Falling Prior to CS

Disable t

3
4
5
6

50 - - ns

50 - - ns
100 - - ns
100 - - ns

SDO Read Timing

CS Enable to Valid Latch Clock t
SCLK Falling to New Data Bit t

Rising to SDO Hi-Z t

CS

7
8
9

--150ns

--150ns

--150ns

Notes: 14. Device parameters are specified with a 4.096 MHz clock, however, clocks between 3MHz to 20 MHz

can be used.

15. If external MCLK is used, then its duty cycle must be between 45% and 55% to maintain this spec.

16. Specified using 10% and 90% points on wave-form of interest. Output loaded with 50 pF.

17. Oscillator start-up time varies with crystal parameters. This specification does not apply when using an
external clock source.

DS279PP6 7

CS

CS5460

SDI

SCLK

CS

SDO

SCLK

MSB MSB - 1

t

3

t

7

t

MSB MSB - 1

t

8

t

t

4

5

t

2

1

Figure 1. SDI Write Timing (Not to Scale)

t

t

2

1

LSB

LSB

t

6

t

9

Figure 2. SDO Read Timing (Not to Scale)

8 DS279PP6

CS5460

2. GENERAL DESCRIPTION

The CS5460 is a CMOS monolithic power mea­surement device with an energy computation en­gine. The CS5460 combines a programmable gain
amplifier, two ∆Σ modulators, two high rate filters,
system calibration, and power calculation func­tions to compute Energy, V

RMS

, I

, and Instan-

RMS

taneous Power.
The CS5460 is designed for power meter applica-

tions and is optimized to interface to shunts or cur­rent transformers to measure current, and a
resistive divider or transformer to measure voltage.
To accommodate various input voltage levels due
to shunts, the current channel includes a program­mable gain amplifier (PGA) which allows the user
to measure either 150 mV

or 30 mV

RMS

RMS

sig-

nals.
The CS5460 includes two high-rate digital filters

which output data at a (MCLK/K)/1024 output word
rate (OWR). A high-pass filter in both channels can
be enabled to remove the DC content from the input
signal before the energy calculations are made.

To ease communication between the CS5460 and a
micro-controller, the converter includes a simple

three-wire serial interface which is SPI™ and Mi­crowire™ compatible. The serial port also contains
a Schmitt Trigger input on its serial clock (SCLK)
to allow for slow rise time signals.

2.1 Theory of Operation

The CS5460 is designed to operate from a single
+5 V supply or dual ±2.5 V supplies, to provide a
30mV
channel and to provide a 150 mV
voltage channel. With single supply, the CS5460 is
designed to accommodate common mode signals
of -0.25 V to VA+.

Figure 3 illustrates the CS5460 connected to a ser­vice to measure power in a single-phase 2-wire sys­tem while operating in a single supply
configuration. Figure 4 illustrates the CS5460 con-

or 150 mV

RMS

range for the current

RMS

range for the

RMS

figured to measure power in a single-phase 3-wire
system.

2.2 Performing Measurements

The CS5460 performs measurements of instanta­neous current, instantaneous voltage, instantaneous
power, energy, RMS current, and RMS voltage.
These measurements are output as 24-bit signed
and unsigned data formats as a percentage of full
scale. The flow of data to per form these calcula­tions is shown in Figure 5. All of these measure­ments begin when a start conversion command is
given. The energy and RMS registers are then up­dated every N conversions (or 1 computation cy­cle) where N is the content of the Cycle Count
register. After the computation cycle has finished,
the DRDY bit in the Status and Mask register is set.
The INT pin will also become active if the DRDY
bit is unmasked.

Table 1 provides an example detailing the output
linearity. A computation cycle is derived from the
master clock and its frequency is
(MCLK/K)/(1024*N). Instantaneous calculations
are performed at a 4000 Hz rate where as, I
V

, and energy, are performed at a 1 Hz rate.

RMS

Also, DRDY is set only after computation cycles
are complete (i.e. there is no indicator flag to indi­cate when the instantaneous conversions are read;
however, if the Cycle Count register were set to 1,
all output calculations would be instantaneous and
DRDY would indicate when instantaneous calcula­tions were finished).

Energy Vrms Irms

Range

Max Input

Linearity

(After

Calibration)

Output word

Table 1. Specificati o n wi t h MC LK = 4.0 9 6 MH z, K = 1 ,

1000:1 2:1 500:1

See

Analog Characteristics

0.1% of
reading

and N = 4000.

0.1% of
reading

24-bits

RMS

0.1% of
reading

,

DS279PP6 9

N

R

2

To Service

CS5460

5k

Ω

L

470 nF

500

Ω

500

Ω

0.1 µF100 µF

Ω

10

0.1 µF

14

3

VA+ VD+

CS5460

17

9

VIN+

*

CP

V

R

1

10

VIN-

15

IIN-

R

S

*

RP

I

CP

0.1 µF

16

12

11

IIN+

VREFIN
VREFOUT

*

I

VA- DGND

PFMON

CPUCLK

XOUT

XIN

RESET

CS

SDI

SDO

SCLK

INT

EDIR

EOUT

2
1

24

19
7
23
6
5
20
22

21

13 4

* Refer to Input Current Protection

2.5 MHz to
20 MHz

10 k

Ω

Optional

Clock

Source

Serial

Data

Interface

Figure 3. Typical Connection Diagram (One-Phase 2-Wire)

5k

Ω

N

L

1

R

1

To Service

L

2

R

2

Ω

500

470 nF

* Refer to Input Current Protection

500

Ω

R

RP

S

0.1 µF

Ω

10

XIN

CS

SDI

SDO

INT

EDIR

0.1 µF

3

17
2
1

24

19
7
23
6
5
20

22
21

0.1 µF100 µF

14

VA+ VD+

CS5460

VA-

13 4

PFMON

CPUCLK

XOUT

RESET

SCLK

EOUT

DGND

9

VIN+

*

CP

V

10

VIN-

16

CP

*

I

15

12
11

IIN+

IIN-

VREFIN
VREFOUT

*

I

2.5 MHz to
20 MHz

Interface

10 k

Ω

Optional

Clock

Source

Serial

Data

Figure 4. Typical Connection Diagram (One-Phase 3-Wire)

10 DS279PP6

V *

off

V *

gn

CS5460

V*

VOLTAGE

CURRENT

∆Σ

∆Σ

DELAY

REG

SINC

SINC

DELAY

2

REG

Config uration R egiste r *

PC[3:0] Bits

4

FIR

FIR

HPF

APF

HPF

APF

Figure 5. Data Flow.

2.2.1 Single Computation Cycle (C = 0)

Based on the information provided in the Cycle
Count register, a single computation cycle is per­formed after the user transmits the single conver­sion cycle command. After the computations are
complete, DRDY is set. Thirty-two SCLKs are
then needed to acquire a calculation result. The first
8 SCLKs are used to clock in the command to de­termine which result register is to be read. The last
24 SCLKs are needed to read the desired calcula­tion result register. After reading the data, the serial
port returns to the command mode, where it waits
for a new command to be issued.

2.2.2 Multiple Computation Cycles (C = 1)

Based on the information provided in the Cycle
Count register, continuous computation cycles are
repeatedly performed on the voltage and current
cycles. Computation cycles cannot be start­ed/stopped on a per channel basis. After each com­putation cycle is completed, DRDY is set.
Thirty-two SCLKs are then needed to read a regis­ter. The first 8 SCLKs are used to clock in the com­mand to determine which results register is to be
read. The last 24 SCLKs ar e needed to re ad the cal­culation result. While in this mode, the user may

V *

RMS

E *

E

out

E

dir

I *

RMS

I *

off

N

+

x

x x

x

+

I *

gn

x

x

I *

* DENOTES REGISTER NAME

2

SINC

TBC *

N

Σ

P *

2

SINC

E to F

N

÷

4096

PULSE-RATE*

choose to acquire only the calculations required for
the application as DRDY rises and falls to indicate
the availability of a new data.

The RMS calculations require a Sinc2 operation
prior to their square root operation. Therefore, the
first output for each channel will be invalid (i.e. all
RMS calculations are invalid in the single compu­tation cycle routine and the first RMS calculations
will be invalid in the continuous computation cy­cle). All energy calculations will be valid since en-

ergy calculations don’t require this Sinc2 operation.

2.3 High Rate Digital Filters

The high rate filter on the voltage channel is imp le­mented as a fixed sinc2 filter, compensated by a
short length FIR. When the converter is driven with
a 4.096 MHz clock (K=1), the filter has a magni­tude response similar to that shown in Figure 6.
Note that the filter’s response scales with MCLK
frequency and K.

The current channel contains a sinc4 filter, com pen­sated by a short length FIR. When the converter is
driven with a 4.096 MHz clock (K=1) the compos­ite filter response is given in Figure 7.

DS279PP6 11