Cirrus Logic CS53L32A-KZ, CS53L32A Datasheet
CS53L32A
Low Voltage, Stereo A/D Converter
Features
20-Pin TSSOP package
1.8 to 3.3 volt supply
24-bit conversion / 96 kHz sample rate
98 dB dynamic range at 3 V supply
-88 dBFS THD+N
Low power consumption
– 9.7 mW at 1.8 V
Up to 32 dB gain
–20dBgainstep
– 12 dB variable input gain, 1 dB steps
– Changes made at zero crossings
Stereo inputs
Digital volume control
– 96 dB attenuation, 1 dB step size
–Mute
– Soft ramping
2:1 input mux
II
Description
The CS53L32A is a highly integrated, 24-bit, 96 kHz audio ADC providing stereo analog-to-digital converters
using delta-sigma conversion techniques. This device includes volume control and line level inputs in a 20-pin
TSSOP package.
The CS53L32A is based on delta-sigma modulation allowing infinite adjustment of the sample rate between
2 kHz and 100 kHz simply by changing the master clock
frequency.
The CS53L32A contains adjustable analog gain, a 2:1
input mux, and digital attenuation.
The CS53L32A operates from a +1.8 V to +3.3 V supply.
These features are ideal for portable MP3 players, MD
recorders/players, digital camcorders, PDAs, set-top
boxes, and other portable systems that require extremely low power consumption in a minimum of space.
ORDERING INFORMATION
CS53L32A-KZ 20-pinTSSOP, -10to70°C
CDB53L32A Evaluation Board
SCL/CCLK/ SDA/CDIN/DIF
RST
VA
VL
Serial Port
Attenuator
0-96 dB
Attenuator
0-96 dB
GND VQ
LRCK
SCLK
SDOUT
Preliminary Product Information
Cirrus Logic, Inc.
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
ChSEL
Control Port
Digital
Filters
MCLK
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
ADC
ADC
FILT+ RE F_GND
CopyrightCirrus Logic, Inc. 2002
AD0/CS/DIV
Gain
Gain
AFLTL AFLTR
(All Rights Reserved)
AIN_L 1
AIN_L2
AIN_R1
AIN_R2
JUL ‘00
DS513PP1
1
TABLE OF CONTENTS
1. CHARACTERISTICS/SPECIFICATIONS .................................................................................5
ANALOG CHARACTERISTICS ................................................................................................ 5
ANALOG CHARACTERISTICS ................................................................................................ 6
POWER AND THERMAL CHARACTERISTICS....................................................................... 7
DIGITAL CHARACTERISTICS................................................................................................. 8
ABSOLUTE MAXIMUM RATINGS ........................................................................................... 8
RECOMMENDED OPERATING CONDITIONS ....................................................................... 8
SWITCHING CHARACTERISTICS .......................................................................................... 9
SWITCHING CHARACTERISTICS - CONTROL PORT - TWO WIRE MODE....................... 11
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE.................................... 12
2. TYPICAL CONNECTION DIAGRAM .................................................................................... 13
3. REGISTER QUICK REFERENCE ..........................................................................................14
3.1 I/O and Power Control (address 01h) ............................................................................... 14
3.2 Interface Control (address 02h) ........................................................................................ 14
3.3 Analog I/O Control (address 03h) ..................................................................................... 15
3.4 Left Channel Digital Volume Control (address 04h).......................................................... 16
3.5 Right Channel Digital Volume Control (address 05h) .......................................................16
3.6 Analog Gain Control (address 06h) .................................................................................. 16
3.7 Clip Detection Status (address 07h) ................................................................................. 16
4. REGISTER DESCRIPTION .................................................................................................... 17
4.1 Gain Enable ...................................................................................................................... 17
4.2 Analog Input Multiplexer ................................................................................................... 17
4.3 Power-Down ..................................................................................................................... 18
4.4 Control Port Enable........................................................................................................... 18
4.5 Master Clock Divide.......................................................................................................... 19
4.6 Master Clock Ratio............................................................................................................ 19
4.7 Master Mode..................................................................................................................... 20
4.8 Digital Interface Format..................................................................................................... 20
4.9 Left/Right Channel Mute ................................................................................................... 21
4.10 Soft Ramp and Zero Cross Enable ................................................................................. 21
4.11 Independent Volume Control Enable .............................................................................. 22
4.12 Left Channel Volume = Right Channel Volume .............................................................. 23
4.13 High-Pass Filter Freeze .................................................................................................. 23
4.14 Volume Control ...............................................................................................................24
4.15 Left/Right Analog Gain.................................................................................................... 25
CS53L32A
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts/
I2C is a r egistered trademark of Philips Semiconductors.
Preliminary product i nformation describes products which are in production, but for which full characterization data is not yet availabl e. Advance product information describes products which are in development and subject to development changes. Cir rus Logic, Inc. has made best efforts to ensure that the information
contained in this document is accurate and reli able. However, the information i s subject to change without notice and is provided “AS IS” without warranty of
any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this i nformation, nor for i nfri ngements of patents or other rights
of third parties. This document is the property o f Ci rrus Logic, Inc. and implies no license under patents, copyrights, t rademarks, or trade secr ets. No part of
this publication may be copied, reproduced, stored in a retrieval system, or transmitted, i n any form or by any means (electronic, mechanical, photographic, or
otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no
part of the print out or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical,
photographic, or otherwise) wi thout the prior written consent of Cirrus Logic, Inc.Furthermore, no part of thi s publication may be used as a basis for manufacture
or sale of any items without the pri or written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appeari ng
in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.
Preliminary Product Information
2 DS513PP1
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Cirrus Logic reserves the right to modify this product without notice.
CopyrightCirrusLogic,Inc.2002
(All Rights Reserved)
4.16 Clip Detection ................................................................................................................. 25
5. PIN DESCRIPTION ................................................................................................................. 26
6. PIN DESCRIPTION ................................................................................................................. 26
6. PIN DESCRIPTION ................................................................................................................. 26
6. APPLICATIONS ..................................................................................................................... 29
6.1 Grounding and Power Supply Decoupling ....................................................................... 29
6.2 Oversampling Modes ....................................................................................................... 29
6.3 Recommended Power-up Sequence ............................................................................... 29
7. CONTROL PORT INTERFACE ............................................................................................. 29
7.1 SPI Mode ......................................................................................................................... 29
7.2 Two Wire Mode ............................................................................................................... 29
7.3 Memory Address Pointer (MAP)....................................................................................... 30
8. PARAMETER DEFINITIONS .................................................................................................. 36
9. REFERENCES ........................................................................................................................ 36
10. PACKAGE DIMENSIONS .................................................................................................... 37
LIST OF FIGURES
Figure 1. SCLK to LRCK and SDATA, Slave Mode...................................................................... 10
Figure 2. SCLK to LRCK and SDATA, Master Mode.................................................................... 10
Figure 3. Control Port Timing - Two Wire Mode............................................................................ 11
Figure 4. Control Port Timing - SPI Mode ..................................................................................... 12
Figure 5. Typical Connection Diagram.......................................................................................... 13
Figure 6. Control Port Timing, SPI Mode ...................................................................................... 31
Figure 7. Control Port Timing, Two Wire Mode............................................................................. 31
Figure 8. Base-Rate Stopband Rejection...................................................................................... 32
Figure 9. Base-Rate Transition Band............................................................................................ 32
Figure 10. Base-Rate Transition Band (Detail) ............................................................................. 32
Figure 11. Base-Rate Passband Ripple........................................................................................ 32
Figure 12. High-Rate Stopband Rejection .................................................................................... 32
Figure 13. High-Rate Transition Band........................................................................................... 32
Figure 14. High-Rate Transition Band (Detail) .............................................................................. 33
Figure 15. High-Rate Passband Ripple......................................................................................... 33
Figure 16. Line Input Test Circuit.................................................................................................. 33
Figure 17. CS53L32A Control Port Mode - Serial Audio Format 0 (I
Figure 18. CS53L32A Control Port Mode - Serial Audio Format 1 ............................................... 34
Figure 19. CS53L32A Control Port Mode - Serial Audio Format 3 ............................................... 34
Figure 20. CS53L32A Control Port Mode - Serial Audio Format 4 ............................................... 34
Figure 21. CS53L32A Control Port Mode - Serial Audio Format 5 ............................................... 34
Figure 22. CS53L32A Control Port Mode - Serial Audio Format 6 ............................................... 35
Figure 23. CS53L32A Stand-Alone Mode - Serial Audio Format 0 (I
Figure 24. CS53L32A Stand-Alone Mode - Serial Audio Format 1............................................... 35
CS53L32A
2
S)....................................... 33
2
S) ...................................... 35
Preliminary Product Information
DS513PP1 3
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Cirrus Logic reserves the right to modify this product without notice.
CopyrightCirrus Logic, Inc. 2002
(All Rights Reserved)
LIST OF TABLES
Table 1. Analog Input Options .......................................................................................................17
Table 2. Power-Down Enable........................................................................................................ 18
Table 3. Control Port Enable......................................................................................................... 18
Table 4. Master Clock Divide Select ............................................................................................. 19
Table 5. MCLK/LRCK Ratios......................................................................................................... 19
Table 6. Master/Slave Mode Selection.......................................................................................... 20
Table 7. Digital Interface Format ...................................................................................................20
Table 8. Left/Right Channel Mute Enable ..................................................................................... 21
Table 9. Analog Volume Control ...................................................................................................22
Table 10. Digital Volume Control................................................................................................... 22
Table 11. Independent Volume Control Enable ............................................................................ 22
Table 12. High-Pass Filter Enable................................................................................................. 23
Table 13. Example Volume Settings ............................................................................................. 24
Table 14. Example Gain Settings.................................................................................................. 25
Table 15. Clip Detection Status Bits.............................................................................................. 25
Table 16. Common Clock Frequencies ......................................................................................... 26
Table 16. Common Clock Frequencies ......................................................................................... 26
Table 16. Common Clock Frequencies ......................................................................................... 26
Table 17. Digital Interface Format - DIF (Stand-Alone Mode) ....................................................... 27
Table 18. Channel Select Options................................................................................................. 27
CS53L32A
Preliminary Product Information
4 DS513PP1
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Cirrus Logic reserves the right to modify this product without notice.
CopyrightCirrusLogic,Inc.2002
(All Rights Reserved)
1. CHARACTERISTICS/SPECIFICATIONS
CS53L32A
ANALOG CHARACTERISTICS (T
GND = 0 V; MCLK = 12.288 MHz; Fs for Base-rate Mode = 48 kHz, SCLK = 3.072 MHz, Measurement Bandwidth
10 Hz to 20 kHz, unless otherwise specified; Fs for High-Rate Mode = 96 kHz, SCLK = 6.144 MHz, Measurement
Bandwidth 10 Hz to 20 kHz, unless otherwise specified.)
Parameter Symbol
Analog Input Characteristics for VA = 1.8 V
Dynamic Range A-weighted
unweighted
Total Harmonic Distortion + Noise (Note 1)
18 to 24-Bit -1 dB
-20 dB
-60 dB
16-Bit -1 dB
-20 dB
-60 dB
Dynamic Range (PGA on)*
0dBGain
A-weighted
unweighted
12 dB Gain
A-weighted
unweighted
Total Harmonic Distortion + Noise (PGA on)*
(Note 1) 0 dB Gain
18 to 24-Bit -1 dB
12 dB Gain
18 to 24-Bit -1 dB
Interchannel Isolation 1 kHz - 90 - - 90 - dB
Interchannel Gain Mismatch - 0.1 - - 0.1 - dB
Offset Error with High Pass Filter
HPF frozen with HPFREEZE
Analog Input Characteristics for VA = 3.0 V
Dynamic Range A-weighted
unweighted
Total Harmonic Distortion + Noise (Note 1)
18 to 24-Bit -1 dB
-20 dB
-60 dB
16-Bit -1 dB
-20 dB
-60 dB
*PGA : Programmable Gain Amplifier
= 25° C; GND = 0 V Logic "1" = VL = 1.8 V; Logic "0" =
A
Base-rate Mode High-rate Mode
TBD
TBD
THD+N
-
-
-
-
-
-
-
-
-
-
THD+N
-
-
-
-
TBD
TBD
THD+N
-
-
-
-
-
-
93
90
-88
-70
-30
-86
-68
-28
90
87
85
82
85
83
-
TBD
96
93
-88
-73
-33
-86
-68
-28
-
-
TBD
-
-
-
-
-
-
-
-
-
-
-
0
-
-
-
TBD
-
-
-
-
-
TBD
TBD
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TBD
TBD
-
-
-
-
-
-
94
91
-88
-71
-31
-86
-68
-28
89
86
86
83
84
82
-
TBD
98
95
-85
-75
-35
-83
-65
-28
-
-
TBD
-
-
-
-
-
-
-
-
-
-
-
0
-
-
-
TBD
-
-
-
-
-
UnitMin Typ Max Min Typ Max
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
LSB
dB
dB
dB
dB
dB
dB
dB
dB
Note: 1. Referenced to typical full-scale differential input voltage (0.5 Vrms).
Preliminary Product Information
DS513PP1 5
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Cirrus Logic reserves the right to modify this product without notice.
CopyrightCirrus Logic, Inc. 2002
(All Rights Reserved)
ANALOG CHARACTERISTICS (CONTINUED)
CS53L32A
Base-rate Mode High-rate Mode
Parameter Symbol
Total Harmonic Distortion + Noise (PGA on)*
(Note 1)
0dBGain
18 to 24-Bit -1 dB
12 dB Gain
18 to 24-Bit -1 dB
Interchannel Isolation 1 kHz - 90 - - 90 - dB
Interchannel Gain Mismatch - 0.1 - - 0.1 - dB
Offset Error with High Pass Filter
HPF frozen with HPFREEZE
Full Scale Input Voltage TBD VA/3.6 TBD TBD VA/3.6 TBD Vrms
Gain Drift - 100 - - 100 - ppm/°C
Input Resistance 10 - - 10 - - kΩ
Input Capacitance - - 15 - - 15 pF
Programmable Gain Characteristics
Gain Step Size - 1.0 - - 1.0 - dB
Absolute Gain Step Error - - TBD - - TBD dB
A/D Decimation Filter Characteristics (Note 2)
Passband (Note 3) 0 - 23.5 0 - 47.5 kHz
Passband Ripple -0.08 - +0.17 -0.09 - 0 dB
Stopband (Note 3) 27.5 - - 64.1 - - kHz
Stopband Attenuation (Note 4) -60.3 - - -48.4 - - dB
Group Delay (Fs = Output Sample Rate) (Note 5) t
Group Delay Variation vs. Frequency ∆t
THD+N
gd
gd
-
-
-
-
- 10/Fs - - 2.7/Fs - s
- - 0.03 - - 0.007µs
78
73
-
TBD
-
-
0
-
-
-
-
-
77
76
-
TBD
UnitMin Typ Max Min Typ Max
-
dB
-
dB
0
LSB
-
High Pass Filter Characteristics
Frequency Response -3 dB (Note 3)
-0.1 dB
Phase Deviation @ 20 Hz (Note 3) - 10 - - 10 - Degree
Passband Ripple (Note 2) - - 0.17 - - 0.09 dB
*PGA : Programmable Gain Amplifier
Notes: 2. Filter response is not tested but is guaranteed by design.
3. Filter characteristics scale with output sample rate. For output sample rates, Fs, other than 48 kHz, the
0.01 dB passband edge is 0.4535x Fs and the stopband edge is 0.625x Fs.
4. The analog modulator samples the input at 6.144 MHz for an Fs equal to 48 kHz. There is no rejection
of input signals which are multiples of the sampling frequency ( n x 6.144 MHz ±21.8 kHz where
n = 0,1,2,3...).
5. Group delay for Fs = 48 kHz, t
Preliminary Product Information
6 DS513PP1
= 15/48 kHz = 312 µs.
gd
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
CopyrightCirrusLogic,Inc.2002
(All Rights Reserved)
-
3.7
-
24.2
-
-
-
3.7
-
24.2
-
Hz
-
Hz
CS53L32A
POWER AND THERMAL CHARACTERISTICS
Base-rate Mode High-Rate Mode
Parameters Symbol Min Typ Max Min Typ Max Units
Power Supplies
-
Power Supply Current- VA=1.8 V
Normal Operation VL=1.8 V
I
Power Supply Current- VA=1.8 V
Power Down Mode (Note 6) VL=1.8 V
I
Power Supply Current- VA=3.0 V
Normal Operation VL=3.0 V
I
Power Supply Current- VA=3.0 V
Power Down Mode VL=3.0 V
I
Total Power Dissipation- All Supplies=1.8 V
Normal Operation All Supplies=3.0 V
Package Thermal Resistance θ
Power Supply Rejection Ratio (1 kHz)
PSRR -
(Note 7) (60 Hz)
I
A
D_IO
I
A
D_IO
I
A
D_IO
I
A
D_IO
JA
6.0
-
150
-
100
-
-
-
-
-
-
-
0
9
260
250
0
11
28
-75- -75-°C/Watt
60
-
40
Chip Power
Analog/Digital Converter - 11 - - 14.5 - mA
A/D Converter & Programmable Gain Amplifier - 13 - - 16.5 - mA
-
-
-
-
-
-
-
-
TBD
TBD
-
-
-
-
-
-
-
-
-
-
-
-
-
-
7.6
300
250
0
11.5
520
500
0
-
-
-
-
-
-
-
-
14.536TBD
TBDmWmW
60
40
-
-
mA
µA
µA
µA
mA
µA
µA
µA
dB
dB
Notes: 6. Power Down Mode is defined as the chip being held in reset with MCLK being applied. To lower power
consumption further, remove MCLK.
7. Valid with the recommended capacitor values on FILT+ and VQ as shown in Figure 5.
Preliminary Product Information
DS513PP1 7
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Cirrus Logic reserves the right to modify this product without notice.
CopyrightCirrus Logic, Inc. 2002
(All Rights Reserved)
CS53L32A
DIGITAL CHARACTERISTICS (T
= 25° C; VL = 1.7 V - 3.6 V; GND = 0 V)
A
Parameters Symbol Min Typ Max Units
High-Level Input Voltage
Low-Level Input Voltage
High-Level Output Voltage V
Low-Level Output Voltage V
Leakage Current I
V
IH
V
IL
OH
OL
in
0.7•VL - - V
- - 0.3•VL V
0.7•VL - - V
- - 0.3•VL V
--±10µA
Input Capacitance - 8 - pF
ABSOLUTE MAXIMUM RATINGS (GND = 0 V; all voltages with respect to ground.)
Parameters Symbol Min Max Units
DC Power Supplies: Positive Analog
Digital I/O
Input Current, Any Pin Except Supplies I
Digital Input Voltage V
Ambient Operating Temperature (power applied) T
Storage Temperature T
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is
not guaranteed at these extremes.
VA
VL
IND
stg
-0.3
-0.3
in
-±10mA
4.0
4.0
V
V
-0.3 VL+0.4 V
A
-55 125 °C
-65 150 °C
RECOMMENDED OPERATING CONDITIONS (GND = 0V; all voltages with respect to ground.)
Parameters Symbol Min Typ Max Units
Ambient Temperature T
DC Power Supplies: Positive Analog
Digital I/O
A
VA
VL
-10 - 70 °C
1.7
1.7
-
-
3.6
3.6
V
V
Preliminary Product Information
8 DS513PP1
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CopyrightCirrusLogic,Inc.2002
(All Rights Reserved)
CS53L32A
1
SWITCHING CHARACTERISTICS (T
Logic 1 = VL, C
=20pF)
L
= -10 to 70° C; VA = 1.7 V - 3.6 V; Inputs: Logic 0 = GND,
A
Parameters Symbol Min Typ Max Units
Input Sample Rate Base Rate Mode
High Rate Mode
Fs
Fs
2
50
-
-
50
100
kHz
kHz
MCLK Pulse Width High MCLK/LRCK = 1024 8 - - ns
MCLK Pulse Width Low MCLK/LRCK = 1024 8 - - ns
MCLK Pulse Width High MCLK/LRCK = 768 10 - - ns
MCLK Pulse Width Low MCLK/LRCK = 768 10 - - ns
MCLK Pulse Width High MCLK/LRCK = 512 15 - - ns
MCLK Pulse Width Low MCLK/LRCK = 512 15 - - ns
MCLK Pulse Width High MCLK / LRCK = 384 or 192 21 - - ns
MCLK Pulse Width Low MCLK / LRCK = 384 or 192 21 - - ns
MCLK Pulse Width High MCLK / LRCK = 256 or 128 31 - - ns
MCLK Pulse Width Low MCLK / LRCK = 256 or 128 31 - - ns
Master Mode
SCLK Falling to LRCK Edge t
SCLK Falling to SDATA Valid t
slrd
sdo
-20 - 20 ns
0 - 20 ns
SCLK Duty Cycle 40 50 60 %
Slave Mode
LRCK Duty Cycle 40 50 60 %
SCLK Pulse Width Low t
SCLK Pulse Width High t
SCLK Period Base Rate Mode
High Rate Mode
SCLK Falling to LRCK Edge t
SCLK Falling to SDATA Valid Base Rate Mode
High Rate Mode
sclkl
sclkh
t
sclkw
t
sclkw
slrd
t
dss
t
dss
20 - - ns
20 - - ns
1
--------- ------------128()Fs
1
--------- ---------
64()Fs
-
-
-
-
-20 - 20 ns
-
-
-
(512)Fs
-
1
(256)Fs
ns
ns
ns
ns
Preliminary Product Information
DS513PP1 9
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CopyrightCirrus Logic, Inc. 2002
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CS53L32A
SCLK
LRCK
SDATA
SCLK
t
sclkh
t
sclkl
t
slrd
t
dss
MSB
Figure 1. SCLK to LRCK and SDATA, Slave Mode
t
sclkw
t
slrd
LRCK
t
sdo
SDATA
MSB MSB-1
Figure 2. SCLK to LRCK and SDATA, Master Mode
Preliminary Product Information
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CS53L32A
SWITCHING CHARACTERISTICS - CONTROL PORT - TWO WIRE MODE
(TA= 25° C; VL = 1.7 V - 3.6 V; Inputs: logic 0 = GND, logic 1 = VL, CL=30pF)
Parameter Symbol Min Max Unit
Two Wire Mode
SCL Clock Frequency f
RST
Rising Edge to Start t
Bus Free Time Between Transmissions t
Start Condition Hold Time (prior to first clock pulse) t
Clock Low time t
Clock High Time t
Setup Time for Repeated Start Condition t
SDA Hold Time from SCL Falling (Note 8) t
SDA Setup time to SCL Rising t
Rise Time of Both SDA and SCL Lines t
Fall Time of Both SDA and SCL Lines t
Setup Time for Stop Condition t
scl
irs
buf
hdst
low
high
sust
hdd
sud
r
f
susp
Note: 8. Data must be held for sufficient time to bridge the transition time, t
RST
t
irs
Stop S tart
Repeated
Start
- 100 KHz
500 - ns
4.7 - µs
4.0 - µs
4.7 - µs
4.0 - µs
4.7 - µs
0-µs
250 - ns
-25ns
-25ns
4.7 - µs
,ofSCL.
f
Stop
SDA
SCL
t
buf
t
t
hdst
low
t
hdd
t
high
t
sud
t
sust
t
hdst
t
f
t
r
t
susp
Figure 3. Control Port Timing - Two Wire Mode
Preliminary Product Information
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Cirrus Logic reserves the right to modify this product without notice.
CopyrightCirrus Logic, Inc. 2002
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SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE
(TA=25°C; VL = 1.7V - 3.6V; Inputs: logic 0 = GND, logic 1 = VL, CL=30pF)
Parameter Symbol Min Max Unit
SPI Mode
CCLK Clock Frequency f
Rising Edge to CS Falling t
RST
CCLK Edge to CS
High Time Between Transmissions t
CS
Falling to CCLK Edge t
CS
Falling (Note 9) t
CCLK Low Time t
CCLK High Time t
CDIN to CCLK Rising Setup Time t
CCLK Rising to DATA Hold Time (Note 10) t
Rise Time of CCLK and CDIN (Note 11) t
Fall Time of CCLK and CDIN (Note 11) t
sclk
srs
spi
csh
css
scl
sch
dsu
dh
r2
f2
-6MHz
500 - ns
500 - ns
1.0 - µs
20 - ns
66 - ns
66 - ns
40 - ns
15 - ns
- 100 ns
- 100 ns
CS53L32A
Notes: 9. t
10. Data must be held for sufficient time to bridge the transition time of CCLK.
11. For F
only needed before first falling edge of CS after RST rising edge. t
spi
<1MHz.
SCLK
RST
CS
CCLK
CDIN
t
t
srs
spi
t
css
t
r2
t
t
scl
t
t
f2
dsu
sch
t
dh
Figure 4. Control Port Timing - SPI Mode
= 0 at all other times.
spi
t
csh
Preliminary Product Information
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