Cirrus Logic CS5397-KS, CS5397, CS5396-KS, CS5396 Datasheet

CS5396 CS5397

120 dB, 96 kHz Audio A/D Converter

Features

l 24-Bit Conversion l 120 dB Dynamic Range (A-Weighted) l Low Noise and Distortion

>105 dB THD + N

l Complete CMOS Stereo A/D System

Delta-Sigma A/D Converters Digital Anti-Alias Filtering S/H Circuitry and Voltage Reference

l CS5396 - digita l filter optimized for audio l CS5397 - non-aliasing digital filter l Adjustable System Sampling Rates

including 32, 44.1, 48 & 96 kHz

l Differential Analog Architecture l Linear Phase Digital Anti-Alias Filtering l 10 Tap Programmable Psychoacoustic Noise

Shaping Filter

l Single +5 V Power Supply

General Description

The CS5396 and CS5397 are complete analog-to-digital converters for stereo digital audio systems. They perform sampling, analog-to-digital conversion and antialias filtering, gener ating 24-bit values for both left and right inputs in ser ial form a t sa mple rate s up to 1 00 kHz per channel.

The CS5396/97 use a patented 7th-order, tri-level deltasigma modulator followed by digital filtering and decimation, which removes the need for an external anti-alias filter. The ADCs use a differential architecture which provides excellent noise rejection.

The CS5396 has a linear phase filter optimized for audio

applications with ±0.005 dB passband ripple and >117 dB stopband rejection. The CS5397 has a nonaliasing filter respo nse with ±0.005 passband rippl e an d >117 dB stopband attenuation. Other fea tures a vail able in both the CS5396 and CS5397 are an optional low group delay filter and a unique psychoacoustic noise shaping filter which s ubjectively truncates the output to 16, 18 or 20 bits while 24-bit sound quality is preserved.

The CS5396/97 are targeted for the highest performance professional audio systems requiring wide dynamic range, negligible distortion and low noise.

VCOM MCLKA LRCKADCTL

VREF

AINL-

AINL+

AINR-

AINR+

Voltage Referen ce

S/H

AGND1 AGND2 AGND0 VL TST1 VD DGND

Preliminary Product Information

Cirrus Logic, Inc. Crystal Semiconductor Products Division

P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.crystal.com

ORDERING INFORMATION

CS5396-KS -10° to 50° C 28-pin SOIC CS5397-KS -10° to 50° C 28-pin SOIC CDB5396/97 Evaluation Board

SCLK SDAT A1 MCLKD

DACTL

CAL SDAT A2

Serial Output Interface

LP Filter

DAC

LP Filter

DAC

Comparator

LGND TST0

Digital Decimation

Filter

(with Low Group

Delay Options)

Digital Decimation

Filter

(with Low Group

Delay Options)

Calibration

Microcontroller

This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.

Serial

Control

Port

Psychoacoustic

Filter

Calibration

SRAM

CDIN CCLK

SEP ‘97

DS229PP2

TABLE OF CONTENTS.......................................................................................................2

ANALOG CHARACTERISTICS ..........................................................................................4

DIGITAL FILTER CHARACTERISTICS..............................................................................5

POWER AND THERMAL CHARACTERISTICS.................................................................6

DIGITAL CHARACTERISTICS............................................................................................6

ABSOLUTE MAXIMUM RATINGS......................................................................................6

RECOMMENDED OPERATING CONDITIONS ..................................................................7

SWITCHING CHARACTERISTICS .....................................................................................7

SPI CONTROL PORT SWITCHING CHARACTERISTICS.................................................9

I2C CONTROL PORT SWITCHING CHARACTERISTICS...............................................10

GENERAL DESCRIPTION ...............................................................................................12

Stand-Alone vs. Control Port Mode ........................................................................12

STAND-ALONE MODE ....................................................................................................12

Master Clock - Stand-Alone Mode ..........................................................................12

Serial Data Interface - Stand-Alone Mode ..............................................................12

Serial Data- Stand-Alone Mode .......................................................................13

Serial Clock - Stand-Alone Mode ....................................................................13

Left/Right Clock - Stand-Alone Mode ..............................................................13

Master Mode - Stand-Alone Mode ..........................................................................13

Slave Mode - Stand-Alone Mode ............................................................................13

High Pass Filter - Stand-Alone Mode .....................................................................13

Power-up and Calibration - Stand-Alone Mode ......................................................13

Synchronization of Multiple Devices - Stand Alone Mode ......................................14

CONTROL PORT MODE ..................................................................................................14

Access to Control Port Mode ..................................................................................14

Internal Power-On Reset .................................................. ...... ..... ...... ..... .........14

Master Clock - Control Port Mode ..........................................................................15

64× vs. 128× Oversampling Modes ........................................................................15

Serial Data Interface - Control Port Mode ..............................................................15

Serial Data - Control Port Mode ......................................................................15

Serial Clock - Control Port Mode .....................................................................15

Left/Right Clock -Control Port Mode ................................................................15

Master Mode- Control Port Mode ...........................................................................17

Slave Mode - Control Port Mode ............................................................................17

Synchronization of Multiple Devices - Control Port Mode ......................................17

Power-up and Calibration - Control Port Mode .......................................................17

High Pass Filter -Control Port Mode .......................................................................17

Input Level Monitoring - Control Port Mode ............................................................18

High Resolution Mode .....................................................................................18

Bar Graph Mode ..............................................................................................18

Dual Digital Audio Outputs .....................................................................................18

Psychoacoustic Filter ..............................................................................................19

Low Group Delay Filter ...........................................................................................19

µC Interface Formats ..............................................................................................19

SPI Mode ................................... ..... ...... ...... ..... ....................................... .........19

C Mode .........................................................................................................19

Establishing the Chip Address in I

ANALOG CONNECTIONS - ALL MODES .......................................................................19

GROUNDING AND POWER SUPPLY DECOUPLING - ALL MODES ............................20

DIGITAL FILTER PLOTS .................................................................................................21

PIN DESCRIPTIONS ........................................................................................... ..............31

Power Supply Connections.....................................................................................31

Analog Inputs...........................................................................................................31

Analog Outputs........................................................................................................32

Digital Inputs............................................................................................................32

CS5396 CS5397

C Mode ....................................................19

2 DS229PP2

CS5396 CS5397

Digital Input Pin Definitions for Stand-Alone MODE............................................... 32

Digital Pin Definitions for CONTROL-PORT MODE................................................33

Digital Outputs.........................................................................................................33

Digital Inputs or Outputs..........................................................................................34

Miscellaneous .........................................................................................................34

PARAMETER DEFINITIONS.............................................................................................35

ADDITIONAL INFORMATION.......................... ........................................ .........................36

PACKAGE DIMENSIONS .................................................................................................37

DS229PP2 3

CS5396 CS5397

ANALOG CHARACTERISTICS (T

Analog connections as shown in Figure 1; Measurement Bandwidth is 20 Hz to 20 kHz unless otherwise specified; Logic 0 = 0V, Logic 1 = VD;

Parameter Symbol Min Typ Max Units

Dynamic Performance

Dynamic Range MCLK equal to 24.576 MHz Fs = 48 kHz in 128x Oversampling Mode (A-weighted) Fs = 48 kHz in 128x mode Fs = 96 kHz in 64x mode (A-weighted) Fs = 96 kHz in 64x mode (40 kHz Bandwidth)

MCLK equal to 12.288 MHz Fs = 48 kHz in 64x mode (A-weighted) Fs = 48 kHz in 64x mode

Total Harmonic Distortion + Noise Fs = 48 kHz in 128x mode -1 dB (Note 1)

Fs = 96 kHz in 64x mode -1 dB (Note 1) (40 kHz bandwidth) -20 dB (Note 1)

Fs = 48 kHz in 64x mode -1 dB (Note 1)

Total Harmonic Distortion -1 dB (Note 1) THD TBD 0.00056 - % Interchannel Phase Deviation - 0.0001 - deg Interchannel Isolation - 120 - dB Dynamic Range Performance Drift (following calibration) - 0.05 - dB/°C

= 25°C; VA, VL,VD = 5V; Full-scale Input Sinewave, 997 Hz;

TBD

-20 dB (Note 1)

-60 dB (Note 1)

-20 dB (Note 1)

-60 dB (Note 1)

TBD TBD TBD

TBD TBD

THD+N

TBD TBD TBD TBD TBD TBD TBD TBD TBD

120 117 120 114

117 114

105

97 57

105

97 57

105

97 57

dB dB dB dB

dB dB

dB dB dB dB dB dB dB dB dB

dc Accuracy

Interchannel Gain Mismatch - 0.05 - dB Gain Error Gain Drift Offset Error (With high pass filter enabled) - 0 - LSB

5TBD%

100 - ppm/°C

Analog Input

Full-scale Differential Input Voltage (Note 2) Input Impedance Differential

Common-mode

Common-Mode Rejection Ratio CMRR - 82 - dB

TBD 4 TBD V

4.5

TBD

Ω

Notes: 1. Referenced to typical full-scale differential input voltage (4.0 Vpp).

2. Specified for a fully differential input ±{(AINR+)-(AINR-)}.The ADC accepts input voltages up to the analog supplies (VA and AGND). Full-scale outputs will be produced for differential inputs beyond VIN.

* Refer to Parameter Definitions at the end of this data sheet.

Specifications are subject to change without notice.

4 DS229PP2

CS5396 CS5397

DIGITAL FILTER CHARACTERISTICS (T

Parameter

Symbol Min Typ Max Min Typ Max Unit

= 25 °C; VA, VL,VD = 5V±5%; Fs = 48 kHz)

CS5396 CS5397

High-Performance Filter

Passband(-0.01 dB) 0 - 0.4604 0 - 0.3958 Fs Passband Ripple - Stopband 0.5542 - 63.45 0.4979 - 63.50 Fs Stopband Attenuation 117 - - 117 - - dB Group Delay (Fs = Output Sampl e Rate)

128x Oversampling Mode

64x Oversampling Mode

Group Delay Variation vs. Frequency

∆

34/Fs

--0.0--0.0

0.005 - -

34/Fs 34/Fs

0.005 dB

µ µ

Low Group Delay Filter

Passband(-0.01 dB)

128x Oversampling Mode

64x Oversampling Mode Passband Ripple - - 0.015 - - 0.015 dB Stopband

128x Oversampling Mode

64x Oversampling Mode Stopband Attenuation 86 - 86 - dB

Group Delay (Fs = Output Sampl e Rate) Group Delay Variation vs. Frequency

∆

0 0

0.646

0.323

- 10/Fs - - 10/Fs -

--0.0--0.0

0.375

0.18800

--127.35

63.68

0.646

0.323

0.375

0.188FsFs

--127.35

63.68FsFs

µ µ

High Pass Filter Characteristics

Frequency Response-3.0 dB (Note 3)

-0.036 dB (Note 3) Phase Deviation@ 20Hz (Note 3) - 5.3 - - 5.3 - Deg Passband Ripple - - 0 - - 0 dB

-1.820-

Hz Hz

s s

Notes: 3. Response shown is for Fs equal to 48 kHz. Filter characteristics scale with Fs.

DS229PP2 5

POWER AND THERMAL CHARACTERISTICS

(TA = 25 °C; VA, VL,VD = 5V±5%; Fs = 48 kHz; Master Mode)

CS5396 CS5397

Parameter

Power Supply Current VA+VL (Normal Operation) VD

Power Supply Current VA+VL (Power-Down Mode) VD

Power Consumption(Normal Op erati on) (Power-Down Mode)

64X oversampling

MCLK=12.288 MHz

Symbol Min Typ Max Min Typ Max Unit

15065TBD

TBD

2 2

107520TBD

128X oversampling

MCLK=24.576 MHz

160 125

3.5

TBD TBDmAmA

142533TBD-mW

mW Power Supply Rejection Ratio (1 kHz) PSRR - 65 - - 65 - dB Allowable Junction Temperature - - 135 - - 135

Junction to Ambient Thermal Impedance

DIGITAL CHARACTERISTICS (T

= 25 °C; VA, VL,VD = 5V±5%)

-45- -45-

C/W

Parameter Symbol Min Typ Max Units

High-Level Input Voltage Low-Level Input Voltage

High-Level Output Voltage at I Low-Level Output Voltage at I

Input Leakage Current

= -20 µAV

= 20 µAV

2.4 - - V

--0.8V

VD - 1.0 - - V

--0.4V

±10µ

ABSOLUTE MAXIMUM RATINGS (AGND, DGND = 0V, All voltages with respect to ground.)

Parameter Symbol Min Typ Max Units

DC Power Supplies: Analog

Logic

Digital

|VA - VD|

(Note 6)

|VA - VL|

(Note 6)

|VD - VL|

(Note 6) Input Current (Note 4) I Analog Input Voltage (Note 5) V Digital Input Voltage (Note 5) V Ambient Operating Temperature (Power Applied) T Storage Temperature T

Notes: 4. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause SCR

latch-up.

5. The maximum over/under voltage is limited by the input current.

6. Applies to normal operation. Greater differences during power up/down will not cause SCR latch-up. WARNING: Operation beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes.

VA VL

IND

stg

-0.3

AGND-0.7 - VA+0.7 V

+6.0 +6.0 +6.0

0.4

10 mA

V V V V V V

-0.3 - VD+0.7 V

-55 - +50 °C

-65 - +150 °C

6 DS229PP2

CS5396 CS5397

RECOMMENDED OPERATING CONDITIONS (AGND, DGND = 0V, all voltages with respect

to ground.)

Parameter Symbol Min Typ Max Unit s

DC Power Supplies: Positive Digital

Positive Logic

Positive Analog

|VA - VD|

(Note 6)

Ambient Operating Temperature (Power Applied)

Specifications are subject to change without notice.

VL VA

4.75

-10 - +50

5.0

5.25

0.4

V V V V

SWITCHING CHARACTERISTICS (T

Logic 1 = VA = VD; C

= 20 pF)

= 25 °C; VA = 5V±5%; Inputs: Logic 0 = 0V,

Parameter Symbol Min Typ Max Units

Output Sample Rate Fs 2 - 100 kHz MCLK Period MCLK Low MCLK High MCLK Fall Time

clkw

clkh

clkft

clkl

39.06 - 1950 ns 26 - - ns 26 - - ns

--8ns

Master Mode

SCLK falling to LRCK SCLK falling to SDATA valid

mslr

sdo

-20 - +20 ns

- - 20 ns

SCLK duty cycle - 50 - %

Slave Mode

LRCK Period 1/Fs 10 - 500

LRCK duty cycle - 50 - % SCLK Period SCLK Pulse Width Low SCLK Pulse Width High SCLK falling to SDATA valid LRCK edge to MSB valid SCLK rising to LRCK edge delay LRCK edge to rising SCLK setup time

sclkw

sclkl

clkh

dss

lrdss

slr1

slr2

4 x t 2 x t

clw clw

--ns

60 - - ns

--t

+ 20 ns - - ns

clw

+ 20 ns - - ns

clw

+ 20 ns ns

clw

+ 20 ns ns

clw

DS229PP2 7

CS5396 CS5397

SCLK output

mslr

SDATA

sdo

LRCK output

MSB MSB-1

SCLK to SDATA & LRCK - MASTER mode

Serial Data Format, Left Justified

SCLK output

mslr

SDATA

sdo

LRCK output

MSB

SCLK to SDATA & LRCK - MASTER mode

Serial Data Format, I

S compatible

SCLK input

LRCK input

SDATA

slr1tslr2

sclkh

lrdss

MSB MSB-1 MSB-2

SCLK to LRCK & SDATA - SLAVE mode

Serial Data Format, Left Justified

SCLK input

LRCK input

slr1tslr2

sclkh

sclkl

dss

sclkw

dss

8 DS229PP2

SDATA

SCLK to LRCK & SDATA - SLAVE mode

Serial Data Format, I

S compatible

MSB MSB-1

CS5396 CS5397

SPI CONTROL PORT SWITCHING CHARACTERISTICS (T

Inputs: Logic 0 = DGND, Logic 1 = VD; C

Parameter Symbol Min Max Unit

SPI Mode

CCLK Clock Frequency

High Time Between Transmissions

CS CS

Falling to CCLK Edge CCLK Low Time CCLK High Time CDIN to CCLK Rising Setup Time CCLK Rising to DATA Hold Time (Note 7) Rise Time of CCLK and CDIN (Note 8) Fall Time of CCLK and CDIN (Note 8)

Notes: 7. Data must be held for sufficient time to bridge the transition time of CCLK.

8. For F

< 1 MHz.

SCK

= 20 pF)

f t t

sck csh css

scl sch dsu

-6MHz

1.0 - µs 20 - ns 66 - ns 66 - ns 40 - ns 15 - ns

-100ns

= 25 °C; VD, VA = 5V ±5%;

CCLK

CDIN

css

tr2t

scl

dsu

sch

csh

DS229PP2 9

CS5396 CS5397

I2C CONTROL PORT SWITCHING CHARACTERISTICS (T

Inputs: Logic 0 = DGND, Logic 1 = VD; C

Parameter Symbol Min Max Unit

I2C® Mode (Note 9)

CCLK Clock Frequency Bus Free Time Between Transmissions

Start Condition Hold Time (prior to first clock pulse) Clock Low Time Clock High Time Setup Time for Repeated Start Condition CDIN Hold Time from CCLK Falling (Note 10) CDIN Setup Time to CCLK Rising Rise Time of Both CDIN and CCLK Lines Fall Time of Both CDIN and CCLK Lines Setup Time for Stop Condition

Notes: 9. Use of the I

2C®

bus interface requires a license from Philips.

10. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.

= 20 pF)

scl

buf

hdst

low

high

sust

hdd

sud

susp

-100kHz

4.7 - µs

4.0 - µs

4.7 - µs

4.0 - µs

4.7 - µs

0-µs

250 - ns

-1µs

-300ns

4.7 - µs

= 25 °C; VD, VA = 5V ±5%;

CDIN

CCLK

Stop Start

buf

hdst

low

hdd

high

sud

Repeated

Start

sust

hdst

Stop

susp

10 DS229PP2

CS5396 CS5397

+5V Analog

470 µF

100 µF

Left Analog Input +

Left Analog Input -

Right Analog Input +

Right Analog Input -

6.8nF

Ω

0.1 µF

VREF

VCOM

AINL+

AINL-

AINR+

AINR-

Ω

VA VL

CS5396/7

A/D CONVERTER

0.1 µF

2324

CS/PDN

CDIN/DFS

CCLK/SM

CAL

SDATA1 SDATA2

LRCK SCLK

MCLKA

MCLKD

DACTL

ADCTL

19 18

17 10

16 15

13 14

-Controller/

Configuration

Audio

Data

Processor

Timing

& Clock

+5V Digital

1 µF

Logic

TSTO pins should be left

floating, with no trace

attached

AGND0

AGND1LGND DGND AGND2

12 28

TSTO1 TSTO2

Figure 1. Typical Connection Diagram

DS229PP2 11

CS5396 CS5397

GENERAL DESCRIPTION

The CS5396/97 is a 24-bit, stereo A/D converter designed for stereo digital audio applications. The analog input channels are simultaneously sampled by separate, patented, 7th-order tri-level delta-sigma modulators at either 128 or 64 times the output sample rate (64× Fs or 128× Fs) of the device. The resulting serial bit streams are digitally filtered, yielding pairs of 24-bit values at output sample rates (Fs) of up to 100 kHz . This technique yields nearly ideal conversion performance independent of input frequency and amplitude. The converter does not require difficult-to-design or expensive anti-alias filters, and it does not require external sample-and-hold amplifiers or voltage references. Only normal power supply decoupling components, voltage reference bypass capacitors and a single resistor and capacitor on each input for antialiasing are required, as shown in Figure 1. An onchip voltage reference provides for a differential input signal range of 4.0 Vpp. The device also contains a high pass filter, implemented digitally after the decimation filter, to completely eliminate any internal offsets in the converter or any offsets present at the input circuitry to the device. Output data is available in serial form, coded as 2’s complement 24-bit numbers. For more information on delta-sigma modulation techniques see the references at the end of this data sheet.

Stand-Alone vs. Control Port Mode

The CS5396/97 can operate in either Stand-Alone or Control Port Mode. The functionality of pins 17, 18 and 19 is established upon entering either the Stand-Alone or Control Port mode, as described in the Pin Description section.

• 128× Oversampling Mode

• Reduction of 24-bit data to 20, 18 or 16-bit data with psychoacoustically optimized dither

• Programmability of psychoacoustic filter coefficients

• Peak Input Signal Level Monitor with either High Resolution or Bar Graph mode selection

• Signal inversion

• High pass filter defeat

• Mute

• Access to the digital filter to allow the input of external digital audio data to produce a two-toone decimated output and/or psychoacoustic bit reduction.

STAND-ALONE MODE Master Clock - Stand-Alone Mode

The master clock is the clock source for the deltasigma modulator sampling (MCLKA) and digital filters (MCLKD). The required MCLKA/D frequency is determined by the desired Fs an d must be 256× Fs. Table 1 shows some common master clock frequencies.

LRCK

(kHz)

32 8.192 2.048

44.1 1 1.2896 2.822 48 12.288 3.072 64 16.384 4.096

88.2 22.5792 5.6448 96 24.576 6.144

Table 1. Common Clock Frequencies for Stand-Alone

MCLKA/D

(MHz)

Mode

SCLK (MHz)

The Control Port Mode requires a micro-controller and allows access to many additional features, which include:

Serial Data Interface - Stand-Alone Mode

The CS5396/97 supports two serial data formats which are selected via the digital format select pin, DFS. The digital output format determines the relationship between the serial data, left/right clock and serial clock. Figures 2 and 3 detail the interface for-

12 DS229PP2

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