Cirrus Logic CS5394-KS, CDB5394 Datasheet

CS5394

117 dB, 48 kHz Audio A/D Converter

Features

24-Bit Conversion

Complete CMOS Stereo A/D System

—Delta-Sigma A/D Converters —Digital Anti-Alias Filtering —S/H Circuitry and Voltage Reference

Adjustable System Sampling Rates

—including 32 kHz, 44.1 kHz and 48 kHz

117 dB Dynamic Range (A-Weighted)

-103 dB THD + N

Differential Analog Circuitry

Internal 64× Oversampling

Linear Phase Digital Anti-Alias Filtering

—with >117 dB Stopband Attenuation

Single +5 V Power Supply

Power Down Mode

Description

The CS5394 is a complete analog-to -digital conve rter for stereo digital audio systems. It performs sampling, analog-to-digital conversion and anti-alias filtering, generating 24-bit values for both left and right inputs in serial form. The output samp le rate can be up to 50 kHz per channel.

The CS5394 uses 7th-order, delta-sigma modulation with 64× oversampling followed by digital filtering and decimation, which remove s the need for an external antialias filter. The ADC uses a differential architecture which provides excellent noise rejection.

The CS5394 has a linear phase filter with passband of dc to 22.1 kHz , ± 0.005 dB passband ripple and >117 dB

stopband rejection. The CS5394 is targeted for the highest perfor mance pro-

fessional audio systems requiring wide dynamic range, negligible distortion and low noise.

ORDERING INFORMATION

CS5394-KS -10° to 70° C 28-pin SOIC CDB5394 Evaluation Board

VCOM2MCLKA

VREF

AINL-

AINL+

AINR-

AINR+

Voltage Reference

5 4

S/H

26 27

S/H

AGND3AGND25AGND

Preliminary Product Information

Cirrus Logic, Inc. Crystal Semiconductor Products Division

P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.crystal.com

SCLK SDATA MCLKD

ADCTL

LP Filter

DAC

LP Filter

DAC

This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.

Comparator

28 23

VL TSTO221VD11DGND

DACTL

LGND22TSTO1

LRCK

14 16 20

Serial Output Interface

Digital

Decimation

Filter

Digital

Decimation

Filter

Calibration

Microcontroller

High Pass Filter

DGND

18 17 10

PDN

DFS

S/M

CAL

MAY ‘98

DS258PP4

TABLE OF CONTENTS

ANALOG C H A RA C T E RISTICS ...... .............................. .............................. ......... 3

POWER AND THERMAL CHARACTERISTICS .................................................. 4

DIGITAL FILTER CHARACTERISTICS ...............................................................4

DIGITAL CHARACTERISTICS ............................................................................4

ABSOLUTE MAXIMUM RATINGS ............................................................ ...........5

RECOMMENDED OPERATING CONDITIONS ................................................... 5

SWITCHING CHARACTERISTICS ...................................................................... 6

GENERAL D E SC R IPTION ............. .. ... ............................. ................................... 9

SYSTEM DESIGN ................................................................................................9

Master Clo c k ... ............ ...................................... .............................. ............ 9

SERIAL DATA INTERFACE ................................................................................ 9

Serial Data ..................................................................................................9

Serial Clock .................................................................................................9

Left / Right C lo c k ........ .. .. ..................... ....................................... ..............10

Master Mode .............................................................................................10

Slave Mode ................ ............. .............................................. ....................10

Analog Connections ... ............... .............. .......................... ............... .........10

High Pass Filter ........................................................................................ 11

Power-u p a n d Ca lib r a tio n ............... .. ............ .............................. ..............11

Synchronization of Multiple Devices .........................................................12

Grounding and Power Supply Decouplin g .............................................. ..12

PERFORMANCE ............................................................................................... 12

Digital Filter ............................................................................................... 12

PIN DESCR I P T IO N S .... .. ........... .............................. ....................................... ...14

PARAMETER DEFINITIONS .............................................................................18

REFEREN CES ......... .............. .............. ........... .............. .............. ............. .......... 19

PACKAGE DIMENSIONS ..................................................................................20

CS5394

2 DS258PP4

CS5394

ANALOG CHARACTERISTICS (T

Fs = 48 kHz; SCLK = 3.072 MHz; Analog connections as shown in Figure 1; Measurement Bandwidth is 20 Hz to 20 kHz unless otherwise specifi ed; Logic 0 = 0 V, Logic 1 = VD.)

Parameter Symbol Min Typ Max Unit

= 25 °C; VA, VL, VD = 5 V; Full-scale Input Sinewave, 997Hz;

Dynamic Performance

Dynamic Range

A-weighted

Total Harmonic Distortion + Noise (Note 1)

-1.0 dB

-20 dB

-60 dB Total Harmonic Distortion -1.0 dB (Note 1) THD - 0.0007 TBD % Interchannel Phase Deviation - 0.01 - Degree Interchannel Isolation - 118 - dB

THD+N

TBD TBD

114 117

-103

-94

-54

TBD TBD TBD

dc Accuracy

Interchannel Gain Mismatch - 0.05 - dB Gain Error - ±5 TBD % Gain Drift - 100 - ppm/°C Bipolar Offset Error with High Pass filter - 0 - LSB

Analog Input

Full-scale Differential Input Voltage (Note 2) V Input Impedance Z Common-Mode Rejection Ratio CMRR - 82 - dB

Common mode bias Voltage Vcom - 2.5 - V

IN IN

TBD 4.0 TBD V

-4.5-k

Ω

Notes: 1. Referenced to typical full-scale di fferential input voltage (4.0 Vpp).

2. Specified for a fully differential input ±{(AINR+) - (AINR-)}. Full-scale outputs will be produced for

* Refer to

differential inputs beyond V

Parameter D efinitions

at the end of this data sheet.

Specifications are subject to change without notice

and within VA and AGND.

DS258PP4 3

CS5394

POWER AND THERMAL CHARACTERISTICS (T

= 25 °C; VA, VL, VD = 5 V ±5%;

Fs = 48 kHz; Master Mode.)

Parameter Symbol Min Typ Max Unit

Power Supply Current (Normal Operati on) (VA) + (VL)

Power Supply Current (Power-Down Mode) (VA) + (VL)

Power Consumption Normal Operation

Power-Down Mode

85 65

2 2

750

TBD TBD

TBD

mA mA

mW Power Supply Rejection Ratio 1 kHz PSRR - 65 - dB Allowable Junction Temperature - - 135 °C Junction to Ambient Thermal I mpedance

DIGITAL FILTER CHARACTERISTICS (T

-45-°C/W

= 25 °C; VA, VL, VD = 5 V ±5%; Fs = 48 kHz)

Parameter Symbol Min Typ Max Unit

Passband -0.01 dB (Note 3) 0 - 22.1 kHz Passband Ripple - - ±0.005 dB Stop band (Note 3) 26.6 - 3050 kHz Stop band Attenuation (Note 4) 117 - - dB Group Delay (Fs = Output Sample Rate) t

Group Delay Variation vs Frequency

∆

- 34/Fs - s

--0.0µs

High Pass Filter Characteristics

Frequency Response -3 dB (Note 3)

-0.036 dB

1.8 20

Phase Deviation @ 20 Hz (Note 3) - 5.3 - Degree Passband Ripple - - 0 dB

Notes: 3. Filter characteristic scales with sample rate.

4. The analog modulator samples the input at 3.072 MHz for Fs equal to 48 kHz. There is no rejecti on of input signals which are (n

DIGITAL CHARACTERISTICS (T

× 3.072 MHz) ± 22.1 kHz, where n = 0, 1, 2, 3, ...

= 25 °C; VA, VL, VD = 5 V ±5%)

Parameter Symbol Min Max Unit

High-Level Input Voltage

MCLKA/D only

Low-Level Input Voltage

MCLKA/D only High-Level Output Voltage V Low-Level Output Voltage V Input Leakage Current I

OH OL in

2.4

3.0

0.8

1.0

V V

(VD) - 1.0 - V

-0.4V

-±10µA

4 DS258PP4

CS5394

ABSOLUTE MAXIMUM RATINGS (AGND, DGND = 0 V, All voltages with respect to ground.)

Parameter Symbol Min Max Unit

DC Power Supplies Positive Analog

Positive Logic

Positive Digital

|VA - VD|

|VA - VL|

|VD - VL|

Input Current (Note 5) I Analog Input Voltage (Note 6) V Digital Input Voltage (Note 6) V Ambient Operating Temperature (Power Applied) T Storage Temperature T

Notes: 5. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause

SCR latch-up.

6. The maximum over/under voltage is limited by the input current.

WARNING: Operation at or beyond these limits may result in permanent damage to th e de vice.

Normal operation is not guaranteed at these extremes.

VA VL

in INA IND

stg

-0.3

-±10mA

-0.7 (VA) + 0.7 V

-0.7 (VD) + 0.7 V

-55 +100 °C

-65 +150 °C

+6.0 +6.0 +6.0

0.4

RECOMMENDED OPERATING CONDITIONS

(AGND, DGND = 0 V, All voltages with respect to ground.)

Parameter Symbol Min Typ Max Unit

DC Power Supplies Positive Analog

Positive Logic

Positive Digital

|VA - VD|

VA VL

4.75

5.0

5.25

0.4

DS258PP4 5

CS5394

SWITCHING CHARACTERISTICS (T

= -10 to 70 ° C; VA = VL = VD = 5 V ± 5%; I nputs:

Logic 0 = 0 V

Logic 1 = VA = VL = VD; CL = 20 pF)

Parameter Symbol Min Typ Max Unit

Output Sample Rate F MCLK Period t MCLK Low t MCLK High t

clkw

clkl

clkh

2-50kHz 78 - 1950 ns 26 - - ns 26 - - ns

MCLK Fall Time - - 12 ns

Master Mode

SCLK falling to LRCK t SCLK falling to SDATA valid t

mslr

sdo

-20 - +20 ns

--20ns

SCLK Duty Cycle - 50 - %

Slave Mode

LRCK Period 1/F

20 - 500 µs

LRCK Duty Cycle TBD 50 TBD % SCLK Period t

SCLK Pulse Width Low t SCLK Pulse Width High t SCLK falling to SDATA valid t LRCK edge to MSB valid t SCLK rising to LRCK edge delay t LRCK edge to rising SCLK setup time t

sclkw

sclkl

sclkh

dss

lrdss

slr1 slr2

(Note 7) - - ns (Note 8) - - ns

60 - - ns

- - (Note 9) ns

- - (Note 9) ns (Note 9) - - ns (Note 9) - - ns

Notes: 7.

-----------------128 F

-----------------256 F

------------------ 20+ 512 F

6 DS258PP4

CS5394

SCLK output

mslr

LRCK outpu t

sdo

SDATA

MSB MSB-1

SCLK to SDATA & LRCK - MASTER Mode

Serial Data Format, DFS low

SCLK output

mslr

SCLK input

LRCK input

SDATA

slr1tslr2

sclkh

lrdss

MSB MSB-1 MSB-2

SCLK to LRCK & SDATA - SLAVE Mode

Serial Data Format, DFS low

SCLK input

slr1tslr2

sclkh

sclkl

sclkw

dss

sclkw

LRCK output

SDATA

SCLK to SDATA & LRCK - MASTER Mode

Serial Data Format, DFS high

S compatible

MSB

sdo

LRCK input

dss

SDATA

MSB MSB-1

SCLK to SDATA & LRCK - MASTER Mode

Serial Data Format, DFS high

S compatible

DS258PP4 7

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