Cirrus Logic CS5372-BS, CS5371-BS Datasheet

CS5371/CS5372

Low-Power High-Performance ∆Σ Modulators

Features

l Fourth-Order ∆Σ Architecture l Clock Jitter Tolerant Architecture l Input Voltage Range 5 V l High Dynamic Range (SNR)

s 124 dB @ 411 Hz Bandwidth s 121 dB @ 822 Hz Bandwidth

l Low Total Harmonic Distortion (THD)

s -118 dB Typical, -112 dB Maximum

l Low Power Consumption

s Normal Mode: 25 mW per Channel s Low Power Mode: 15 mW per Channel

l Small Footprint 24 Pin SSOP Package l Single or Multi-Channel System Support

s 1 Channel System; CS5371 s 2 Channel System; CS5372 s 3 Channel System; CS5371 + CS5372 s 4 Channel System; CS5372 + CS5372

l Single or Dual Power Supply Configurations

s VA+ = +5 V; VA- = 0 V; VD = +3 V to +5 V s VA+ = +2.5 V; VA- = -2.5 V; VD = +3 V to +5 V s VA+ = +3 V; VA- = -3 V; VD = +3 V

p-p

(2.5 V

diff

)

Description

The CS5371 and CS5372 are one and two channel high dynamic range, fourth-order ∆−Σ modulators intended for geophysical and sonar applications. Used in combination with the CS5376 digital filter, a unique high resolution A/D measurement system results.

The CS5371 and CS5372 provide higher dynamic range and lower total harmonic distortion than our industry standard CS5321 modulator, while consuming significantly less power per channel. The modulators generate an oversampled serial bit stream at 512 kbits per second when operated from a clock frequency of 2.048 MHz. The CS5371 and CS5372 are available in a small 24-pin SSOP package, providing exceptional performance in a very small footprint.

In normal mode (LPWR = 0, MCLK = 2.048 MHz), power consumption is 25 mW per channel, and in low power mode (LPWR = 1, MCLK = 1.024MHz), power consumption is 15 mW per channel. Each modulator can be independently powered down to 1 mW per channel, and by halting the input clock the modulators enter a micropower state using only 10 µW per channel.

ORDERING INFORMATION

CS5371 - BS -40

CS5372 - BS -40

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Preliminary Product Information

P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com

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This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.

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DS255PP2

TABLE OF CONTENTS

1. CHARACTERISTICS/SPECIFICATIONS....................................................... 4

ANALOG CHARACTERISTICS .................................................................. 4

5.0 AND 3.0 V DIGITAL CHARACTERISTICS ........................................... 6

ABSOLUTE MAXIMUM RATINGS ............................................................. 6

SWITCHING CHARACTERISTICS ............................................................ 7

2. GENERAL DESCRIPTION. ........................................................................... 8

3. MODULATOR PERFORMANCE.................................................................. 10

3.1. Full Scale Signal Performance......................................................... 10

3.2. Noise Performance .......................................................................... 10

4. SIGNAL INPUTS ......................................................................................... 10

4.1. Differential Inputs - INR+/-, INF+/- ................................................... 10

4.2. Anti-Alias Filters ............................................................................... 11

4.3. Input Impedance .............................................................................. 11

4.4. Maximum Signal Levels ................................................................... 12

5. INPUT OFFSET ........................................................................................... 12

5.1. Offset Enable - OFST....................................................................... 12

5.2. Offset Drift ........................................................................................ 12

6. VOLTAGE REFERENCE INPUTS .............................................................. 12

6.1. Voltage Reference Configurations ................................................... 13

6.2. VREF Input Impedance .................................................................... 13

6.3. Gain Accuracy .................................................................................. 14

6.4. Gain Drift .......................................................................................... 14

7. DIGITAL FILTER INTERFACE .................................................................... 14

7.1. Modulator Clock - MCLK .................................................................. 14

7.2. Modulator Data - MDATA................................................................. 14

7.3. Modulator Sync - MSYNC ................................................................ 15

7.4. Modulator Flag - MFLAG.................................................................. 15

8. POWER MODES ......................................................................................... 15

8.1. Normal Power Mode ........................................................................ 15

8.2. Low Power Mode - LPWR ................................................................ 16

8.3. Power Down Mode - PWDN............................................................. 16

8.4. Micro Power Mode ........................................................................... 16

9. POWER SUPPLY ........................................................................................ 16

9.1. Power Supply Configurations ........................................................... 16

9.2. Power Supply Bypassing ................................................................. 16

9.3. SCR Latch-up Considerations.......................................................... 16

9.4. DC-DC Converter Considerations.................................................... 17

9.5. Power Supply Rejection ................................................................... 17

10. PIN DESCRIPTION - CS5371 ..................................................................... 18

11. PIN DESCRIPTION - CS5372 ..................................................................... 20

12. PACKAGE DIMENSIONS ............................................................................ 22

CS5371/CS5372

Contacting Cirrus Logic Support

For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:

http://www.cirrus.com/corporate/contacts/

Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.

2 DS255PP2

1. CHARACTERISTICS/SPECIFICATIONS

CS5371/CS5372

ANALOG CHARACTERISTICS Notes:T

VD = 3 V ± 5%; DGND = 0 V; MCLK = 2.048 MHz; LPWR = 0; VREF+/- = 2.5V (VREF- = -2.5 V; VREF+ = 0 V); Devices are connected as shown in Figure 3, the System Connection Diagram, unless otherwise specified.

Parameter Symbol

Specified Temperature Range T

Dynamic Performance

Dynamic Range (Note 1) OFST = 1 0 Hz to 1644 Hz

0 Hz to 822 Hz

0 Hz to 411 Hz

0 Hz to 206 Hz 0 Hz to 103 Hz

0 Hz to 51.5 Hz

0 Hz to 25.75 Hz Total Harmonic Distortion (Note 2) THD - -118 -112 dB Intermodulation Distortion (Note 3) IMD - -115 - dB

DC Accuracy

Channel to Channel Gain Variation CGV - 1 - % Full Scale Error (Note 4) FSE - 1 - % Full Scale Drift (Notes 4 and 5) TC Offset (Notes 4) V Offset after Calibration (Note 6) - ±1 - µV Offset Calibration Range (Note 7) - 100 - %F.S. Offset Drift (Notes 4 and 5) TC

Notes: 1. Dynamic Range defined as 20log( (RMS full scale) / (RMS idle noise) )

2. Tested with full scale input signal of 31.25 Hz; OWR = 1000 sps; OFST = 0 or OFST = 1.

3. Characterized with input signals of 31.25 Hz and 52.63 Hz, each 6 dB down from full scale, OWR = 1000 sps.

4. Specification is for the parameter over the specified temperature range and is for the CS5371/CS5372 devices only and does not include the effects of external components.

5. Specifications are guaranteed by design and/or characterization.

6. The offset after calibration specification applies to the effective offset voltage for a full scale input to the CS5371/CS5372 modulator, but is measured from the output digital codes from the CS5376.

7. The CS5371/CS5372 offset calibration is performed digitally and includes full scale range. Calibration offsets greater than ± 5% of full scale will begin to subtract from the dynamic range.

= -40 °C to +85 °C; VA+ = 2.5 V ± 5%; VA- = -2.5 V ± 5%;

CS5371-BS / CS5372-BS

SNR

ZSE

-40 - +85 °C

121

- 5 - ppm/°C

-1-mV

-1-µV/°C

109 121 124 127 130 133 136

UnitMin Typ Max

dB dB dB dB dB dB dB

DS255PP2 3

CS5371/CS5372

ANALOG CHARACTERISTICS (Continued)

Parameter Symbol Min Typ Max Unit

Specified Temperature Range T

Input Characteristics

Input Signal Frequencies (Note 8) BW DC - 1644 Hz

Input Voltage Range (Note 9) VIN - - 5 V

Input Over-range Voltage Tolerance (Note 9) I

Input Signal plus Common Mode VA- - VA+ V

Common Mode Rejection Ratio CMRR - 90 - dB

Channel Crosstalk, CS5372 only CXT - -120 - dB

Voltage Reference Input

VREF (VREF+) - (VREF-) - 2.5 - V

VREF Current - - 120 µA

Power Supplies

DC Power Supply Currents (Note 10 and 11) LPWR = 0; MCLK = 2.048 MHz Analog

Digital

LPWR = 1; MCLK = 1.024 MHz Analog

Digital

Power Down CS5371 PWDN = 1

PWDN = 1, MCLK = 0

CS5372 PWDN1 or PWDN2 = 1

PWDN1 = PWDN2 = 1

PWDN1 = PWDN2 = 1; MCLK = 0

Power Supply Rejection DC - 128 kHz (Note 12) PSRR - 90 - dB

OVR

-40 - +85 °C

5--%F.S.

5.0

0.1

3.0

0.1

1 10 25

1 10

7.0

0.2

4.5

0.2

mA mA mA mA

µW mW mW

µW

p-p

Notes: 8. The upper bandwidth limit is determined by the CS5376 digital filter. A simple single pole anti-alias filter

with a -3 dB frequency at (MCLK / 256) should be placed in front of each channel.

9. The input voltage range is for the configuration depicted in Figure 3, the System Connection Diagram, and applies to signal frequencies from DC to the stop-band frequency selected in the CS5376.

10. Per channel. All outputs unloaded. All digital inputs forced to VD or GND respectively.

11. In Low Power Mode LPWR = 1, the Master Clock MCLK is reduced to 1.024 MHz. This reduces the signal bandwidth by a factor of 2.

12. Tested with a 100 mVp-p sine wave applied separately to each supply.

4 DS255PP2

CS5371/CS5372

5.0 AND 3.0 V DIGITAL CHARACTERISTICS Notes:T

= 25 °C; VA+, VD = 5 V ± 5% or 3 V ±

5%; AGND, DGND = 0 V; All voltages with respect to DGND.

Parameter Symbol Min Typ Max Unit

High-Level Input Voltage V

Low-Level Input Voltage V

High-Level Output Voltage I

Low-Level Output Voltage I

= -5.0 mA V

out

= 5.0 mA V

out

Input Leakage Current I

3-State Leakage Current I

Digital Output Pin Capacitance C

out

0.6 * VD - VD V

0.0 - 0.8 V

(VD) - 1.0 - - V

--0.4V

-±1±10µA

--±10µA

-9-pF

ABSOLUTE MAXIMUM RATINGS Notes:DGND = 0 V

Parameter Symbol Min Typ Max Unit

DC Power Supplies (Note 13 and 14) Positive Digital

Positive Analog

Negative Analog

Input Current, Any Pin Except Supplies (Note 15 and 16) I

Input Current, Supplies (Note 16) I

Output Current I

Power Dissipation (Note 17) PDN - - 500 mW

Analog Input Voltage All Analog Pins V

Digital Input Voltage All Digital Pins V

Ambient Operating Temperature T

Storage Temperature T

VA+

VA-

OUT

INA

IND

stg

-0.3

+0.3

+6.0 +6.0

-3.3

--±10mA

--±50mA

--±25mA

- 0.3 - (VA+) + 0.3 V

-0.3 - (VD) + 0.3 V

-40 - 85 °C

-65 - 150 °C

V V V

Notes: 13. VA+ and VA- must satisfy {(VA+) - (VA-)} < +6.6 V.

14. VD and VA- must satisfy {(VD) - (VA-)} < +7.6 V.

15. Includes continuous over-voltage conditions at the analog input (AIN) pins.

16. Transient current of up to 100 mA can be safely tolerated without SCR latch-up.

17. Total power dissipation, including all input and output currents.

DS255PP2 5

CS5371/CS5372

2.7 V

0.3 V

fallin

risein

SWITCHING CHARACTERISTICS Notes:T

5%; VD = 3 V ± 5%; Inputs: Logic 0 = 0 V, Logic 1 = VD; C

= -40 °C to +85 °C; VA+ = +2.5 V ± 5% VA- = -2.5 V ±

= 50 pF

Parameter Symbol Min Typ Max Unit

MCLK Frequency (Note 18) f

0.1 2.048 2.2 MHz

MCLK Duty Cycle 40 - 60 %

MCLK Jitter (In-band, Aliased in-band) - - 300 ps

MCLK Jitter (Out-of-band) - - 1 ns

Rise Times: Any Digital Input (Note 19)

Any Digital Output

Fall Times: Any Digital Input (Note 19)

Any Digital Output

MSYNC Setup Time to MCLK falling (Note 20) t

MSYNC Hold Time after MCLK falling t

MCLK rising to Valid MFLAG t

MCLK rising to Valid MDATA t

risein

riseout

fallin

fallout

mss

msh

mfh

mdv

20 - - ns

-3565ns

-6090ns

100

Notes: 18. If MCLK is removed, the CS5372 enters a micro power state.

19. Excludes MCLK input, MCLK should be driven with a signal having rise/fall times of 25 ns or faster.

20. MSYNC latched on MCLK falling edge, data output on next MCLK rising edge.

ns ns

MCLK

MSYNC

MDATA

MFLAG

mss

msh

mdv

Figure 1. Rise and Fall Times

VALID DATA

riseo ut

mdv

mfh

VALID DATA

fallout

2.7 V

0.3 V

Figure 2. CS5372 Interface Timing

6 DS255PP2

CS5371/CS5372

2. GENERAL DESCRIPTION.

The CS5371 and CS5372 are one and two channel fourth-order ∆−Σ modulators, optimized for extremely high resolution measurement of signals between DC and 1644 Hz. They are designed to be used with the CS5376 low power multi-channel decimation filter. Figure 3 on page 8 shows a fourchannel system connection diagram for two CS5372 and one CS5376.

High Performance

The CS5371/CS5372 modulators have exceptional performance characteristics. Modulator dynamic range (SNR) is 124 dB over a 411 Hz bandwidth, with total harmonic distortion (THD) of -118 dB.

Low Power Consumption

The CS5371/CS5372 modulators have very low power consumption. Power consumption is only 25 mW per channel in normal mode (LPWR=0, MCLK=2.048 MHz), and 15 mW per channel in low power mode (LPWR=1, MCLK=1.024 MHz).

An independently selectable power-down mode (PWDN=1) can be used to disable a modulator and reduces its power consumption to 1 mW. If MCLK is then halted (MCLK=0), the modulator enters a micropower state using only 10 µW per channel.

Small Package Size

The CS5371/CS5372 modulators are available in a very small 24-pin SSOP package approximately 8 mm x 8 mm in size. The CS5372 has two modulator channels per package to increase board layout density even further.

Multi-Channel System Support

Combining the CS5371 and CS5372 modulators with the CS5376 digital filter permits multiple channel system configurations to be supported.

1 Channel - CS5371, CS5376

2 Channel - CS5372, CS5376

3 Channel - CS5371, CS5372, CS5376

4 Channel - CS5372, CS5372, CS5376

Differential Analog Signal Inputs

The CS5371/CS5372 modulators have differential analog inputs capable of measuring signals up to

5.0 V peak-to-peak (2.5 V fully differential) when using a 2.5 V voltage reference. The inputs will tolerate a 5% over-range voltage and continue operating at full specification.

Digital Filter Interface

The CS5371/CS5372 modulators are designed to operate with the CS5376 digital filter. The CS5376 generates the modulator clock and synchronization signal inputs (MCLK and MSYNC), while receiving the modulator data and over-range flag outputs (MDATA and MFLAG). The modulators produce an oversampled ∆−Σ serial bit stream at 512 kbits per second when operated from a 2.048 MHz modulator clock.

Multiple Power Supply Configurations

The CS5371/CS5372 modulators support multiple power supply configurations. They can run from single or dual supplies in the following configurations:

s VA+ = +5V; VA- = 0V; VD = +3V to +5V s VA+ = +2.5V; VA- = -2.5V; VD = +3V to +5V s VA+ = +3V; VA- = -3V; VD = +3V

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