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CS5360-BS
Datasheet
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Cirrus Logic CS5360-BS Datasheet

CS5360
24-Bit Stereo A/D Converter for Digital Audio

Features

l 24 Bit Conversion l 105 dB Dynamic Range l -95 dB THD+N l 128X Oversamplin g l Fully Differential Inputs l Linear Phase Digital Anti-Alias Filtering
– 21.7 kHz passband (Fs = 48kHz) – 85 dB stop band attenuation – 0.0025 dB pass band ripple
l High Pass Filter - DC Offset Removal l Peak Signal Level Detector
– High Resolution and Bar Graph Modes
l Pin Compatible wi th CS5334 and CS5 335
I
CMOUT
AINL-
AINL+
AINR-
AINR+
15
16 17
S/H
14 13
S/H
VA+
3
Voltage Reference
+
-
+
-
VD+
6
LP Filter
DAC
LP Filter
DAC
RST
18
Comparator
Comparator

Description

The CS5360 is a 2- channel, single +5 V supply, 24-bit analog-to-digital converter for digital audio systems. The CS5360 performs sampling, analog-to-digital conversion and anti-alias filte ring, gener ating 24-bit va lues for bot h left and right inputs in serial form. The output word rate can be up to 50 kHz per channel.
The CS5360 uses 4th-order, delta-sigma modulation with 128X oversam pling followed by digital filtering and decimation, which removes the need for an external anti­alias filter. This ADC uses a differential architecture which provides excellent noise rejection.
The CS5360 has a filter passband to 21.7 kHz. The filter has linear phase, 0.0025 dB passband ripple, and >85 dB stopband rejection. An on-chip high pass filter is also included to remove DC offsets.
ORDERING INFORMATION
CS5360-KS -10° to 70°C 20-pin Plastic SSOP CS5360-BS -40° to 85°C 20-pin Plastic SSOP
MCLK
+
-
+
-
OVFL SCLK LRCK
7
FRAME
2812
10
SDAT A
9
Serial Output Interface
Digital
Decimation
Filter
Digital
Decimation
Filter
High Pass Filter
High Pass Filter
DIF0
20
DIF1
19
4
AGND
Preliminary Product Information
5
DGND
This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.
Copyright  Cirrus Logic, Inc. 1999
(All Rights Reserved)
PU
11
1
HP DEFEAT
DS280PP2
OCT ‘99
1

TABLE OF CONTENTS

1. CHARACTERISTICS AND SPECIFICATIONS .................................. ....... ...... ....... ...... ....... ..... 3
ANALOG CHARACTERISTICS................................................................................................ 3
DIGITAL FILTER CHARACTERISTICS....................................................................................4
DIGITAL CHARACTERISTICS................................................................................................. 4
ABSOLUTE MAXIMUM RATINGS ........................................................................................... 4
SWITCHING CHARACTERISTICS ................................. ...... ....... ...... ....... ...... ....... ...... ............5
2. SYSTEM DESIGN .....................................................................................................................8
2.1 Master Clock ......................................................................................................................8
3. SERIAL DATA INTERFACE ..................................................................................................... 8
3.1 Serial Data .........................................................................................................................8
3.2 Serial Clock ........................................................................................................................ 8
3.3 Left / Right Clock .............................................................................................................. 10
3.4 Master Mode ....................................................................................................................10
3.5 Slave Mode ......................................................................................................................10
3.6 Analog Connections .........................................................................................................10
3.7 High Pass Filter ................................................................................................................ 10
4. INPUT LEVEL MONITORING ................ ....... ...... ....... ...... ...... ....... ...... ....... ...... ....................... 11
4.1 High Resolution Mode ...................................................................................................... 11
4.2 Bar Graph Mode .............................................................................................................. 12
4.3 Overflow ...........................................................................................................................12
4.4 Initialization ......................................................................................................................12
4.5 Initialization with High Pass Filter Enabled ......................................................................12
4.6 Initialization and Internal Calibration with High Pass Filter Disabled ...............................12
4.7 Power-Down .................................................................................................................... 13
4.8 Grounding and Power Supply Decoupling .......................................................................13
4.9 Digital Filter ......................................................................................................................13
5. PIN DESCRIPTIONS ....................................................... ...... ....................................... ...... . ... 15
6. PARAMETER DEFINITIONS ..................................................................................................18
7. PACKAGE DIMENSIONS ....................................................................................................... 19
CS5360

LIST OF FIGURES

Figure 1. SCLK to SDATA & LRCK - MASTER Mode Format 0 and 1 ........................................... 6
Figure 3. SCLK to LRCK & SDATA - SLAVE Mode Format 0 & 1.................................................. 6
Figure 2. SCLK to SDATA & LRCK - MASTER Mode Format 2 .....................................................6
Figure 4. SCLK to LRCK & SDATA - SLAVE Mode Format 2......................................................... 6
Figure 5. SCLK to Frame Delay ...................................................................................................... 6

Contacting Cirrus Logic Support

For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts/
Preliminary product inf o rmation describes products whi ch are i n production, but for whi ch f ul l characterization data is not yet available. Advance product infor­mation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document i s accurat e and reli able. However , t he infor mation is subje ct to chang e without noti ce and is provi d ed “AS IS” without warrant y of
any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other ri g ht s of third parties. This document is the pro perty of Cirrus Logi c, Inc. and i mplie s no licen se under patents, copyrights, tr ademarks, or trade secre ts. No part of this publication may be copied, reproduced , stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the pr i or writ ten consent of Cirrus Logic, Inc. It e ms f rom any Ci rrus L ogi c websi t e or di sk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trade­marks and service marks can be found at http://www.cirrus.com.
2 DS280PP2
Figure 6. Typical Connection Diagram................ ...... ....... ...... ...... ....... ....................................... .... .7
Figure 7. Data Block and Frame..................................................................................................... 8
Figure 8. Serial Data Format 0.. ............................................................................. ....... ...... ............ 9
Figure 9. Serial Data Format 1.. ............................................................................. ....... ...... ............ 9
Figure 10. Serial Data Format 2...................................................................................................... 9
Figure 11. Full Scale Input Levels................................................................................................. 10
Figure 12. CS5360 Digital Filter Passband Ripple........................................................................ 14
Figure 13. CS5360 Digital Filter Transition Band.......................................................................... 14
Figure 14. CS5360 Digital Filter Stopband Rejection.................................................................... 14
Figure 15. CS5360 Digital Filter Transition Band.......................................................................... 14

LIST OF TABLES

Table 1. Common Clock Frequencies............................................................................................. 9
Table 2. Digital Input Formats......................................................................................................... 9
Table 3. Peak Signal Level Bits - High Resolution Mode.............................................................. 12
Table 4. P7 to P0 - Peak Signal Level Bits -Bar Graph Mode....................................................... 13
CS5360
DS280PP2 3
CS5360

1. CHARACTERISTICS AND SPECIFICATIONS

ANALOG CHARACTERISTICS

(TA = 25 °C; VA+ = VD+ = 5 V; -1 dB Input sinewave, 997 Hz; Fs = 48 kHz; MCLK = 12.288 MHz; SCLK = 3.072
MHz; Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified; Logic 0 = 0 V, Logic 1 = VD+)
5360-KS 5360-BS
Parameter Symbol
Temperature Range T
A -10 to +70 -40 to +85 °C

Dynamic Performance

Dynamic Range A-weighted 10097105
102
Total Harmonic Distortion + Noise (Note 1)
-1 dB
-20 dB
-60 dB Interchannel Phase Deviation - 0.01 - - 0.01 - Degree Interchannel Isolation (dc to 20 kHz) - 105 - - 105 - dB
THD+N
-
-
-
-95
-82
-42
-
-
-90
-77
-37
95 92
105 102
-
-
-
-95
-82
-42
-85
-72
-32

dc Accuracy

Interchannel Gain Mismatch - 0.05 - - 0.05 - dB Gain Error - -±5- -±5% Gain Drift - 200 - - 200 - ppm/°C Offset Error with HPF
HP defeat with CAL
-
-
0
±100
-
-
-
-
0
±100

Analog Input

Input Voltage Range (Differential) VIN 1.9 2.0 2.1 1.9 2.0 2.1 Vrms Input Impedance ZIN - 30 - - 30 - k Input Bias Voltage - 2.2 - - 2.2 - V Common Mode Rejection Ratio CMRR - 60 - - 60 - dB

Power Supplies

Power Supply Current I
Power Down (IA + ID)
Power Dissipation Normal
Power Down
Power Supply Rejection Ratio - 55 - - 55 - dB
A
I
D
-
-
-
-
-
40 25
0.5
325
2.5
45 30
-
375
-
-
-
-
-
-
40 25
0.5
325
2.5
45 30
375
UnitsMin T yp Max Min Typ Max
-
-
-
-
-
-
dB
dB dB dB
LSB LSB
Ω
mA mA mA
mW mW
Notes: 1. Referenced to nominal input level.
Specifications are subject to change without notice
4 DS280PP2
CS5360

DIGITAL FILTER CHARACTERISTICS (Note 2, T

= 25 °C; VA+ = VD+ = 5 V ±5%; Fs = 48 kHz)
A
Parameter Symbol Min Typ Max Unit
Passband (Note 3) 0.02 - 21.7 kHz Passband Ripple - - ±0.0025 dB Stopband (Note 3) 26.3 - 6118 kHz Stopband Attenuation (Note 4) 85 - - dB Group Delay (Fs = Output Sampl e Rate) t Group Delay Variation vs. Frequency
gd
∆
t
gd
- 32/Fs - s
--0µs

High Pass Filter Characteristics

Frequency Response -3 dB (Note 3)
-0.1 dB
-
-
0.9 20
-
Hz
­Phase Deviation @20 Hz (Note 3) - 2.6 - Degree Passband Ripple - - 0 dB
Notes: 2. Filter response is not tested but is guaranteed by design.
3. Filter characteristics scale with output sample rate.
4. The analog modulator samples the input at 6.144 MHz for an output sample rate of 48 kHz. There is no rejection of input signals which are multiples of the sampling frequency (n x 6.144 MHz ±21.7 kHz where n = 0, 1, 2, 3, ...).

DIGITAL CHARACTERISTICS (T

= 25 °C; VA+ = VD+ = 5 V ±5%)
A
Parameter Symbol M in Max Unit
High-level Input Voltage V Low-level Input Voltage V High-level Output Voltage at Io = -20 µA V Low-level Output Voltage at Io = 20 µA V Input Leakage Current I
IH
IL OH OL
in
2.4 - V
-0.8V
(VD+) - 1.0 - V
-0.4V
-10µA

ABSOLUTE MAXIMUM RATINGS (AGND = 0 V, all voltages with respect to ground.)

Parameter Symbol M in Max Unit
DC Power Supply VA+ -0.3 +6.0 V Input Current, Any Pin Except Supplies (Note 5) I Analog Input Voltage (Note 6) V Digital Input Voltage (Note 6) V Ambient Temperature (power applied) T Storage Temperature T
in INA IND
A
stg
Notes: 5. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause
SCR latch-up.
6. The maximum over/under voltage is limited by the input extremes.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
- ±10 mA
-0.7 (VA+) + 0.7 V
-0.7 (VA+) + 0.7 V
-55 +125 °C
-65 +150 °C
DS280PP2 5
CS5360
1
1024
()
F
S
()
------------------------------- 30 n s+

SWITCHING CHARACTERISTICS (T

Logic 1 = VA+ = VD+; C
= 20 pF)
L
= 25 °C; VA+ = 5 V ±5%; Inputs: Logic 0 = 0 V,
A
Parameter Symbol Min Typ Max Unit
Output Sample Rate F MCLK Period MCLK / LRCK = 256
t MCLK / LRCK = 384 MCLK / LRCK = 512
MCLK Low MCLK / LRCK = 256
MCLK / LRCK = 384 MCLK / LRCK = 512
MCLK High MCLK / LRCK = 256
t MCLK / LRCK = 384 MCLK / LRCK = 512
Peak Update Pulse Width pu
S
clkw
t
clkl
clkh
pulse
8.0 - 50 kHz 78
52 39
31 20 15
31 20 15
-
-
-
-
-
-
-
-
-
1953 1302
976
-
-
-
-
-
-
20 - - ns

Master Mode

SCLK Falling to LRCK (Note 7) t SCLK Falling to SDATA Valid (Note 7) t
mslr sdo
-10 - 10 ns
-10 - 35 ns
SCLK Duty Cycle - 50 - % SCLK Falling to Frame Valid (Note 7) t LRCK Edge to OVFL Valid t LRCK Edge to OVFL Edge Delay t
sfo ovfl ovfl
-10 - Note 8 ns
-10 - 30 ns
-10 - Note 12 ns

Slave Mode

LRCK Duty Cycle 25 50 75 % SCLK Period t SCLK Pulse Width Low (Note 10) t SCLK Pulse Width High (Note 11) t SCLK Falling to SDATA Valid (Note 7) t LRCK Edge to MSB Valid t SCLK Rising to LRCK Edge Delay (Note 14) t LRCK Edge to Rising SCLK Setup Time (Note 14) t SCLK Falling to Frame Delay t
sclkw
sclkl
sclkh
dss
lrdss
slr1 slr2
sfo
Note 9 - - ns
Note 13 - - ns
50 - - ns
- - Note 13 ns
- - Note 13 ns
50 - - ns
Note 13 - - ns
- - Note 15 ns
Notes: 7. SCLK Rising for Mode 1
8.
1
------------------- -----
9.
()
()
96
F
S
10. Pulse Width High for Mode 1
11. Pulse Width Low for Mode 1
12.
13.
1
------------------- -------- -20 ns+
()
()
512
F
S
1
----------------------------50 ns+
()
()
512
F
S
14. SCLK Falling for Mode 1
15.
1
----------------------------35 ns+
()
()
384
F
S
ns
ns
ns
6 DS280PP2
Figure 1. SCLK to SDATA & LRCK - MASTER Mode
Format 0 and 1
Figure 3. SCLK to LRCK & SDATA - SLAVE Mode
Format 0 & 1
SCLK*
FRAME
t
sfo
CS5360
SCLK output*
LRCK output
SDATA
OVFL
SCLK input*
(SLAVE mode)
LRCK input
(SLAVE mode)
SDATA
OVFL
t
ovfl
slr1tslr2
t
mslr
t
sdo
MSB MSB-1
t
t
lrdss
MSB MSB-1 MSB-2
t
ovfl
t
sclkl
t
sclkh
t
sclkw
t
dss
SCLK output
t
mslr
LRCK output
t
sdo
SDATA
OVFL
MSB
t
ovfl
Figure 2. SCLK to SDATA & LRCK - MASTER Mode
Format 2
SCLK input
(SLAVE mode)
LRCK input
(SLAVE mode)
SDATA
OVFL
t
slr1tslr2
t
sclkl
t
sclkh
t
sclkw
t
dss
MSB MSB-1
t
ovfl
Figure 5. SCLK to Frame Delay
* SCLK is inverted in Format 1
DS280PP2 7
Figure 4. SCLK to LRCK & SDATA - SLAVE Mode
Format 2
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