Cirrus Logic CS5351-KZ, CS5351-KS, CS5351-BZ, CS5351-BS Datasheet

CS5351

108 dB, 192 kHz, Multi-Bit Audio A/D Converter

Features



Advanced Multi-bit Delta-Sigma Architecture



24-Bit Conversion



108 dB Dynamic Range



-98 dB THD+N



System Sampling Rates up to 192 kHz



Single-Ended Analog Inputs



Less than 150 mW Power Consumption



High Pass Filter or DC Offset Calibration



Supports Logic Levels Between 5 and 2.5V



Linear Phase Digital Anti-Alias Filtering



Overflow Detection



Functionally Compatible with the CS5361

General Description

The CS5351 is a complete analog-to-digital converter for digital audio systems. It performs sampling, analog-todigital conversion and anti-alias filtering, generating 24bit values for both left and right inputs in serial form at sample rates up to 192 kHz per channel.

The CS5351 uses a 5th-order, multi-bit delta-sigma modulator followed by digital filtering and decimation, which removes the need for an external anti-alias filter.

The CS5351 is ideal for audio systems requiring wide dynamic range, negligible distortion and low noise, such as A/V receivers, DVD-R, CD-R, digital mixing consoles, and effects processors.

ORDERING INFORMATION

CS5351-KS -10° to 70° C 24-pin SOIC CS5351-BS -40° to 85° C 24-pin SOIC CS5351-KZ -10° to 70° C 24-pin TSSOP CS5351-BZ -40° to 85° C 24-pin TSSOP CDB5351 Evaluation Board

FILT+

AINL

AINR

VQ LRCK

Voltage Reference

S/H

REFGND

Preliminary Product Information

http://www.cirrus.com

SCLK

Serial Audio Interface

LP Filter

DAC

LP Filter

DAC

This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.

∆Σ

Digital

Decimation

Filter

Digital

Decimation

Filter

SDOUT MCLK

High Pass Filter

RST

I2S/LJ

M/S

HPF

MDIV

MODE0

MODE1

SEPT ‘02

DS565PP2

TABLE OF CONTENTS

1 PIN DESCRIPTIONS .................................................................................................................4

2 TYPICAL CONNECTION DIAGRAM ......................................................................................... 5

3 APPLICATIONS ......................................................................................................................... 6

3.1 Operational Mode/Sample Rate Range Select ..................................................................6

3.2 System Clocking ................................................................................................................ 6

3.2.1 Master Mode .........................................................................................................7

3.2.2 Slave Mode ........................................................................................................... 8

3.3 Power-up Sequence .......................................................................................................... 8

3.4 Analog Connections ........................................................................................................... 8

3.5 High Pass Filter and DC Offset Calibration ....................................................................... 9

3.6 Overflow Detection ............................................................................................................. 9

3.6.1 OVFL Output Timing ........................................................................................... 10

3.7 Grounding and Power Supply Decoupling ....................................................................... 10

3.8 Synchronization of Multiple Devices ................................................................................ 10

4 CHARACTERISTICS AND SPECIFICATIONS .......................................................................11

ANALOG CHARACTERISTICS (CS5351-KS/KZ) ..................................................................11

ANALOG CHARACTERISTICS (CS5351-BS/BZ) ..................................................................12

DIGITAL DECIMATION FILTER CHARACTERISTICS.......................................................... 13

DC ELECTRICAL CHARACTERISTICS................................................................................. 16

DIGITAL CHARACTERISTICS............................................................................................... 16

THERMAL CHARACTERISTICS............................................................................................ 16

ABSOLUTE MAXIMUM RATINGS ......................................................................................... 17

SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT................................................. 18

5 PARAMETER DEFINITIONS ................................................................................................... 21

6 PACKAGE DIMENSIONS .....................................................................................................22

7 ADDENDUM ............................................................................................................................ 24

CS5351

LIST OF FIGURES

Figure 1. Typical Connection Diagram ............................................................................................5

Figure 2. CS5351 Master Mode Clocking ....................................................................................... 7

Figure 3. CS5351 Recommended Analog Input Buffer ................................................................... 9

Contacting Cirrus Logic Support

For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find one nearest you go to <http://www.cirrus.com/corporate/contacts/sales.cfm>

IMPORTANT NOTICE

"Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. "Advance" product inf ormation describes products that are in development and subject to development changes. Cirrus Logic, I nc. and its subsidiari es ("Cirrus") believe that the inf ormation contained in this document is accurate and reliable. However, the informati on is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant i nformation to verify, before pl acing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infrin gement, and l imitation of liabil ity. No responsibility is assumed by Cirrus for the use of thi s information, including use of this information as the basis for manufacture or sale of any items, or for i nfringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishi ng this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property ri ghts. Cirrus owns the copyrights of the information contained herein and gives consent for copies to be made of the information only for use within your organization wi th respect to Cirrus integrated circuits or other parts of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.

An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in thismaterial and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. An export license and/or quota needs to be obtained from the competent authorities of the Chinese Government if any of the products or technologies describ ed in this material is subject to the PRC Foreign Trade Law and i s to be exported or taken out of the PRC.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK.

Cirrus Logic, Cirrus, and the Cirrus Logi c logo designs are trademarks of Cirrus Logic, Inc. All other br and and pr oduct names in this document may be trademarks or service marks of their r especti ve owners.

2 DS565PP2

CS5351

Figure 4. Single Speed Mode Stopband Rejection ....................................................................... 14

Figure 5. Single Speed Mode Transition Band ............................................................................. 14

Figure 6. Single Speed Mode Transition Band (Detail)................................................................. 14

Figure 7. Single Speed Mode Passband Ripple ........................................................................... 14

Figure 8. Double Speed Mode Stopband Rejection...................................................................... 14

Figure 9. Double Speed Mode Transition Band ............................................................................ 14

Figure 10. Double Speed Mode Transition Band (Detail) ............................................................. 15

Figure 11. Double Speed Mode Passband Ripple ........................................................................ 15

Figure 12. Quad Speed Mode Stopband Rejection ...................................................................... 15

Figure 13. Quad Speed Mode Transition Band............................................................................. 15

Figure 14. Quad Speed Mode Transition Band (Detail)................................................................ 15

Figure 15. Quad Speed Mode Passband Ripple........................................................................... 15

Figure 16. Master Mode, Left Justified SAI................................................................................... 19

Figure 17. Slave Mode, Left Justified SAI..................................................................................... 19

Figure 18. Master Mode, I Figure 19. Slave Mode, I

Figure 20. OVFL Output Timing.................................................................................................... 19

Figure 21. Left-Justified Serial Audio Interface ............................................................................. 20

Figure 22. I

Figure 23. OVFL Output Timing, I2S Format ................................................................................ 20

Figure 24. OVFL Output Timing, Left-Justified Format ................................................................. 20

Figure 25. CS5351/CS5361 Analog Input Buffer .......................................................................... 24

S Serial Audio Interface............................................................................................. 20

S SAI .................................................................................................. 19

S SAI .................................................................................................... 19

LIST OF TABLES

Table 1. CS5351 Mode Control ............................................................................................................. 6

Table 2. CS5351 Common Master Clock Frequencies ........................................................................ 7

Table 3. CS5351 Slave Mode Clock Ratios .......................................................................................... 8

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1 PIN DESCRIPTIONS

Pin Name # Pin Description

RST

M/S

LRCK

SCLK

MCLK

GND

SDOUT

MDIV

HPF

S/LJ

M0 M1

OVFL

AINR AINL

VQ1 VQ2 VQ3

REF_GND

FILT+

Reset (Input) - The device enters a low power mode when low.

Master/Slave Mode (Input) - Selects operation as either clock master or slave.

Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the

serial audio data line.

Serial Clock (Input/Output) - Serial clock for the serial audio interface.

Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters.

6 Digital Power (Input) - Positive power supply for the digital section.

Ground (Input) - Ground reference. Must be connected to analog ground.

7,18

Logic Power (Input) - Positive power for the digital input/output.

Serial Audio Data Output (Output) - Output for two’s complement serial audio data.

MCLK Divider (Input)-Enables a master clock divide by two function.

High Pass Filter Enable (Input)-Enables the Digital High-Pass Filter.

Serial Audio Interface Format Select (Input) -Selects either the left-justified or I2S format for the SAI.

13,

Mode Selection (Input) - Determines the operational mode of the device.

Overflow (Output, open drain) - Detects an overflow condition on both left and right channels.

Analog Input (Input) - The full scale analog input level is specified in the Analog Characteristics specifi-

16,

cation table.

Quiescent Voltage (Input/Output) - Filter connection for the internal quiescent reference voltage.

17, 20,

19 Analog Power (Input) - Positive power supply for the analog section.

Reference Ground (Input) - Ground reference for the internal sampling circuits.

Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.

RST 124FILT+

M/S 223REFGND

LRCK 322VQ3

SCLK 421AINR

MCLK 520VQ2

VD 619VA

GND 718GND

VL 817VQ1

SDOUT 916AINL

MDIV 10 15 OVFL

HPF 11 14 M1

S/LJ 12 13 M0

CS5351

4 DS565PP2

2 TYPICAL CONNECTION DIAGRAM

CS5351

+5V

47µF

+5 V to 3.3 V

1µF

Analog

Input

Buffer

(Figure 3 )

1µF

0.1

1µF 0.1µF

0.1

FILT+

0.1µF

REFGND

VQ 2

VQ 1

AINL

AINR

VA V L

Ω

5.1

CS5351

A/D CONVERTER

0.1 µF

0.1µF

OVFL

RST

S/LJ

M/S

HPF

MDIV

SDOUT

LRCK

SCLK

MCLK

10 k

Ω

+5V to 2.5V

Power Down

and Mode

Se tting s

Audio Data

Processor

Timing Logic

and Clock

GND

Figure 1. Typical Connection Diagram

DS565PP2 5

CS5351

3 APPLICATIONS

3.1 Operational Mode/Sample Rate Range Select

The output sample rate, Fs, can be adjusted from 2kHz to 192kHz. The CS5351 must be set to the proper speed mode via the mode pins, M1 and M0. Refer to Table 1.

M1 (Pin 14) M0 (Pin 13) MODE Output Sample Rate (Fs)

0 0 Single Speed Mode 2kHz - 50kHz 0 1 Double Speed Mode 50kHz - 100kHz 1 0 Quad Speed Mode 100kHz - 192kHz 11Reserved

Table 1. CS5351 Mode Control

3.2 System Clocking

The device supports operation in either Master Mode, where the left/right and serial clocks are synchronously generated on-chip, or Slave Mode, which requires external generation of the left/right and serial clocks. The device also includes a master clock divider in Master Mode where the master clock will be internally divided prior to any other internal circuitry when MDIV is enabled, set to logic 1. In Slave Mode the MDIV pin needs to be disabled, set to logic 0.

6 DS565PP2

CS5351

3.2.1 Master Mode

In Master mode, LRCK and SCLK operate as outputs. The left/right and serial clocks are internally derived from the master clock with the left/right clock equal to Fs and the serial clock equal to 64x Fs, as shown in Figure 2. Refer to Table 2 for common master clock frequencies

MCLK

÷ 1

÷ 2

SAMPLE RATE (kHz)

32 8.192 16.384

44.1 11.2896 22.5792 48 12.288 24.576 64 8.192 16.384

88.2 11.2896 22.5792 96 12.288 24.576

176.4 11.2896 22.5792 192 12.288 24.576

Table 2. CS5351 Common Master Clock Frequencies

÷ 256

÷ 128

÷ 64

Single Speed

Double

Speed

÷ 4

MDIV

÷ 2

÷ 1

Figure 2. CS5351 Master Mode Clocking

MDIV = 0

MCLK (MHz)

Single

Speed

Double

Speed

Quad

M0M1

MDIV = 1

MCLK (MHz)

LRCK Output

(Equal to Fs)

SCLK Output

DS565PP2 7

CS5351

3.2.2 Slave Mode

LRCK and SCLK operate as inputs in Slave mode. The left/right clock must be synchronously derived from the master clock and be equal to Fs. It is also recommended that the serial clock be synchronously derived from the master clock and be equal to 64x Fs to maximize system performance. Refer to Table 3 for required clock ratios.

Single Speed Mode Fs = 2kHz to 50kHz

MCLK/LRCK Ratio 256x (512x)* 128x (256x)* 128x (256x)*

SCLK/LRCK Ratio 32x, 64x, 128x 32x, 64x 64x

Double Speed Mode

Fs = 50kHz to 100kHz

Quad Speed Mode

Fs = 100kHz to 192kHz

*Available when MDIV = 1 (for Master Mode)

Table 3. CS5351 Slave Mode Clock Ratios

3.3 Power-up Sequence

Reliable power-up can be accomplished by keeping the device in reset until the power supplies, clocks and configuration pins are stable. It is also recommended that reset be enabled if the analog or digital supplies drop below the minimum specified operating voltages to prevent power glitch related issues.

The internal reference voltage must be stable for the device to produce valid data. Therefore, there is a delay between the release of reset and the generation of valid output, due to the finite output impedance of FILT+ and the presence of the external capacitance.

3.4 Analog Connections

The analog modulator samples the input at 6.144 MHz (MCLK=12.288 MHz). The digital filter will reject signals within the stopband of the filter. However, there is no rejection for input signals which are

× 6.144 MHz) the digital passband frequency, where n=0,1,2,...Refer to Figure 3 which shows the sug-

(n gested filter that will attenuate any noise energy at 6.144 MHz, in addition to providing the optimum source impedance for the modulators. The use of capacitors which have a large voltage coefficient (such as general purpose ceramics) must be avoided since these can degrade signal linearity.

Please see the Addendum at the end of the datasheet for an analog input buffer that can be used with both the CS5351 as well as the CS5361 with a simple change in the bill of materials.

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