Cirrus Logic CS5331A-BS, CS5330A-KS, CS5330A-BS Datasheet

CS5330A

CS5331A

8-Pin, Stereo A/D Converter for Digital Audio

Features

Single +5 V Power Supply

•

18-Bit Resolution

•

94 dB Dynamic Range

•

Linear Phase Digital Anti-Alias Filtering

•

0.05dB Passband Ripple 80dB Stopband Rejection

Low Power Dissipation: 150 mW

•

Power-Down Mode for Portable Applications

Complete CMOS Stereo A/D System

•

Delta-Sigma A/D Converters Digital Anti-Alias Filtering S/H Circuitry and Voltage Reference

Adjustable System Sampling Rates

•

including 32kHz, 44.1 kHz & 48kHz

General Description

The CS5330A / 31A is a complete stereo analog-todigital converter which performs anti-alias filtering, sampling and analog-to-digital conversion generating 18-bit values for both left and right inputs in serial form. The output sample rate can be infinitely adjusted between 2 and 50 kHz.

The CS5330A / 31A operates from a single +5V supply and requires only 150 mW for normal operation, making it ideal for battery-powered applications.

The ADC uses delta-sigma modulation with 128X oversampling, followed by digital filtering and decimation, which removes the need for an external anti-alias filter. The linear-phase digital filter has a passband to

21.7 kHz, 0.05 dB passband ripple and >80 dB stopband rejection. The device also contains a high pass filter to remove DC offsets .

The device is available in a 0.208" wide, 8-pin surface mount package.

ORDERING INFORMATION:

Model Temp. Range Package Type

CS5330A-KS -10° to 70°C 8-pin plastic SOIC CS5331A-KS -10° to 70°C 8-pin plastic SOIC CS5330A-BS-40° to +85°C8-pin plastic SOIC CS5331A-BS-40° to +85°C8-pin plastic SOIC

Voltage Reference

AINL

S/H

AINR

AGND

Cirrus Logic, Inc. Crystal Se micond ucto r Prod uct Divisi on

P.O. Box 17847, Austin, TX 78760 (512) 445-7222 FAX: (512) 445-7581 http://www.crystal.com

S/H

VA+

LP Filter

DAC

Comparator

MCLK

Digital Decimation

SCLK

423

Serial Output Interface

Filter

LRCK

High Pass Filter

SDATA

MAR ’99

DS138F2

CS5330A/CS5331A

ANALOG CHARACTERISTICS (T

Fs = 48 kHz; MCLK = 12.288 MHz; SCLK = 3.072 MHz; Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified; Logic 0 = 0V, Logic 1 = VD+)

Parameter Symbol

Temperature Range T

= 25°C; VA+ = 5V; -1 dBFS Input Sinewave, 997 Hz;

5330A/31A-KS

Min Typ Max

A -10 to +70 -40 to +85 °C

5330A/31A-BS

Min Typ Max Units

Dynamic Performance

Dynamic Range A-weighted 88 94 -

86 92 -

Total Harmonic Distortion+Nois e (Note 1)

-1dB

-20dB

-60dB Total Harmonic Distortion -1dB THD - 0.003 0.02 - 0.003 0.02 % Interchannel Phase Deviation - 0 - - 0 - Degree Interchannel Isolation (dc to 20 kHz) - 90 - - 90 - dB

THD+N

- -84 75

- -72 66

- -32 26

86 94 84 92 -

- -84 75

- -72 66

- -32 26

dB dB

dB dB dB

dc Accuracy

Interchannel Gain Mismatch - 0.1 - - 0.1 - dB Gain Error Gain Drift - 150 - - 150 Offset Error (Note 2) - - 0 - - 0 LSB

--±10 - - ±10

ppm/°C

Analog Input

Full Scale Input Voltage Range VIN 3.6 4.0 4.4 3.6 4.0 4.4 Vpp Input Impedance (Fs = 48 kHz) ZIN - 100 - - 100 Input Bias Voltage - 2.4 - - 2.4 - V

kΩ

Power Supplies

Power Supply Current (Note 3)

VA+ Power down

Power Dissipation (Note 3)

Normal Power Down

Power Supply Rejection Ratio PSRR - 50 - - 50 - dB

* Refer to Parameter Definitio ns at the end of th is data sheet. Notes:1.Referenced to typical full-scale input voltage (4.0 Vpp)

2.Internal highpass filter removes offset.

3.For max power calculations, VD = 5.25 V.

IA+

-3042

- 100 1000

- 150 220

- 0.5 5.25

-3042

- 100 1000

- 150 220

- 0.5 5.25

µA

mW mW

2 DS138F2

DIGITAL CHARACTERISTICS

= 25 °C; VA+ = 5V ± 5%)

Parameter Symbol Min Typ Max Units

CS5330A/CS5331A

High-Level Input Voltage V Low-Level Input Voltage V High-Level Output Voltage at lo = -20 µA Low-Level Output Voltage at lo = 20 µA Input Leakage Current I

IH 2.4 - - V IL --0.8V

OH (VD+)-1.0 - - V OL --0.4V

in --

±10.0 µA

DIGITAL FILTER CHARACTERISTICS

= 25 °C; VA+ = 5V ± 5%; Fs = 48 kHz)

Parameter Symbol Min Typ Max Units

Passband (0.05 dB) (Note 4) 0.02 - 21.7 kHz Passband Ripple - -

±0.05 Stopband (Note 4) 29 - 6115 kHz Stopband Attenuation (Note 5) 80 - - dB Group Delay (Note 6) t Group Delay Variation vs. Frequency

gd - 15/Fs - s

∆t

--0

High Pass Filter Characteristics

Frequency Response: -3 dB (Note 4)

-0.1 dB

3.7 20

Phase Deviation @ 20 Hz (Note 4) - 10 - Degree Passband Ripple - - 0 dB

Notes:4.Filter characteristics scale with output sa mple rate.

5.The analog modulator samples the input at 6.144 MHz for an output sample rate of 48 kHz. There is no rejection of input signals which are multiples of the sampling frequency ( n x 6.144 MHz ±21.7kHz

where n = 0,1,2,3...).

6.Group delay for Fs = 48kHz, t

= 15/48kHz = 312µs

µs

Hz Hz

DS138F2 3

CS5330A/CS5331A

ABSOLUTE MAXIMUM RATINGS (AGND = 0V, all voltages with respect to ground.)

Parameter Symbol Min Typ Max Units

DC Power Supply: VA+ -0.3 - +6.0 V Input Current, Any Pin Except Supplies (Note 7) Iin - Analog Input Voltage (Note 8) V Digital Input Voltage (Note 8) V Ambient Temperature (power applied) T Storage Temperature T

INA -0.7 - (VA+)+0.7 V IND -0.7 - (VA+)+0.7 V

A -55 - +125

stg -65 - +150

Notes:7.Any Pin except s upplies. Trans ient currents of up to +/- 100 mA on the analog in put pins will n ot

cause SCR latch-up.

8.The maximum over/under voltage is limited by the input current.

WARNING:Operation at or beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes.

±10

°C °C

RECOMMENDED OPERATING CONDITIONS

(AGND = 0V; all voltages with respect to ground)

Parameter Symbol Min Typ Max Units

DC Power Supplies: VA+ 4.75 5.0 5.25 V Analog Input Voltage (Note 9) V Analog Input Bias Voltage 2.2 2.4 2.6 V

Note: 9.The output codes will clip at full scale with in put signals > Full Scale and < VA+.

IN -4-Vpp

Specifications are subject to change without notice.

4 DS138F2

CS5330A/CS5331A

SWITCHING CHARACTERISTICS (T

1 = VA+; C

= 20 pF) Switching characteristics are guaranteed by characterization.

= 25 °C; VA+ = 5V ± 5%; Inputs: Logic 0 = 0V, Logic

Parameter Symbol Min Typ Max Units

Output Sample Rate Fs 2 - 50 kHz MCLK Period MCLK / LRCK = 256 t MCLK Low MCLK / LRCK = 256 t MCLK High MCLK / LRCK = 256 t MCLK Period MCLK / LRCK = 384 t MCLK Low MCLK / LRCK = 384 t MCLK High MCLK / LRCK = 384 t MCLK Period MCLK / LRCK = 512 t MCLK Low MCLK / LRCK = 512 t MCLK High MCLK / LRCK = 512 t

clkw

clkl

clkh

clkw

clkl

clkh

clkw

clkl

clkh

78 1000 ns 31 - 1000 ns 31 - 1000 ns 52 1000 ns 20 - 1000 ns 20 - 1000 ns 39 1000 ns 13 - 1000 ns 13 - 1000 ns

MASTER MODE

SCLK falling to LRCK t SCLK falling to SDATA valid t

mslr

sdo

-10 - 10 ns

-10 - 35 ns

SCLK Duty cycle - 50 - %

SLAVE MODE

LRCK duty cycle 25 50 75 % SCLK Period t SCLK Pulse Width Low t SCLK Pulse Width High t SCLK falling to SDATA valid t LRCK edge to MSB valid t SCLK rising to LRCK edge delay t

sclkw

sclkl

sclkh

dss

lrdss

slr1

(Note 10) - - ns (Note 11) - - ns

20 - - ns

- - (Note 12) ns

20 - - ns

LRCK edge to rising SCLK setup time t slr2 (Note 12) - - ns

Notes: 10.

64 F

11.

−15 ns 12.

128 F

256 F

+ 5 ns

DS138F2 5

CS5330A/CS5331A

SCLK output

mslr

LRCK output

sdo

SDATA

SCLK to SDATA LRCK - MASTER mode (CS53 30A)

SCLK input

(SLAVE mode)

LRCK input

(SLAVE mode)

SDATA

slr1tslr2

lrdss

MSB MSB-1 MSB-2

sclkl

sclkh

sclkw

dss

SCLK output

mslr

LRCK output

sdo

SDATA

SCLK to SDATA LRCK - MASTER mode (CS5331A)

SCLK input

(SLAVE mode)

LRCK input

(SLAVE mode)

SDATA

slr1tslr2

sclkl

sclkh

sclkw

MSB MSB-1

dss

SCLK to LRCK & SDATA - SLAVE mode (CS5 330A)

SCLK to LRCK & SDATA - SLAVE mode (CS5331A)

6 DS138F2

Analog

Input

Circuits

150

+5V

Analog

Ω

.47 µF

10 µF

.01 µF

0.1 µF

AINL

AINR

VA+

CS5330A CS5331A

MCLK

SCLK

LRCK

SDATA

CS5330A/CS5331A

Audio Data

Processor

Ω

1 k

Ω

1 k

Ω

1 k

Ω

1 k

Timing

Logic

Clock

Ω

47 k

* Required for Master mode only

** Optional if analog input circuits biased to within ± 5% of CS5330A/CS5331A

nominal input bias voltage

AGND

Figure 1. Typical Connection Diagram

DS138F2 7

CS5330A/CS5331A

GENERAL DESCRIPTION

The CS5330A and CS5331A are 18-bit, 2-channel Analog-to-Digital Converters designed for digital audio applications. Each device uses two one-bit delta-sigma modulators which simultaneously sample the analog input signals at 128 times the output sample rate (Fs). The resulting serial bit streams are digitally filtered, yielding pairs of 18-bit values. This technique yields nearly ideal conversion perfor mance independent of input frequency and amplitude. The converters do not require difficult-to-design or expensive anti-alias filters and do not require exter nal sample-and-hold amplifiers or a voltage reference.

The CS5330A and CS5331A differ only in the output serial data format. These formats are discussed in the following sections and shown in Figures 2 and 3.

An on-chip voltage reference provides for a single-ended input signal range of 4.0 Vpp. Output

data is available in serial form, coded as 2’s complement 18-bit numbers. Typical power consumption is 150 mW which can be further reduced to 0.5 mW using the Power-Down mode.

For more information on delta-sigma modulation, see the references at the end of this data sheet.

SYSTEM DESIGN

master clock frequencies. The output sample rate is equal to the frequency of the Left / Right Clock (LRCK). The serial nature of the output data results in the left and right data words bein g read at different times. However, the words within an LRCK cycle represent simultaneously sampled analog inputs. The serial clock (SCLK) shifts the digitized audio data from the internal data registers via the SDATA pin.

Serial Data Interface

LRCK

(kHz)

32 8.1920 12.2880 16.3840

44.1 11.2896 16.9344 22.5792 48 12.2880 18.4320 24.5760

Table 1. Common Clock Frequencies

256× 384× 512×

MCLK (MHz)

The CS5330A and CS5331A can be operated in either Master mode, where SCLK and LRCK are outputs, or SLAVE mode, where SCLK and LRCK are inputs.

Master Mode

In Master mode, SCLK and LRCK are outputs which are internally derived from MCLK. The CS5330A/31A will divide MCLK by 4 to gener-

ate a SCLK which is 64× Fs and by 256 to generate LRCK. The CS5330A and CS5331A can be placed in the Master mode with a 47 kohm pull-down resistor on the SDATA pin

as shown in Figure 1.

Very few external components are required to support the ADC. Normal power supply decoupling components and a resistor and capacitor on each input for anti-aliasing are all that’s required, as shown in Figure 1.

Slave Mode

LRCK and SCLK become inputs in SLAVE mode. LRCK must be externally derived from MCLK and be equal to Fs. The frequency of

SCLK should be equal to 64× LRCK, though

Master Clock

other frequencies are possible.

The master clock (MCLK) runs the digital filter and is used to generate the delta-sigma modulator sampling clock. Table 1 shows some common

8 DS138F2

MCLK frequencies of 256×, 384×, and 512× Fs are supported. The ratio of the applied MCLK to

CS5330A/CS5331A

LRCK is automatically detected during power-up and internal dividers are set to generate the ap-

propriate internal clocks.

CS5330A

The CS5330A data output format is shown in Figure 2. Notice that the MSB is clocked by the transition of LRCK and the remaining seventeen data bits are clocked by the falling edge of SCLK. The data bits are valid during the rising edge of SCLK.

LRCK

SCLK

17 17

18192021 22

CS5331A

The CS5331A data output format is shown in Figure 3. Notice the one SCLK period delay between the LRCK transitions and the MSB of the data. The falling edges of SCLK caus e the ADC to output the eighteen data bits. The data bits are valid during the rising edge of SCLK. LRCK is also inverted compared to the CS5330A interface. The CS5331A interface is compatible with

31 0 1

192021 2223

31 0 1

SDATA

LRCK

SCLK

SDATA

17 16

Left Audio Data Right Audio Data

17 16

Left Audio Data Right Audio Data

Figure 2. Data Output Timing - CS5330A

1819202122 31

1716

1920212223

31 0 1

Figure 3. Data Output Timing - CS5331A (I2S compatible)

DS138F2 9

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