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CS5322-KL
Datasheet
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Cirrus Logic CS5322-KL, CS5322-BL, CS5321-KL1, CS5321-BL1, CS5321-BL Datasheet

...
CS5320/21/22
24-Bit Variable Bandwidth A/D Converter Chipset

Features

l CMOS A/D Converter Chipset l Dynamic Range
- 130 dB @ 25 Hz Bandwidth
- 121 dB @ 411 Hz Bandwidth
l Delta-Sigma Archite c ture
- Fourth-Order Modulator
- Variable Oversampling: 64X to 4096X
- Internal Track-and-Hold Amplifier
l CS5321 Signal- to-Distortion: 115 dB l Clock Jitter Tolerant Architecture l Input Voltage Range: +4.5 V l Flexible Filter Chip
- Hardware or Software Selectable Options
- Seven Selectable Filter Corners (-3 dB)
Frequencies: 25, 51, 102, 205, 411, 824 and 1650 Hz
l Low Power Dissipation: <100 mW

Description

The CK5320 and CK5321 Chipsets function as a unique A/D converter intended for very high resolution measure­ment of signals belo w 15 00 Hz. The CK 5320 Ch ipset is a cost effective com mercial grade solution for appl ica­tions which require a high dynamic range A/D converter. The chipsets perform sampling, A/D conversion, and anti-alias filtering.
The CS5320 and CS5321 use Delta-S igma modulation to produce highly accurate conversions. The ∆Σ modula­tor oversamples, virtually eliminating the need for external analog anti-alias filters. The CS5322 linear­phase FIR digital filter decim ates the output to any on e of seven selectable update periods: 16, 8, 4, 2, 1, 0.5 and 0.25 millisecon ds . Data i s ou tput fr om t he di git al fi l­ter in a 24-bit serial format.
ORDERING INFORMATION*
Chip Sets Kits
CS5320-KL & CS5322-KL CK5320-KL1 CS5321-BL & CS5322-KL CK5321-KL1 CS5321-BL & CS5322-BL CK5321-BL1
CS5320/21 CS5322
V
AINR
AIN+
AIN-
VREF+
VREF-
dd1
V
ss1
AGND
Analog
Modulator
V
V
ss2
dd2
DGND
Preliminary Product Information
* Refer to Table 5
R/W
CSCLKINSYNCVD+
LPWR OFST
MDAT A
HBR
This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.
RESET
MSYNC
MFLG
MCLK
MDAT A
VD+
DGND
CSEL
H/S
TDATA PWDN USEOR DGND
Copyright  Cirrus Logic, Inc. 1999
(All Rights Reserved)
Digital
Filter
RSEL SCLK SID SOD ERROR DRDY ORCAL DECA DECB DECC
DS454PP1
OCT ‘99
1

TABLE OF CONTENTS

1. CHARACTERISTICS AND SPECIFICATIONS............................. ...... ....... ..... 4
CS5320 AND CS5321 ANALOG CHARACTERISTICS ............................. 4
CS5320 AND CS5321 SWITCHING CHARACTERISTICS ........................ 6
CS5320 AND CS5321 DIGITAL CHARACTERISTICS .............................. 7
CS5320 AND CS5321 RECOMMENDED OPERATION CONDITIONS ....7
CS5320 AND CS5321 ABSOLUTE MAXIMUM RATINGS ......................... 7
CS5322 FILTER CHARACTERISTICS ......................................................8
CS5322 POWER SUPPLY .......................................................................10
CS5322 SWITCHING CHARACTERISTICS ............................................ 10
CS5322 DIGITAL CHARACTERISTICS ...................................................15
CS5322 RECOMMENDED OPERATION CONDITIONS ......................... 15
CS5322 ABSOLUTE MAXIMUM RATINGS ............................................. 15
2. GENERAL DESCRIPTION ............................................................................16
2.1. Analog Input ......................................................................................18
2.2. The OFST Pin.................................................................................... 18
2.3. Input Range and Overrange Conditions ............................................19
2.4. Voltage Reference.............................................................................20
2.5. Clock Source ..................................................................................... 20
2.6. Low Power Mode...............................................................................21
2.7. Digital Interface and Data Format...................................................... 21
2.8. Performance......................................................................................22
2.9. Power Supply Considerations............................................................ 23
2.10. Power Supply Rejection Ratio.........................................................23
2.11. RESET Operation............................................................................23
2.12. Power-down Operation.................................................................... 23
2.13. SYNC Operation..............................................................................24
2.14. Serial Read Operation.....................................................................24
2.15. Serial Write Operation ..................................................................... 25
2.16. Offset Calibration Operation............................................................25
2.17. Status Bits .......................................................................................26
2.18. Board Layout Considerations .......................................................... 28
3. CS5320/21 PIN DESCRIPTIONS ..................................................................29
Power Supplies ......................................................................................... 29
Analog Inputs ............................................................................................ 29
Digital Inputs ............................................................................................. 30
Digital Outputs ..........................................................................................30
CS5320/21/22

Contacting Cirrus Logic Support

For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts/
Preliminary product inf o rmation describes products whi ch are in production, b ut f or whi c h ful l characterization data i s not yet available. Advance p roduct infor­mation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document i s accurat e and reli able. However , t he infor mation is subje ct to chang e without noti ce and is provi d ed “AS IS” without warrant y of
any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other ri g ht s of third parties. This document is the pro perty of Cirrus Logi c, Inc. and i mplie s no licen se under patents, copyrights, tr ademarks, or trade secre ts. No part of this publication may be copied, reproduced , stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the pr i or writ ten consent of Cirrus Logic, Inc. It e ms f rom any Ci rrus L ogi c websi t e or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trade­marks and service marks can be found at http://www.cirrus.com.
2 DS454PP1
4. CS5322 PIN DESCRIPTIONS ... ....... ...... ....... ...... ...... ....... ............................. 31
Power Supplies ........................................................................................ 31
Digital Outputs .......................................................................................... 31
Digital Inputs ............................................................................................. 32
5. ORDERING INFORMATION ......................... ...... ...... ....... ...... ....... ...... ....... ... 34
6. PARAMETER DEFINITIONS......................................................................... 35
7. PACKAGE DIMENSIONS ............................................................................. 36

LIST OF FIGURES

Figure 1. Rise and Fall Times ..................................................................................... 6
Figure 2. CS5320 and CS5321 Interface Timing, HBR=1 .......................................... 6
Figure 3. CS5322 Filter Response ............................................................................. 8
Figure 4. CS5322 Digital Filter Passband Ripple f Figure 5. CS5322 Digital Filter Passband Ripple f Figure 6. CS5322 Digital Filter Passband Ripple f Figure 7. CS5322 Digital Filter Passband Ripple f Figure 8. CS5322 Digital Filter Passband Ripple f Figure 9. CS5322 Digital Filter Passband Ripple f Figure 10. CS5322 Digital Filter Passband Ripple f Figure 11. CS5322 Impulse Response f Figure 12. CS5322 Impulse Response f
Figure 13. CS5322 Serial Port Timing ...................................................................... 11
Figure 14. TDATA Setup/Hold Timing ...................................................................... 12
Figure 15. DRDY Timing .......................................................................................... 13
Figure 16. RESET Timing ......................................................................................... 13
Figure 17. CS5320/21/CS5322 Interface Timing ...................................................... 14
Figure 18. CS5320/21 Block Diagram ...................................................................... 16
Figure 19. CS5322 Block Diagram ........................................................................... 17
Figure 20. System Connection Diagram ................................................................... 19
Figure 21. 4.5 Voltage Reference with two filter options .......................................... 20
Figure 22. 1024 Point FFT Plot with -20 dB Input, 100 Hz Input, ten averages ....... 22
Figure 23. 1024 Point FFT Plot with Full Scale Input, 100 Hz Input, ten averages .. 22 Figure 24. 1024 Point FFT Plot with Full Scale Input, 100 Hz Input, ten averages .. 22
CS5320/21/22
= 62.5 Hz .............................. ..... 8
0
= 125 Hz ................................... 8
0
= 250 Hz .............................. ..... 8
0
= 500 Hz ................................... 9
0
= 1000 Hz ................................. 9
0
= 2000 Hz ................................. 9
0
= 4000 Hz ............................... 9
= 62.5 Hz ................................................... 9
0
= 1000 Hz .................................................. 9
0
0

LIST OF TABLES

Table 1. Output Coding for the CS5320/21 and CS5322 Combination ................. 21
Table 2. Configuration Data Bits ............................................................................ 24
Table 3. Status Data (from the SOD Pin) ............................................................... 26
Table 4. Bandwidth Selection: Truth Table ............................................................ 27
Table 5. Detailed Ordering Information .................................................................. 34
DS454PP1 3

1. CHARACTERISTICS AND SPECIFICATIONS

CS5320/21/22

CS5320 AND CS5321 ANALOG CHARACTERISTICS (T

, V
V
dd1
= +5V; VD+ = 5V; AGND = DGND = 0V; HBR = V
dd2
LPWR = 0, MCLK = 1.024 MHz; Device connected as
dd
= (See Note 1); V
A
ss1
, V
ss2
= -5V;
shown in Figure 20, CS5322 used for filtering; Logic 1 = VD+, Logic 0 = 0V; unless otherwise specified.)
CS5320 CS5321
Parameter*
Symbol Min T yp Max Min Typ Max Unit

Dynamic Performance

Dynamic Range (Note 2) HBR = 1 f OFST = 1 f
HBR = 0 f OFST = 1 f
= 4000 Hz
O
= 2000 Hz
O
= 1000 Hz
f
O
= 500 Hz
f
O
= 250 Hz
f
O
= 125 Hz
f
O
= 62.5 Hz
f
O
= 4000 Hz
O
= 2000 Hz
O
= 1000 Hz
f
O
= 500 Hz
f
O
= 250 Hz
f
O
= 125 Hz
f
O
= 62.5 Hz
f
O
Signal-to-Distortion (Note 3)
HBR = 1 HBR = 0
DR
SDR
-
103
-
118
113
121
-
124
-
127
-
129
-
130
-
-
-
-
-
-
-
99 115 118 121 124 126 127
100-110
120
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
116
-
-
-
-
-
-
-
-
-
-
-
100 110
103 118 121 124 127 129 130
99 115 118 121 124 126 127
115 120
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
dB dB dB dB dB dB dB
dB dB dB dB dB dB dB
dB dB
Intermodulation Distorti on (Note 4) IMD - 105 - - 110 - dB

dc Accuracy

Full Scale Error (Note 5) FSE - 1 - - 1 - % Full Scale Drift (Note 5,6) TC
Offset (Note 5) V
FS
ZSE
-5--5-
-10 --10 -mV
ppm/°C
Offset after Calibration (Note 7) - ±100 - - ±100 - µV Offset Calibration Range (Note 8) - 100 - - 100 - %F.S. Offset Drift (Note 5,6) TC
ZSE
Notes: 1. CS5320-KL and CS5322-KL are guaranteed from 0
-60- -60-µV/°C
o
to 70o C. CS5322-BL is guaranteed from -40o to
+85o C. CS5321-BL is guaranteed from -55o to +85o C.
= CS5322 output word rate. Refer to “CS5322 FILTER CHARACTERISTICS” on page 8 for details
2. f
O
on the FIR Filter.
3. Characterized with full scale input signal of 50 Hz; fo = 500 Hz.
4. Characterized with input signals of 30 Hz and 50 Hz, each 6 dB down from full scale with fo = 1000 Hz.
5. Specification is for the parameter over the specified temperature range and is for the CS5320/21 device only (VREF = +4.5 V). It does not include the effects of external components; OFST = 0.
6. Drift specifications are guaranteed by design and/or characterization.
7. The offset after calibration specification applies to the effective offset voltage for a ±4.5 volt input to the CS5320/21 modulator, but is relative to the output digital codes from the CS5322 after ORCAL and USEOR have been made active.
8. The CS5322 offset calibration is performed digitally and includes ± full scale (±4.5 volts into CS5320/21). Calibration of offsets greater than ±5% of full scale will begin to subtract from the dynamic range.
4 DS454PP1
CS5320/21/22
CS5320 AND CS5321 ANALOG CHARACTERISTICS (Continued)
CS5320/21
Parameter*

Input Characteristics

Input Signal Frequencies (Note 9) BW dc - 1500 Hz Input Voltage Range (Note 10) V Input Overrange Voltage (Note 10) I

Power Supplies

DC Power Supply Currents (Note 11)
LPWR = 0 Positive Supplies
Negative Supplies
LPWR = 1 Positive Supplies
Negative Supplies
Power Consumption (Note 11)
Normal Operating Mode (Note12)
Lower Power Mode (Note 13) Power Down P Power Supply Rejection (dc to 128 kHz) (Note 14) PSR - 60 - dB
Symbol Min Typ Max Unit
-4.5 - +4.5 V
--5%F.S.
-
-
-
-
5.5
5.5
3.0
3.0
55 30
7.5
7.5
4.5
4.5
75 45
mA mA mA mA
mW mW
-2-mW
OVR
P
DN
P
IN
DL
D
Notes: 9. The upper bandwidth limit is determined by the CS5322 digital filter.
10. This input voltage range is for the configuration shown in Figure 20, the System Connection Diagram, and applies to signal from dc to f3 Hz. Refer to CS5322 Filter Characteristics for the values of f3.
11. All outputs unloaded. All logic inputs forced to V
or GND respectively.
dd
12. LPWR = 0.
13. The CS5321 power dissipation can be reduced under the following conditions:
a) LPWR=1; MCLK=512kHz, HBR=1 b) LWPR=1; MCLK=1.024MHz, HBR=0
14. Characterized with a 100 mVp-p sine wave applied separately to each supply.
* Refer to Parameter Definitions (immediately following pin descriptions at the end of this data sheet).
Specifications are subject to change without notice.
DS454PP1 5
CS5320/21/22
V
V
V
V

CS5320 AND CS5321 SWITCHING CHARACTERISTICS (T

, V
5V ± 5%; V
ss1
= -5V ± 5%; Inputs: Logic 0 = 0V Logic 1 = V+; CL = 50 pF (Note 15))
ss2
= (See Note 1); V
A
dd1
, V
Parameter Symbol Min T yp Max Units
MCLK Frequency (Note 16) f
c
0.250 1.024 1.2 MHz MCLK Duty Cycle 40 - 60 % MCLK Jitter (In-band) - - 300 ps Rise Times: Any Digital Input (Note 17)
Any Digital Output
Fall Times: Any Digital Input (Note 17)
Any Digital Output MSYNC Setup Time to MCLK rising t MSYNC Hold Time after MCLK rising t MCLK rising to Valid MFLG t MCLK rising to Valid MDATA t
t
risein
t
riseout
t
fallin
t
fallout
mss
msh
mfh
mdv
-
-
-
-
50
50
-
100 200
-
100
200 20 - - ns 20 - - ns
-140255ns
-170300ns
Notes: 15. Guaranteed by design, characterization, or test.
16. If MCLK is removed, the modulator will enter the power down mode.
17. Excludes MCLK input. MCLK should be driven with a signal having rise and fall times of 25 ns or faster.
t
risein
t
fallin
t
riseout
t
fallout
dd2
ns ns
ns ns
=
MCLK
MSYNC
MDATA
MFLG
t
mss
4.0
1.0

Figure 1. Rise and Fall Times

t
msh
t
mdv
VALID DATA
t
t
4.6
0.4
mdv
VALID DATA
mfh

Figure 2. CS5320 and CS5321 Interface Timing, HBR=1

6 DS454PP1
CS5320/21/22

CS5320 AND CS5321 DIGITAL CHARACTERISTICS (T

= (See Note 1); V
A
dd1
= V
dd2
=
5.0V ± 5%; GND = 0V; measurements performed under static conditions)
Parameter Symbol Min Typ Max Units
High-Level Input Drive Voltage (Note 18) V Low-Level Input Drive Voltage (Note 18) V
High-Level Output Voltage IOUT = -40 µA (Note 19) V Low-Level Output Voltage IOUT = +40 µA (Note 19) V Input Leakage Current I Digital Input Capacitance C Digital Output Capacitance C
IH
IL OH OL
LKG
IN
OUT
(Vdd)-0.6 - - V
--1.0V
(Vdd)-0.3 - - V
--0.3V
--±10µA
-9-pF
-9-pF
Notes: 18. Device is intended to be driven with CMOS logic levels.
19. Device is intended to be interfaced to CMOS logic. Resistive loads are not recommended on these pins.

CS5320 AND CS5321 RECOMMENDED OPERATION CONDITIONS (Voltages with

respect to GND = 0V, See Note 20)
Parameter Symbol Min Typ Max Units
DC Supply: Positive
Negative
Ambient Operating Temperature -KL
-BL
V
dd1,Vdd2
V
ss1,Vss2
T T
4.75
-4.75
A
A
0
-55
5.0
-5.0
-
-
5.25
-5.25 +70
+85
V V
°C °C
Notes: 20. The maximum voltage differential between the Positive Supply of the CS5320/21 and the Positive
Digital Supply of the CS5322 must be less than 0.25V.
CS5320 AND CS5321 ABSOLUTE MAXIMUM RATINGS * (Voltages with respect to
GND = 0V)
Parameter Symbol Min Max Units
DC Supply: Positive
Negative
V
dd1,Vdd2
V
ss1,Vss2
Input Current, Any Pin Except Supplies (Note 21) I Output Current I Total Power (all supplies and outputs) P Digital Input Voltage V Storage Temperature T
in
out
t
IND
stg
-0.3
+0.3
- ±10 mA
-25mA
-1W
-0.3 (Vdd)+0.3 V
-65 150 °C
Notes: 21. Transient currents of up to 100 mA will not cause SCR latch up.
*WARNING: Operation beyond these limits may result in permanent damage to the device. Normal operation is
not guaranteed at these extremes.
6.0
-6.0
V V
DS454PP1 7
CS5320/21/22

CS5322 FILTER CHARACTERISTICS (T

= (See Note 1); VD+ = 5.0V; GND = 0V;
A
CLKIN = 1.024 MHz; transfer function shown in Figure 3; unless otherwise specified.)
Output Word Rate
(Hz)
f
0
4000 2000 1000
500 250 125
62.5
Notes: 22. G
= -130 dB for all Output Word Rates.
SB
Passband f1
(Hz)
1500
750 375
187.5
93.8
46.9
23.4
Passband Flatness
RPB (dB)
0.2
0.04
0.08
0.1
0.1
0.1
0.1
-3dB Freq. f2 (Hz)
1652.5
824.3
411.9
205.9
102.9
51.5
25.7
Stopband f3 (Hz)
(Note 22)
31.25
dB
0
-3
G
SB
2000 1000
500 250 125
62.5
Group Delay
(ms)
7.25
14.5 29 58
116 232 464
-130
f1 f2 f3 f

Figure 3. CS5322 Filter Response Figure 4. CS5322 Digital Filter Passband Ripple

Figure 5. CS5322 Digital Filter Passband Ripple
= 125 Hz
f
0
= 62.5 Hz
f
0
Figure 6. CS5322 Digital Filter Passband Ripple
f0 = 250 Hz
8 DS454PP1
CS5320/21/22
1 8 15 22 29 36 43 50 57
Time (# of Output Words)
-5,250,000
-5,243,750
-5,237,500
-5,231,250
-5,225,000
-5,218,750
-5,212,500
-5,206,250
Digital Output Code
-5,240,723
7
Figure 7. CS5322 Digital Filter Passband Ripple
= 500 Hz
f
0
Figure 9. CS5322 Digital Filter Passband Ripple
= 2000 Hz
f
0
Figure 8. CS5322 Digital Filter Passband Ripple
f0 = 1000 Hz
Figure 10. CS5322 Digital Filter Passband Ripple
f0 = 4000 Hz
-5,206,250
-5,212,500
-5,208,328
-5,218,750
-5,225,000
-5,231,250
Digital Output Code
-5,237,500
-5,243,750
Figure 11. CS5322 Impulse Response,
= 62.5 Hz
f
0
-5,250,000 1 8 15 22 29 36 43 50 5
Time (# of Output Words)
Figure 12. CS5322 Impulse Response,
f0 = 1000 Hz
DS454PP1 9
CS5320/21/22

CS5322 POWER SUPPLY (T

= (See Note 1); VD+ = 5V; CLKIN = 1.024 MHz)
A
CS5322-K CS5322-B
Parameter
Min Typ Max Min Typ Max Unit
Power Supply Current: ID+ (Note 11) - 2.2 4 - 2.2 4 mA Power Dissipation: (Note 11)
PWDN Low
PWDN High

CS5322 SWITCHING CHARACTERISTICS (T

Inputs: Logic 0 = 0V Logic 1 = VD+; C
= 50 pF (Note 23)
L
-
-
11
0.6
20
2.5
= (See Note 1); VD+ = 5V ± 5%; DGND = 0V;
A
-
-
11
0.6
20
2.5
mW mW
Parameter Symbol Min Typ Max Units
CLKIN Frequency f
c
0.512 1.024 1.2 MHz CLKIN Duty Cycle 40 - 60 % Rise Times: Any Digital Input
Any Digital Output
Fall Times: Any Digital Input
Any Digital Output
t
t
rise
fall
-
-
-
-
50
50
-
100 100
-
100 100

Serial Port Read Timing

DRDY to Data Valid t RSEL Setup Time before Data Valid t Read Setup before CS
Active t Read Active to Data Valid t SCLK rising to New SOD bit t SCLK Pulse Width High t SCLK Pulse Width Low t SCLK Period t SCLK falling to DRDY falling t CS
High to Output Hi-Z t
Read Hold Time after CS
Inactive t
Read Select Setup to SCLK falling t
ddv
rss rsc rdv rdd rph
rpl
rsp
rst rch rhc rds
- - 25 ns 50 - - ns 20 - - ns
- - 50 ns
- - 50 ns 30 - - ns 30 - - ns
100 - - ns
- - 50 ns
- - 20 ns 20 - - ns 20 - - ns

Serial Port Write Timing

Write Setup Before CS Activ e t SCLK Pulse Width Low t SCLK Pulse Width High t SCLK Period t Write Setup Time to First SCLK falling t Data Setup Time to First SCLK falling t Write Select Hold Time after SCLK falling t Write Hold Time after CS
Inactive t
Data Hold Time after SCLK falling t
wsc
wpl
wph
wsp
wws
wds
wwh
whc
wdh
20 - - ns 30 - - ns 30 - - ns
100 - - ns
20 - - ns 20 - - ns 20 - - ns 20 - - ns 20 - - ns
ns ns
ns ns
23. Guaranteed by design, characterization and/or test.
10 DS454PP1
RSEL
CS5320/21/22
t
rss
DRDY
R/W
CS
SOD
SCLK
t
ddv
t
rsc
t
rdv
Hi-Z
MSB
t
rph
t
rds
MSB-1
t
rdd
t
rpl
LSB+1
t
rsp
Serial Port Read Timing
(R/W
= 1, CS = 0, RSEL = 1 DRDY Does not toggle if reading status, RSEL = 0)
LSB
t
rst
Hi-Z
t
t
rch
rhc
CS
t
t
wsc
whc
R/W
t
t
wws
wph
t
wwh
SCLK
t
wsp
t
wdh
MSB-1
t
LSB+1
wpl
LSB
SID
t
wds
MSB
Serial Port Write Timing
Figure 13. CS5322 Serial Port Timing
DS454PP1 11
CS5322 SWITCHING CHARACTERISTICS (continued)
Parameter Symbol Min Typ Max Units

Test Data (TDATA) Timing

SYNC Setup Time to CLKIN rising t SYNC Hold Time after CLKIN rising t TDATA Setup Time to CLKIN rising after SYNC t TDATA Hold Time after CLKIN rising t ORCAL Setup Time to CLKIN rising t ORCAL Hold Time after CLKIN rising t

DRDY Timing

CLKIN rising to DRDY falling t CLKIN falling to DRDY rising t CLKIN rising to ERROR change t

RESET Timing

RESET Setup Time to CLKIN rising t RESET Hold Time after CLKIN rising t SYNC Setup Time to CLKIN rising t SYNC Hold Time after CLKIN rising t
ss
sh tds tdh
os
oh
df dr ec
rs
rh ss sh
CS5320/21/22
20 - - ns 20 - - ns
-20-ns
-150-ns 20 - - ns 20 - - ns
-140-ns
-150-ns
-140-ns
20 - - ns 20 - - ns 20 - - ns 20 - - ns
CLKIN
SYNC
ORCAL
LSYNC*
TDATA
FILTER
SAMPLES
DATA
t
tds
sh
t
oh
t
rdh
VALID VALID
t
ss
t
os
t
Figure 14. TDATA Setup/Hold Timing
t
tds
t
tdh
12 DS454PP1
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