Cirrus Logic CS5181-BL Datasheet
CS5181
∆Σ
Modulator & 400 kHz to 625 kHz 16-Bit ADC
Features
l 16-Bit Delta-Sigma A/D Converter
l Fully Differential Input with 4.0 V
l Dynamic Range: 93 dB
l Spurious Free Dynamic Range: 90 dBc
l Harmonic Distortion: 89 dB
l Up to 625 kHz Output Word Rate
l No Missing Codes
l Non-Aliasing Low-Pass Digital Filter
l High Speed 3-Wire Se rial Interface
l Supply Requirements:
- VA+ = 5 V, VD+ = 3.3 V: 570 mW
l Modulator Output Mode
l Power-Down Mode
I
VA+
Range
pp
AGND
Description
CS5181 is a fully calibrated high-speed ∆Σ analog-todigital converter, capable of 625 kSamp les/second output word rate (OWR). The OWR scales with the master
clock. It consists of a 5th order ∆Σ modulato r, decim ation
filter, and serial in terfac e. Th e chip c an use the 2.3 75 V
on-chip voltage reference, or an external 2.5 V refer-
ence. The input voltag e ra nge is 1.6 × VREFIN V
differential. Multip le CS518 1s can be ful ly sy nchroni zed
in multi-channel applications with a sync signal. The part
has a power-down m ode to minimize power c onsumption at times of system inacti vity. The hig h speed digital
I/O lines have complementary signals to help reduce radiated noise from traces on the PC board layout. The
CS5181 can also be operated in m odulator-only mode
which provides the del ta-sigma modulator bitstr eam as
the output.
ORDERING INFORMATION
CS5181-BL -40 °C to +85 °C 28-pin PLCC
VD+
DGND
pp
fully
AIN+
AIN-
∆Σ
Modulator
VREF-
VREF+
VREFIN
VREFOUT
VREFCAP
x1.6
Reference
PWDN SYNC RESET MODE
Preliminary Product Information
Cirrus Logic, Inc.
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.crystal.com
Decimator Clock
Mode
MCLK
MCLK
MFLAG
Selector
SDO
Timing
and
Serial
Interface
Control
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright Cirrus Logic, Inc. 1999
(All Rights Reserved)
SDO
SCLK
SCLK
FSO
DS250PP1
APR ‘99
1
TABLE OF CONTENTS
CHARACTERISTICS/SPECIFICATIONS ................................................ ............4
ANALOG CHARACTERISTICS...................................................................4
DYNAMIC CHARACTERISTICS ................................................................. 5
DIGITAL CHARACTERISTICS....................................................................5
SWITCHING CHARACTERISTICS ........................................................ ..... 6
RECOMMENDED OPERATING CONDITIONS.......................................... 7
ABSOLUTE MAXIMUM RATINGS.............................................................. 7
GENERAL DESCRIPTION .................................................................................. 8
THEORY OF OPERATION .................................................................................. 8
Converter Initialization: Calibration and Synchronization ..........................8
Clock Generator ..........................................................................................9
Voltage Reference ......................................................................................9
Analog Input .............................................................................................10
Output Coding .......................................................................................... 10
Modulator-Only mode ............................................................................... 10
Instability Indicator .................................................................................... 12
Digital Filter Characteristics ...................................................................... 12
Serial Interface .......................................................................................... 12
Power Supplies / Board Layout ................................................................ 12
Power-down Mode .................................................................................... 14
PIN DESCRIPTIONS ......................................................................................... 15
PARAMETER DEFINITIONS ............................................................................. 18
APPENDIX A: CIRCUIT APPLICATIONS ......................................................... 20
PACKAGE OUTLINE DIMENSIONS ................................................................. 23
CS5181
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts/
Preliminary product info rmation describes products which are i n p roduction, but for which ful l char act er iza t i on da t a is not yet available. Advance produ ct i nformation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information
contained in this document is accurate and reli able. However , the i nformati on is sub ject to change with out no tice and i s provi ded “AS IS” withou t warranty of
any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights
of third parties. This document i s the propert y of Cirru s Logic, Inc. and implie s no licen se under patent s, copyri ghts, trademarks, or tr ade secrets. No part of
this publication may be copied, reproduced , stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or
otherwise) without the pri or wri tt en consen t of Ci rrus Logic, Inc. Items from any Cirrus Logic websi t e or di sk may be print ed for use by the user. However, no
part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical,
photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture
or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing
in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.
2 DS250PP1
TABLE OF FIGURES
1. Serial Port Timing (not to scale) .............................................................................. 6
2. RESET and SYNC logic and timing. ....................................................................... 8
3. CS5181 connection diagram for using the internal voltage reference. .................... 9
4. CS5181 connection diagram for using an external voltage reference. .................. 10
5. Modulator Only Mode Data RTZ Format. .............................................................. 11
6. Circuit to Reconstruct
Return-to-Zero (RTZ) Data from SDO/SDO into Original Modulator Bitstream.... 11
7. Magnitude versus frequency spectrum of modulator bitstream
(MCLK = 40.0 MHz). .............................................................................................. 11
8. Expanded view of the magnitude versus frequency spectrum of modulator
bitstream (MCLK = 40 MHz). ................................................................................. 11
9. CS5181 Digital Filter Magnitude Response (MCLK = 40 MHz) ............................. 12
10. CS5181 Digital Filter Phase Response (MCLK = 40 MHz) ................................... 12
11. CS5181 System Connection Diagram ................................................................... 13
12. Single amplifier driving only AIN+, with AIN- held at a steady dc value ................ 20
13. Performance of amplifier of Figure 11 overdriving AIN+ input to the
CS5181 at 3.8 VPP ............................................................................................... 20
14. Performance of amplifier of Figure 11 with AIN+ driven at 2.0 VPP ...................... 20
15. Four amplifier balanced driver. .............................................................................. 21
16. Performance of amplifier in Figure 14 ................................................................... 21
17. Performance of amplifier in Figure 14 ................................................................... 22
18. CS5181 Differential Non-linearity plot. (Data taken with repeating ramp) ............ 22
19. Histogram of DNL from Figure 17 ......................................................................... 22
20. CS5181 Noise Histogram, 32768 samples. ......................................................... 22
CS5181
DS250PP1 3
CHARACTERISTICS/SPECIFICATIONS
CS5181
ANALOG CHARACTERISTICS (T
DGND = 0 V; MCLK = 40.0 MHz; VREFIN = VREFOUT; MODE = VD+; Analog Source Impedance = 301 Ohms
with 2200 pF to AGND; Full-Scale input Sinewave at 22 kHz; Unless otherwise noted.)
Parameter Symbol Min Typ Max Unit
= -40 to 85 °C; VA+ = 5 V ±5%, VD+ = 3.3 V ±0.3V; AGND =
A
Dynamic Performance
Dynamic Range (Note 1) DR 89 93 - dB
Total Harmonic Distortion @ 22 kHz (Note 1) THD 84 89 - dB
Signal to (Noise + Distortion) SINAD 82 87 - dB
Spurious Free Dynamic Range SFDR 84 90 - dBc
Static Performance
Integral Nonlinear ity (Note 2) INL - ±2 - LSB
Differential Non-Linearity (Note 2) DNL - - ±0.5 LSB
Full Scale Error (Note 6) - ±8 - LSB
Full Scale Drift with Internal Reference (Notes 2 and 5) - ±50 - ppm/°C
Offset Error (Note 6) - ±8 - LSB
Offset Drift (Note 2) - ±6.0 - µV/°C
Analog Input
Differential Input Voltage Range (Note 3) - 1.6 X
VREFIN
Common Mode Range CMR 1 - VREFIN
Input Capacitance - 4.0 - pF
Differential Input Impedance (capacitive) - 300 - k
Common Mode Rejection Ratio (Note 2) CMRR 50 - - dB
Common Mode Input Current - ±160 ±320 µA
-V
+ 0.25
pp
V
Ω
Reference Input
VREFIN 2.25 2.375 2.6 V
VREFIN Current (Note 4) - 1 ±320 µA
Reference Output
VREFOUT Voltage 2.25 2.375 2.5 V
VREFOUT Output Current - - ±500 µA
VREFOUT Impedance - 0.1 -
Ω
Notes: 1. Dynamic range is tested with a 22 kHz input signal 60 dB below full scale.
2. Specification guaranteed by design, characterization, and/or test.
3. Full scale fully-differential input span is nominally 1.6 X the VREFIN voltage. The peak negative
excursion of the signals at AIN+ or AIN- should not go below AGND for proper operation.
4. VREFIN current is less than 1 µA unde r normal operation, but can b e as high a s ± 320 µA durin g calibratio n.
5. Drift of the on-chip reference alone is typically about ±30 ppm/°C. If using an external reference, total
full scale drift will be that of the external reference plus an additional ±20 ppm/°C, which is the typical
drift of the X1.6 buffer.
6. Applies after self-calibration at final operating ambient temperature.
4 DS250PP1
ANALOG CHARACTERISTICS (Continued)
Parameter Symbol Min Typ Max Unit
Power Supplies
Power Supply Current (MODE = 1, PWDN = 1) (Note 7)
VA1+, VA2+ = 5 V
VD1+, VD2+ = 3.3 V
CS5181
-
-
53
92.4
65
100
mA
mA
Power Supply Current (MODE = 1, PWDN
VA1+, VA2+ = 5 V
VD1+, VD2+ = 3.3 V
Power Supply Current (MODE = 0, PWDN
VA1+, VA2+ = 5 V
VD1+, VD2+ = 3.3 V
Power Supply Current (MODE = 0, PWDN
VA1+, VA2+ = 5 V
VD1+, VD2+ = 3.3 V
Power Supply Rejection (Note 9) PSRR - 55 - dB
Notes: 7. All outputs unloaded. All inputs except MCLK held static at VD+ or DGND.
8. Power consumpti on whe n PWDN
9. Measured with a 100 mV
= 0) (Notes 7, 8)
= 1) (Note 7)
= 0) (Notes 7, 8)
= 0 applies only for no master clock applied (MCLK held high or low).
sine wave on the VA+ supplies at a frequency of 100 Hz.
pp
-
-
-
-
-
-
3.7
0.062
53
18.9
3.7
0.062
6
0.2
65
22
6
0.2
mA
mA
mA
mA
mA
mA
DYNAMIC CHARACTERISTICS
Parameter Symbol Min Typ Max Unit
Modulator Sampling Frequency - MCLK - Hz
Output Word Rate - MCLK/64 - Hz
Filter Characteristics (Note 2)
-3 dB Corner - MCLK/142.3804 - Hz
Passband Ripple - - ±0.05 dB
Stopband Frequency - MCLK/128 - Hz
Stopband Rejection 90 - - dB
Group Delay - 2370/MCLK - s
DIGITAL CHARACTERISTICS
Parameter Symbol Min Typ Max Unit
High-Level Input Voltage V
Low-Level Input Voltage V
High-Level Output Voltage (I
Low-Level Output Voltage (I
Input Leakage Current I
Input Capacitance Cin - 6 - pF
DS250PP1 5
= -100 µA) V
O
= 100 µA) V
O
Specifications are subject to change without notice.
(TA = -40 to 85 °C; VD = 3.3V ±0.3V; AGND = DGND = 0 V)
IH
IL
OH
OL
in
2.0 - - V
--0.8V
2.7 - - V
--0.3V
-±1±10µA
CS5181
SWITCHING CHARACTERISTICS (T
= -40 to 85 °C; VA+ = 5 V ±5%, VD+ = 3.3 V ±0.3 V;
A
AGND = DGND = 0 V; MODE = VD+)
Parameter Symbol Min Typ Max Unit
Master Clock Frequency (Note 2) MCLK 0.512 25 to 40 41 MHz
Master Clock Duty Cycle 45 - 55 %
Rise Times (Notes 2, 10, and 11)
Any Digital Input, Except MCLK
MCLK
Any Digital Output
Fall Times (Notes 2, 10, and 11)
Any Digital Input, Except MCLK
MCLK
Any Digital Output
t
t
rise
fall
-
-
-
-
-
-
20
20
-
-
-
-
100
.2/MCLK
-
100
.2/MCLK
-
ns
s
ns
ns
s
ns
Calibration/Sync
RESET rising to MCLK rising
RESET
rising recognized, to FSO falling
-3 -ns
- 988205/MCLK - s
SYNC rising to MCLK rising - 3 - ns
SYNC rising recognized to FSO falling - 5161/MCLK - s
PWDN
rising recognized to FSO falling
SYNC high time
RESET
low time
- 5168/MCLK - s
1/MCLK - - s
1/MCLK - - s
Serial Port Timing (Note 12)
SCLK frequency - MCLK/3 - Hz
SCLK high time t
SCLK low time t
FSO falling to SCLK rising t
SCLK falling to new data bit t
SCLK rising to FSO rising t
1
2
3
4
5
-1/MCLK-s
-2/MCLK-s
-2/MCLK+2E-9 - s
-1.5 -ns
-1/MCLK-2E-9 - s
Notes: 10. Rise and Fall times are specified at 10% to 90% points on waveform.
11. RESET
12. Specifications applicable to complementary signals SCLK
, SYNC, and PWDN have Schmitt-trigger inputs.
FSO
t1t
2
SCLK
SDATA
t
3
t
4
XX
MSB MSB-1 LSB-1 LSB
and SDO.
t
5
XX
Figure 1. Serial Port Timing (not to scale)
6 DS250PP1
CS5181
RECOMMENDED OPERATING CONDITIONS (AGND = DGND = 0 V)
Parameter Symbol Min Typ Max Unit
DC Power Supplies Digital
Analog
Analog Reference Voltage VREFIN 2.25 2.5 2.6 V
AGND to DGND differential -100 0 100 mV
Operating Junction Temperature T
ABSOLUTE MAXIMUM RATINGS
Parameter Symbol Min Max Unit
DC Power Supplies Ground
Digital
Analog
Input Current, Any pin except Supplies I
Output Current I
Power Dissipation (Total) - 1000 mW
Analog Input Voltage V
Digital Input Voltage V
Ambient Operating Temperature T
Storage Temperature T
VD+
VA+
j
AGND/DGND
VD+
VA+
in
out
INA
IND
A
stg
3.0
4.75
3.3
5
3.6
5.25
--120°C
-0.3
-0.3
-0.3
(VD+) + 0.3
6.0
6.0
-±10mA
-±25mA
-0.3 (VA+) + 0.3 V
-0.3 (VD+) + 0.3 V
-40 85 °C
-65 150 °C
V
V
V
V
V
WARNING: Operation beyond these limits may result in permanent damage to the device. Normal operation is not
guaranteed at these extremes.
Specifications are subject to change without notice.
DS250PP1 7
CS5181
GENERAL DESCRIPTION
The CS5181 is a monolithic CMOS 16-bit A/D
converter designed to operate in continuous mode
after being reset.
The CS5181 can operate in modulator-only mode
in which the bit stream from the modulator is the
data output from the device.
THEORY OF OPERATION
The front page of this data sheet illustrates the
block diagram of the CS5181.
Converter Initialization: Calibration and Synchronization
The CS5181 does not have an internal power-on reset circuit. Therefore when power is first applied to
the device the RESET pin should be held low until
power is established. This resets the converter’s logic to a known state. When power is fully established
the converter will perform a self-calibration, starting
with the first MCLK rising edge after RESET goes
high. The converter will use 988,205 MCLK cycles
to complete the calibration and to allow the digital
filter to fully settle, after which, it will output fullysettled conversion words. The converter will then
continue to output conversion words at an output
word rate equal to MCLK/64. Figure 2 illustrates
the RESET and SYNC logic and timing for the converter.
The CS5181 is designed to perform conversions
continuously with an output rate that is equivalent
to MCLK/64. The conversions are performed and
the serial port is updated independent of external
controls. The converter is designed to measure differential bipolar input signals, and unipolar signals,
with a common mode voltage of between 1.0 V and
VREF + 0.25 V. Calibration is performed when the
RESET signal to the device is released. If RESET
is properly framed to MCLK, the converter can be
synchronized to a specific MCLK cycle at the system level.
The SYNC signal can also be used to synchronize
multiple converters in a system. When SYNC is
used, the converter does not perform calibration.
The SYNC signal is recognized on the first rising
edge of MCLK after SYNC goes high. SYNC
aligns the output conversion to occur every 64
MCLK clock cycles after the SYNC signal is recognized and the filter is settled. After the SYNC is
initiated by going high, the converter will wait
5,161 MCLK cycles for the digital filter to settle
before putting out a fully-settled conversion word.
To synchronize multiple converters in a system, the
SYNC pulse should rise on a falling edge of the
MCLK signal. This ensures that the SYNC input to
all CS5181s in the system will be recognized on the
next rising edge of MCLK. Use of the SYNC input
CS5181
RESET
MCLK
SYNC
8 DS250PP1
D
CLK
D
CLK
Figure 2. RESET and SYNC logic and timing.
Q
Q RESET
QSYNC
MCLK
RESET
FSO
988205 MCLK Cycles
MCLK
SYNC
FSO
5161 MCLK Cycles
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