Cirrus Logic CS4630-CM Datasheet

CS4630

CrystalClear SoundFusion PCI Audio Accelerator

Features

l 420 MIPs SLIMD

increased internal memo ry for greater
performance

l Hardware acceleration for Microsoft

DirectSound and DirectSound3D
Positional Audio

l Sensaura™ 3-D, 2 or 4 channel audio
l EAX™ 1.0 enhanced environmental audio

standard

l Unlimited-Voice Wavetable Synthesis with

Effects including DLS support

l Acoustic Echo Cancellation Hardware

Acceleration for NetMeeting

l 10 Band Graphic Equalization
l High Quality Hardware Sample Rate

Conversion (90+ dB Dynamic Range)

l PC/PCI, DDMA, and CrystalClear Legacy

Support (CCLS)

l PCI 2.1 Compliant PCI Interface



DSP Architecture with



Description

The CS4630 is a high performance upgrade to the
CS4624 PCI audio accelerato r. With support for l egacy
compatibility modes, the CS4630 enables real mode
DOS compatibility within PCI-only audio subsystems.
This device, combined with application and driver
software, provides a complete system solution for

hardware acceleration of Microsoft’s DirectSound,
DirectSound3D, Dire ctInput, and Wavetable Synth esis.
WDM drivers provide support for both Windows 98
Windows 2000



.

The CS4630 is based on the Cirrus Logic CrystalClear
Stream Processor (SP) DSP core. The SP core is
optimized for digital audio processing, and is powerful
enough to handle complex signal processing tasks such
as Sensaura 3D, 4-channel output, and hardware
wavetable synthesis. The SP core is supported by a bus
mastering PCI interface and a built-in dedicated DMA
engine with hardware scatter-gather support. These
support functio ns ensure extremely efficient transfer of
audio data streams to and from host-based memory
buffers, providing a system solution with maximum
performance and minimal host CPU load ing .



and



l Full duplex, 128 Stream DMA Interface with

Hardware Scatter/Gather Support

l PCI Power Management (D0 through

D3

), APM 1.2, and ACPI 1.0

cold

l Power Management Event (PME#)

Generation within D0-D3

cold

l Dual AC ‘97 2.1 Codec Interface
l Asynchronous Digital Serial

Interface (ZV Port)

l S/PDIF Digital Input and Output

support for PCM and AC3

PCI

Interfa c e

encoded 5.1 Channel Formats

l DirectInput



Joystick and MPU-

401 MIDI In/Out

l 3.3 V / 2.5 V Power Supply (5 V

tolerant I/O)

l PC 98 and PC 99 Compliant

Preliminary Product Information

P.O. Box 17847, Austin, Texas 78760
[phone] FAX: [phone]
http://www.cirrus.com

This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.

ORDERING INFORMATION

CS4630-CM 128-pin MQFP 14x20x2.85 mm

28-Stream

1

DMA Controller

with Hardware
Scatter/Gather

PC/PCI&

CCLS Legacy

MPU-401

MIDI Interface

Joystick
Interfa ce

Copyright  Cirrus Logic, Inc. 1999

(All Rights Reserved)

Parameter

RAM

Sample

RAM

Program

RAM

Program

ROM

Coefficient

ROM

SLIMD

SP Core

Dual Codec

AC ’97 2.1

Interface

EGPIO

S/PDIF In

S/PDIF Out

ZV Port

Async. Serial
Port Interface

NOV ‘99

DS445PP1

1

TABLE OF CONTENTS

1. CHARACTERISTICS/SPECIFICATIONS ..................................................4

ABSOLUTE MAXIMUM RATINGS ........................................................................................... 4

RECOMMENDED OPERATING CONDITIONS.......................................................................4

AC CHARACTERISTICS (PCI SIGNAL PINS ONLY) ..............................................................5

DC CHARACTERISTICS.......................................................................................................... 6

PCI INTERFACE PINS .............................................................................................................7

AC ’97 SERIAL INTERFACE TIMING ......................................................................................8

ZV PORT TIMING.....................................................................................................................9

INDEPENDENT TIMING ENVIRONMENT.............................................................................10

EEPROM TIMING CHARACTERISTICS................................................................................ 11

2. OVERVIEW ...................................................................................................12

2.1 Stream Processor DSP Core ........................................................................................... 13

2.2 Legacy Support ................................................................................................................13

3. SYSTEM ARCHITECTURES ......................................................................14

4. HOST INTERFACE ......................................................................................15

4.1 PCI bus Transactions .......................................................................................................15

4.2 Configuration Space ........................................................................................................17

4.3 Subsystem Vendor ID Fields ...........................................................................................19

4.4 Dynamic Config Register .................................................................................................19

4.5 Interrupt Signal ................................................................................................................19

5. SERIAL PORT CONFIGURATIONS .........................................................20

6. GAME PORT .................................................................................................22

6.1 MIDI Port ..........................................................................................................................22

6.2 Joystick Port .....................................................................................................................22

7. EEPROM INTERFACE ................................................................................23

8. GENERAL PURPOSE I/O PINS ..................................................................24

8.1 EGPIO .............................................................................................................................24

9. ZV PORT SERIAL INTERFACE ................................................................24

CS4630

Contacting Cirrus Logic Support

For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:

http://www.cirrus.com/corporate/contacts/

CCLS, SLIMD, and CrystalClear are trademarks of Cirrus Logic, Inc.
DirectInput and DirectX are trademarks of Microsoft Corporation.
DirectSound, DirectSo und3D, Windows 98 and Windows 2000 are regi st ered trademarks of Microsoft Corporation.
EAX is a trademark of Creative Tec hnology, Ltd.
Intel is a registered trademark of Intel.
NetMeeting is a trademark of Microsoft Corporation.
Sensaura is a trademark of Sensaura, Inc.
Sound Blaster Pro is a tradema r k of Creative Technology, Ltd.
SoundFusion is a registere d trademark of Cirrus Logic, Inc.
All other names are trademarks, registered trademarks, or service marks of their respective companies.

Preliminary product inf ormation d escribes pr oducts which a re in producti on, but for wh ich full cha racterization data is not yet available. Advance prod­uct information de scribes produ cts which are in develop ment an d subject to d evelopment c hange s. Cirrus Logi c, Inc. has mad e bes t effo rts to ensu re
that the info rmation c ontain ed in this do cument is acc urate an d r elia ble. Ho wever, the inf or mati on is subj ec t to c hange wit hou t not ice and is provid ed

“AS IS” without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this infor mation , nor for
infringements of pat ents o r othe r rights of third p arties. This d ocument is t he propert y of Cir rus Lo gic, In c. and i mplies no l ic ense un der patent s, c opy­rights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form
or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus
Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a
retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent
of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written
consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trade­marks or service marks of their respective owners which may be registered in some jurisdictions. A lis t of Cirrus Logic, Inc. trademarks and service
marks can be found at http://www.cirrus.com.

2 DS445PP1

CS4630

10. CONSUMER IEC-958 DIGITAL INTERFACE (S/PDIF) ...................... 24

11. PCI POWER MANAGEMENT .................................................................. 26

11.1 D0 State ......................................................................................................................... 26

11.2 Dl State .......................................................................................................................... 26

11.3 D2 State ......................................................................................................................... 26

11.4 D3hot State .................................................................................................................... 26

11.5 D3

11.6 CS4630 PME# Assertion ............................................................................................... 27

11.7 On Card Vaux Switching Logic ...................................................................................... 27

12. PIN DESCRIPTION ............................................................................................................... 29

12.1 PCI Interface .................................................................................................................. 30

12.2 PCI Power Management Interface Pins ........................................................................ 31

12.3 External Interface Pins .................................................................................................. 32

12.4 Clock / Miscellaneous .................................................................................................... 33

12.5 Serial Codec Interface ................................................................................................... 34

12.6 ZV Port Serial Interface .......... ...... ............................................. ....... ...... ....... ...... ....... ... 35

12.7 Consumer Digital Audio I/O (S/PDIF) ............................................................................ 35

12.8 Asynchronous Serial Interface and Enhanced General Purpose I/O ............................ 36

13. PACKAGE OUTLINE ................................................................................ 37

State ................................................................................................................... 26

cold

11.6.1 ABITCLK ON ..................................................................................................... 27

11.6.2 ABITCLK OFF ................................................................................................... 27

LIST OF FIGURES

Figure 1. AC Characteristics ...................................................................................................... 5

Figure 2. PCI Timing Measurement Conditions ......................................................................... 7

Figure 3. AC ’97 Configuration Timing Diagram ........................................................................ 8

Figure 4. ZV PORT .................................................................................................................... 9

Figure 5. Independent Timing Configuration ........................................................................... 10

Figure 6. EEPROM Timing ...................................................................................................... 11

Figure 7. CS4630 Block Diagram ............................................................................................ 12

Figure 8. AC ‘97 Codec Interface ............................................................................................ 14

Figure 9. Portable Docking Station Scenario ........................................................................... 14

Figure 10. Host Interface Base Address Registers .................................................................... 15

Figure 11. AC ‘97 Codec Connection Diagram .......................................................................... 20

Figure 12. Dual AC ‘97 Codec Connection Diagram ................................................................. 21

Figure 13. Joystick Logic ........................................................................................................... 22

Figure 14. External EEPROM Connection ................................................................................. 23

Figure 15. EEPROM Read Sequence ....................................................................................... 23

Figure 16. ZV Port Clocking Format .......................................................................................... 24

Figure 17. IEC Consumer Interface Implementation Circuit ...................................................... 25

Figure 18. Optional Fiber Optic Circuit ...................................................................................... 25

Figure 19. On-Card 3.3Vaux Switching Logic ............................................................................ 28

DS445PP1 3

CS4630

1. CHARACTERISTICS/SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS PCIGND = CGND = CRYGND = 0 V, all voltages

with respect to 0 V)

Parameter Symbol Min T yp Max Unit

Power Supplies PCIVDD

CVDD

CRYVDD

VDD5REF
Total Power Dissipation (Note 1) - - TBD W
Input Current per Pin, DC (Except supply pins) - - TBD mA
Output current per pin, DC - - TBD mA
Input voltage (Note 2) TBD - TBD V
Ambient temperature (power applied) (Note 3) -45 - 85 °C
Storage temperature -55 - 150 °C

Notes: 1. Includes all power generated by AC and/or DC output loading.

2. The power supply pins are at recommended maximum values. XTALI & XTALO are at 3.6 V maximum.

3. At ambient temperatures above 70° C, total power dissipation must be limited to less than 0.4 Watts.

-

-

-

-

-

-

-

-

4.6

TBD

4.6

5.5

V
V
V
V

WARNING: Operation beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes.

RECOMMENDED OPERATING CONDITIONS (PCIGND = CGND = CRYGND = 0 V,

all voltages with respect to 0 V)

Parameter Symbol Min Typ Max Unit

Power Supplies PCIVDD

CVDD

CRYVDD

VDD5REF
Internal DSP Frequency CS4630 - - 140 MHz
Operating Ambient Temperature T

A

Specifications are subject to change without notice.

3

2.25
3

3/4.75

02570°C

3.3

2.5

3.3

3.3/5

3.6

2.75

3.6

3.6/5.25

V
V
V
V

4 DS445PP1

CS4630

AC CHARACTERISTICS (PCI SIGNAL PINS ONLY) (T

= 0° to 70° C;

A

PCIVDD = CRYVDD = 3.3 V; CVDD = 2.5 V; VDD5REF = 5 V; PCIGND = CGND = CRYGND = 0 V;
Logic 0 = 0 V, Logic 1 = 3.3 V; Reference levels = 1.4 V; unless otherwise noted; (Note 4))

Parameter Symbol Min Max Unit

Switching Current High (Note 5)

0 < Vout < 1.4

1.4 < Vout < 2.4

I

OH

-44

-

-

mA
mA

-

3.1 < Vout < 3.3

Switching Current Low (Note 5)

Vout > 2.2

2.2 > Vout > 0.55

0.71 > Vout > 0

Low Clamp Current -5 < Vin < -1 I

I

OL

CL

95

Vout/0.023

-

-mA

Note 7

-

-

Note 8

mA
mA

Output rise slew rate 0.4 V - 2.4 V load (Note 6) slewr 1 5 V/ns
Output fall slew rate 2.4 V - 0.4 V load (Note 6) slewf 1 5 V/ns

Notes: 4. Specifications guaranteed by characterization and not production testing.

5. Refer to V/I curves in Figure 1. Specification does not apply to PCICLK and RST# signals. Switching
Current High specification does not apply to SERR#, PME#, and INTA# which are open drain outputs.

6. Cumulative edge rate across specified range. Rise slew rates do not apply to open drain outputs.

7. Equation A: I

8. Equation B: I

= 11.9 * (Vout - 5.25) * (Vout + 2.45) for 3.3 V > Vout > 3.1 V

OH

= 78.5 * Vout * (4.4 - Vout) for 0 V < Vout < 0.71 V

OL

DC
drivepoint

AC drive
point

Pull Up

-

Current(mA)

44

voltage

3.3

2.4

1.4

-2

EquationA:

I =11.9*(Vout-5.25)*(Vout+2.45)

OH

for 3.3V > Vout > 3.1V

voltage

test
po in t

0.55

176

-

Figure 1. AC Characteristics

Pull Down

3.3

AC drive
point

2.2

DC drive
point

3, 6 95 380

Equation B:

I = 78.5*Vout*(4.4-Vout)

OL

Current(mA )

for 0V < Vout < 0.71V

test
point

DS445PP1 5

CS4630

DC CHARACTERISTICS (T

= 0° to 70° C; PCIVDD = CRYVDD = 3.3 V; CVDD = 2.5 V; VDD5REF =

A

5 V; PCIGND = CGND = CRYGND = 0 V; all voltages with respect to 0 V unless otherwise noted)

Parameter Symbol Min Typ Max Unit

PCI Interface Signal Pins

High level input voltage V
Low level input voltage V
High level output voltage Iout = -2 mA V
Low level output voltage Iout = 3 mA, 6 mA (Note 9) V
High level leakage current Vin = 2.7 V (Note 10) I
Low level leakage current Vin = 0.5 V (Note 10) I

IH

IL
OH
OL
IH

IL

2-5.75V

-0.5 - 0.8 V

2.4 - - V

--0.55V

--70µA

---70µA

Non-PCI Interface Signal Pins (Except XTALO)

High level input voltage XT ALI

Other Pins

Low level input voltage XTALI

Other Pins

V

IH

V

IL

2.3
2

-0.5

-0.5

3.3

-

0

-

(Note 14)
High level output voltage Iout = -3.5 mA (Notes 11, 12) V
Low level output voltage Iout = 3.5 mA (Note 12) V
High level leakage current Vin = 5.25 V (Note 12) I
Low level leakage current Vin = 0 (Note 12) I

OH
OL
IH

IL

2.4 - - V

--0.4V

--10µA

---10µA

4.0

5.75

0.8

0.8

V
V

V
V

Parameter Min Typ Max Unit

Power Supply Pins (Outputs Unloaded)

Power Supply Current: VDD5REF
PCIVDD/CRYVDD Total( (Notes 4,13)
CVDD

-

-

-

TBD
TBD
TBD

-

TBD

mA
mA

Low Power Mode Supply Current - TBD - mA

Notes: 9. The following signals are tested to 6 mA: FRAME#, TRDY#, IRDY#, DEVSEL#, STOP#, SERR#,

PERR#, and INTA#. All other PCI interface signals are tested to 3 mA.

10. Input leakage currents include hi-Z output leakage for all bi-directional buffers with three-state outputs.

11. For open drain pins, high level output voltage is dependent on external pull-up used and number of
attached gates.

12. All inputs that do not include internal pull-ups or pull-downs, must be externally driven for proper
operation. If an input is not driven, it should be tied to power or ground, depending on the particular
function. If an I/O pin is not driven and programmed as an input, it should be tied to power or ground
through its own resistor.

13. Typical values are given as average current with typical SP task execution and data streaming. Current
values vary dramatically based on the software running on the SP.

14. Vih for the Joystick position inputs (JACX JACY JBCX JBCY) is dependent on the joystick rate.

6 DS445PP1

CS4630

PCI INTERFACE PINS (T

=0° to 70° C; PCIVDD = CRYVDD = 3.3 V; CVDD = 2.5 V; VDD5REF = 5 V;

A

PCIGND = CGND = CRYGND = 0 V; Logic 0 = 0 V, Logic 1 = 3.3 V; Timing reference levels = 1.4 V)

Parameter Symbol Min Max Unit

PCICLK cycle time t
PCICLK high time t
PCICLK low time t
PCICLK to signal valid delay - bused signals (Note 18) t
PCICLK to signal valid delay - point to point (Note 18) t

val(p+p)

Float to active delay (Note 15) t
Active to Float delay (Note 15) t
Input Set up Time to PCICLK - bused signals (Note 18) t
Input Set up Time to PCICLK - point to point (Note 18) t

su(p+p)

Input hold time for PCICLK t
Reset active time after PCICLK stable (Note 16) t

rst-clk

Reset active to output float delay (Notes 15, 16, 17) t

cyc

high

low

val

on
off
su

h

rst-off

30 - ns
11 - ns
11 - ns

211ns
212ns
1-ns

-28ns

7-ns

10, 12 - ns

0-ns

100 -

µ

s

-30ns

Notes: 15. For Active/Float measurements, the Hi-Z or “off” state is when the total current delivered is less than or

equal to the leakage current. Specification is guaranteed by design, not production tested.

16. RST# is asserted and de-asserted asynchronously with respect to PCICLK.

17. All output drivers are asynchronously floated when RST# is active.

18. REQ# and GNT# are point to point signals. All other PCI signals are considered bused signals.

PCICLK

RST#

t

rst-clk

t

off

t

on

OUTPUTS

Hi-Z

t

val

OUTPUTS

Valid

INPUTS

t

su

Valid
Input

t

h

Figure 2. PCI Timing Measurement Conditions

t

rst-off

DS445PP1 7

CS4630

AC ’97 SERIAL INTERFACE TIMING (T

V;VDD5REF = 5 V; PCIGND = CGND = CRYGND = 0 V; Logic 0 = 0 V, Logic 1 = 3.3 V;
Timing reference levels = 1.4 V; unless otherwise noted)

Parameter Symbol Min Typ Max Unit

ABITCLK/ABITCLK2 cycle time t
ABITCLK/ABITCLK2 rising to ASDOUT/ADSOUT2 valid t
ASDIN/ASDIN2 valid to ABITCLK/ABITCLK2 falling t
ASDIN/ASDIN2 hold after ABITCLK/ABITCLK2 falling t
PCICLK rising to ARST#/ARST2# valid t

ABITCLK/ABITCLK2

= 0 to 70° C; PCIVDD = CRYVDD = 3.3 V; CVDD = 2.5

A

78 81.4 - ns

-1725ns

10 - - ns

5--ns

-10- ns

t

aclk

pd5

s5
h5

pd6

aclk

ASYNC/ASYNC2

ASDOUT/ASDOUT2

ASDIN/ASDIN2

ARST#/ARST2#

PCICLK

Figure 3. AC ’97 Configuration Timing Diagram

t

pd5

t

s5

t

h5

t

pd6

8 DS445PP1

ZV PORT TIMING

Parameter Symbol Min Max Unit

ZLRCK delay after ZSCLK rising t
ZLRCK setup before ZSCLK rising t
ZSCLK low period t
ZSCLK high period t
ZSDATA setup to ZSCLK rising t
ZSDATA hold after ZSCLK rising t

slrd
slrs

sclk
sclkh
sdlrs

sdh

CS4630

2-ns
32 - ns
22 - ns
22 - ns
32 - ns

2-ns

ZLRCK

ZSCLK

ZSDATA

t

slrd

t

sdlrs

Figure 4. ZV PORT

t

slrs

t

sclkl

t

sdh

t

sclkh

DS445PP1 9

CS4630

INDEPENDENT TIMING ENVIRONMENT (T

= 0 to 70° C; PCIVDD = CRYVDD = 3.3 V; CVDD =

A

2.5V; VDD5REF = 5 V; PCIGND = CGND = CRYGND = 0 V; Logic 0 = 0V, Logic 1 = 3.3 V;
Timing reference levels = 1.4 V; XTALI = 12.288 MHz; unless otherwise noted)

Parameter Symbol Min Typ Max Units

SCLK output cycle time t
FSYNC output cycle time (@SCLK falling edge) t
SCLK falling to FSYNC transition t
LRCLK output cycle time (@ SCLK rising edge) t
SCLK rising to LRCLK transition t
SCLK falling to SDOUT/SDO2/SDO3 valid t
SDIN/SDIN2 valid to SCLK rising (SI1F2-0: 010, SI2F1-0: 00) t
SDIN/SDIN2 hold after SCLK rising

sclk

fsync

pd7

lrclk

pd8
pd9

s6

t

h6

312 326 - ns

20000 20833 - ns

-45 2 45 ns

20000 20833 - ns

-45 2 45 ns

- 2 45 ns
30 - - ns
30 - - ns

(SI1F2-0: 010, SI2F1-0: 00)
SDIN/SDIN2 valid to SCLK falling

t

s7

30 - - ns

(SI1F2-0: 011, SI2F1-0: 01)
SDIN/SDIN2 hold after SCLK falling

t

h7

30 - - ns

(SI1F2-0: 011, SI2F1-0: 01)
XTAL frequency 12.287 12.288 12.289 MHz
XTALI high time (Note 4) 35 - - ns
XTALI low time (Note 4) 35 - - ns
MCLK output frequency (Note 4) 12.287 12.288 12.289 MHz

SCLK

FSYNC

LRCLK

SDOUT/SD02/SD03

SDIN/SDIN2

SDIN/SDIN2

t

sclk

t

18

fsync

t

lrclk

15

0

0

0

t

pd7

t

pd8

t

pd9

15

t

s6

16 0

17

t

t

s7

19

18 0

h6

t

h7

0

17 16

19

Figure 5. Independent Timing Configuration

10 DS445PP1

CS4630

EEPROM TIMING CHARACTERISTICS (T

= 0 to 70 °C, PCIVDD = CRYVDD = 3.3 V; CVDD =

A

2.5V; VDD5REF = 5 V; PCIGND = CGND = CRYGND = 0 V; Logic 0 = 0 V, Logic 1 = 3.3 V;
Timing reference levels = 1.4 V; PCI clock frequency = 33 MHz; unless otherwise noted (Note 4))

Parameter Symbol Min Max Units

EECLK Low to EEDAT Data Out Valid t
Start Condition Hold Time t
EECLK Low t
EECLK High t
Start Condition Setup Time (for a Repeated Start Condition) t
EEDAT In Hold Time t
EEDAT In Setup Time t

HD:STA

LEECLK

HEECLK

SU:STA
HD:DAT
SU:DAT

EEDAT/EECLK Rise Time (Note 19) t
EEDAT/EECLK Fall Time t
Stop Condition Setup Time t

SU:STO

EEDAT Out Hold Time t

AA

R
F

DH

07.0

5.0 ­10 ­10 -

5.0 -

0-

250 - ns

-1

- 300 ns

5.0 -

0-

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

Notes: 19. Rise time on EEDAT is determined by the capacitance on the EEDAT line with all connected gates and

the required external pull-up resistor. Nominal values based on 4.7k and 22pF.

t

t

F

HEECLK

t

LEECLK

t

R

EECLK

t

HD:DAT

t

SU:DAT

EEDAT (IN)

EEDAT (OUT)

t

SU:STA

t

HD:STA

t

AA

t

SU:STO

t

DH

EEDAT (OUT)

Figure 6. EEPROM Timi n g

DS445PP1 11

CS4630

2. OVERVIEW

The CS4630 is a high performance audio accelera­tor DSP for the PCI bus. This device, combined
with application and driver software, provides a
complete system solution for cost effective acceler-

ation of Microsoft’s DirectSound,
Direct Sound3D, DirectInput, MIDI playback via
Wavetable Synthesis with reverberation and chorus
effects processing, and more. The following fea­tures can be enabled via updated device driver:

• Primary AC ‘97 Interface now 2.1 compatible

• 2nd AC ‘97 codec support

• Increased on-board memory for enhanced algo­rithm execution and greater concurrency

• 128 DMA Streams Supported

• PCI Power Management Event Support(D0­D3

• Support for wake-up event via AC 97 2.1 Link

There are three main functional blocks within the
CS4630: the Stream Processor, the PCI Interface,
and the DMA Engine. A block diagram of the
CS4630 device is shown in Figure 7. The Stream
Processor (SP) is a high speed custom Digital Sig­nal Processor (DSP) core specifically designed for

cold

)

audio signal processing. This extremely powerful
DSP core is capable of running complex algorithms
and a number of different signal processing algo­rithms simultaneously. This high concurrency capa­bility is valuable for applications such as immersive
3D games, which may play a nu mber of DirectSound
streams, a number of DirectSound3D streams, and a
MIDI music sequence simultaneously.

Separate RAM memories are included on-chip for
the SP program code (PROGRAM RAM), param­eter data (PARAMETER RAM), and audio sample
data (SAMPLE RAM). Two ROM memories store
coefficients for sample rate conversion and audio
decompression algorithms (COEFFICIENT ROM)
and common algorithm code (PROGRAM ROM).

The RAM-based DSP architecture of the CS4630
ensures maximum system flexibility. The software
function/feature mix can be adapted to meet the re­quirements of a variety of different applications,
such as DirectX games, DVD movie playback, or
DOS applications. This RAM-based architecture
also provides a means for future system upgrades,

28-Stream

1

DMA Controller

with Hardware

Scatter/Gather

PC/PCI &

PCI

Interfac e

12 DS445PP1

CCLS Legacy

MPU-401

MIDI Interface

Joystick
Interfa c e

Figure 7. CS4630 Block Diagram

Parameter

RAM

Sample

RAM

Program

RAM

Program

ROM

Coefficient

ROM

SLIMD

SP Core

Dual Codec

AC ’97 2.1

Interface

EGPIO

S/PDIF In

S/PDIF Out

ZV Port

Async. Serial

Port Interface