CIRRUS LOGIC CS4525 Service Manual

CS4525

30 W Digital Audio Amplifier with Integrated ADC

Digital Amplifier Features

 Fully Integrated Power MOSFETs  No Heatsink Required

– Programmable Power Foldback on

Thermal Warning

– High Efficiency

 > 100 dB Dynamic Range  < 0.1% THD+N @ 1 W  Configurable Outputs (10% THD+N)

– 1 x 30 W into 4 Ω, Parallel Full-Bridge – 2 x 15 W into 8 Ω, Full-Bridge – 2 x 7 W into 4 Ω, Half-Bridge + 1 x 15 W

into 8 Ω, Full-Bridge

 Built-In Protection with Error Reporting

– Overcurrent/Undervoltage/Thermal

Overload Shutdown

– Thermal Warning Reporting

 PWM Popguard  Click-Free Start-Up  Programmable Channel Delay for System

Noise & Radiated Emissions Management

for Half-Bridge Mode

ADC Features

 Stereo, 24-bit, 48 kHz Conversion  Multi-bit Architecture  95 dB Dynamic Range (A-wtd)  -86 dB THD+N  Supports 2 Vrms Input with Passive

Components

System Features

 Asynchronous 2-Channel Digital Serial Port  32 kHz to 96 kHz Input Sample Rates  Operation with On-Chip Oscillator Driver or

Applied SYS_CLK at 18.432, 24.576 or

27.000 MHz

 Integrated Sample Rate Converter (SRC)

– Eliminates Clock-Jitter Effects – Input Sample Rate Independent Operation – Simplifies System Integration

 Spread Spectrum PWM Modulation

– Reduces EMI Radiated Energy

 Low Quiescent Current

(Features continued on page 2)

System Clock Crystal Driver

I/O

Stereo

Analog In

Serial Audio

Clocks & Data

Serial Audio

Data I/O

Serial Audio

Clocks & Data

HP Detect/Mute

Reset

Interrupt

I²C or Hardware

Configuration

Crystal Oscillator Driver

Multi-bit ΔΣ ADC

Serial Audio Input Port

Serial Audio

Delay Interface

Auxiliary Serial Port

Configuration

Preliminary Product Information

http://www.cirrus.com

2.5 V to 5 V

Processing

Parametric EQ High-Pass Bass/Treble Adaptive

Loudness Compensation

2-Ch Mixer

2.1 Bass Mgr Linkwitz-Riley

Crossover De-Emphasis Volume

Error Protection

Thermal Warning Thermal Feedback

Audio

Over Current Under Voltage

PWM

Multi-bit ΔΣ

Modulator

with

Integrated

Sample Rate

Converter

Gate Drive

Gate

Drive

Gate Drive

8 V to 18 V

PGND

This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.

NOVEMBER '07

Amplifier

Out 1

Amplifier

Out 2

Amplifier

Out 3

Amplifier

Out 4

PWM Modulator

Output 1

PWM Modulator

Output 2

DS726PP2

CS4525

Software Mode System Features

 Digital Audio Processing

– 5 Programmable Parametric EQ Filters – Selectable High-Pass Filter – Bass/Treble Tone Control – Adaptive Loudness Compensation – 2-Channel Mixer – 2.1 Bass Management – 24 dB/octave Linkwitz-Riley Crossover

Filters

– De-emphasis Filter

 Selectable Serial Audio Interface Formats

– Left-Justified up to 24-bit – I²S up to 24-bit – Right-Justified 16-, 18-, 20-, 24-bits

 Digital Serial Connection to Additional CS4525

or DACs for Subwoofer

 Digital Interface to External Lip-Sync Delay  PWM Switch Rate Shifting Eliminates AM

Frequency Interference

 Digital Volume Control with Soft ramp

– +24 to -103 dB in 0.5 dB steps

 Programmable Peak Detect and Limiter  2-Channel Logic-Level PWM Output

– Programmable Channel Mapping – Can Drive an External PWM Amplifier,

Headphone Amplifier, or Line-Out Amplifier

– Integrated Headphone Detection

 Flexible Power Output Configurations  Thermal Foldback for Interruption-Free

Power-Stage Protection – Supports Internal and External Power

Stages

 Operation from On-Chip Oscillator Driver or

Applied Systems Clock

 Supports I²C

Host Control Interface

Hardware Mode System Features

 2-Channel Stereo Full-Bridge Power Outputs  Analog and Digital Inputs  I²S and Left-Justified Serial Input Formats  Thermal Foldback for Interruption-Free

Protection of Internal Power Stage

 Operation from Applied Systems Clock  External Mute Input

Common Applications

 Integrated Digital TV’s  Flat Panel TV Monitors  Computer/TV Monitors  Mini/Micro Shelf Systems  Digital Powered Speakers  Portable Docking Stations  Computer Desktop Audio

General Description

The CS4525 is a stereo analog or digital input PWM high efficiency Class D amplifier audio system with an integrated stereo analog-to-digital (A/D) converter. The stereo power amplifiers can deliver up to 15 W per channel into 8 Ω speakers from a small space-saving 48-pin QFN package. The PWM amplifier can achieve greater than 85% efficiency. The package is thermally enhanced for optimal heat dis sipation which eliminat es the need for a heatsink.

The power stage outputs can be con fig ur ed as t w o fu llbridge channels for 2 x 15 W operation, two half-bridge channels and one full-bridge channel for 2 x 7 W + 1 x 15 W operation, or one parallel full-bridge channel for 1 x 30 W operation. The CS4525 integrates on-chip over-current, under-voltage, and over-temperature protection and error reporting as well as a thermal warning indicator and programmable foldback of the output power to allow cooling.

The main digital serial port on the CS4525 can support asynchronous operation with the integrated on-chip sample rate converter (SRC) which eases system integration. The SRC allows for a fixed PWM switching frequency regardless of incoming sample rate as well as optimal clocking for the A/D modulators.

An on-chip oscillator driver eliminates the need for an external crystal oscillator circuit, reducing overall design cost and conserving circuit board space. The CS4525 automatically uses the on-chip oscillator driver in the absence of an applied master clock.

The CS4525 is available in a 48-pin QFN package in Commercial grade (-10° to +70° C). The CRD4525-Q1 4-layer, 1 oz. copper and CRD4525-D1 2-layer, 1 oz. copper customer reference designs are also available.

Please refer to “Ordering Information” on page 97 for complete ordering information.

2 DS726PP2

TABLE OF CONTENTS

1. PIN DESCRIPTIONS - SOFTWARE MODE .......................................................................................... 8

2. PIN DESCRIPTIONS - HARDWARE MODE ....................................................................................... 10

2.1 Digital I/O Pin Characteristics ........ ... ... ... .... ... ... ... .......................................... .... ... ... ... ... ................ 12

3. TYPICAL CONNECTION DIAGRAMS .................................................................................................13

4. TYPICAL SYSTEM CONFIGURATION DIAGRAMS ........................................................................... 15

5. CHARACTERISTICS AND SPECIFICATIONS .................................................................................... 18

6. APPLICATIONS ................................................................................................................................... 26

6.1 Software Mode .................................. ... ... .... ... ... ... .... .......................................... ... ... ... ................... 26

6.1.1 System Clocking ................................................................................................................... 26

6.1.1.1 SYS_CLK Input Clock Mode .................................................................................... 26

6.1.1.2 Crystal Oscillator Mode ............................................................................................ 27

6.1.2 Power-Up and Power-Down .................................................................................................28

6.1.2.1 Recommended Power-Up Sequence ....................................................................... 28

6.1.2.2 Recommended Power-Down Sequence .................................................................. 28

6.1.3 Input Source Selection .......................................................................................................... 29

6.1.4 Digital Sound Processing ...................................................................................................... 29

6.1.4.1 Pre-Scaler ................................................................................................................. 30

6.1.4.2 Digital Signal Processing High-Pass Filter ............................................................... 30

6.1.4.3 Channel Mixer ..........................................................................................................30

6.1.4.4 De-Emphasis ............................................................................................................31

6.1.4.5 Tone Control ............................................................................................................. 31

6.1.4.6 Parametric EQ ..........................................................................................................33

6.1.4.7 Adaptive Loudness Compensation .............................. ............................................. 34

6.1.4.8 Bass Management .................................................................................................... 35

6.1.4.9 Volume and Muting Control ...................................................................................... 36

6.1.4.10 Peak Signal Limiter .............. ... ... ... .... ... ... ... .... ... ... ... .......................................... ... ... 37

6.1.4.11 Thermal Limiter ................ .... ... ... .......................................... ... .... ... ... ... ... .... ... ... ... ...39

6.1.4.12 Thermal Foldback ......................... .... ... ... ... .... ... ... ... .......................................... ... ... 40

6.1.4.13 2-Way Crossover & Sensitivity Control .......... ......................... .......................... ...... 41

6.1.5 Auxiliary Serial Output .......................................................................................................... 43

6.1.6 Serial Audio Delay & Warning Input Port .............................................................................. 44

6.1.6.1 Serial Audio Delay Interface ..................................................................................... 44

6.1.6.2 External Warning Input Port ..................................................................................... 44

6.1.7 Powered PWM Outputs ........................................................................................................ 45

6.1.7.1 Output Channel Configurations ................................................................................ 45

6.1.7.2 PWM Popguard Transient Control ............................................................................ 45

6.1.8 Logic-Level PWM Outputs .................................................................................................... 46

6.1.8.1 Recommended PWM_SIG Power-Up Sequence for an External PWM Amplifier .... 47

6.1.8.2 Recommended PWM_SIG Power-Down Sequence for an External PWM Amplifier 47

6.1.8.3 Recommended PWM_SIG Power-Up Sequence for Headphone & Line-Out .......... 48

6.1.8.4 Recommended PWM_SIG Power-Down Sequence for Headphone & Line-Out ..... 48

6.1.8.5 PWM_SIG Logic-Level Output Configurations ......................................................... 49

6.1.9 PWM Modulator Configuration .................... .... ... ... ............................................. ...................50

6.1.9.1 PWM Channel Delay ................................................................................................ 50

6.1.9.2 PWM AM Frequency Shift ........................................................................................ 51

6.1.10 Headphone Detection & Hardware Mute Input ................................................................... 51

6.1.11 Interrupt Reporting .............................................................................................................. 53

6.1.12 Automatic Power Stage Shut-Down ................................................................................... 53

6.2 Hardware Mode .......................... ... ... ... ... .... .......................................... ... ... ... .... ... ... ...................... 54

6.2.1 System Clocking ................................................................................................................... 54

6.2.2 Power-Up and Power-Down .................................................................................................54

6.2.2.1 Recommended Power-Up Sequence ....................................................................... 54

CS4525

DS726PP2 3

CS4525

6.2.2.2 Recommended Power-Down Sequence ............ ... ... ... .... ... ... ... .... ... ... ... ... ................ 55

6.2.3 Input Source Selection .......................... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ............................ 55

6.2.4 PWM Channel Delay ............................................................................................................ 55

6.2.5 Digital Signal Flow ................................................................................................................ 56

6.2.5.1 High-Pass Filter ........................................................................................................ 56

6.2.5.2 Mute Control ............................................................................................................. 56

6.2.5.3 Warning and Error Reporting .................................................................................... 56

6.2.6 Thermal Foldback ................................................................................................................. 57

6.2.7 Automatic Power Stage Shut-Down ..................................................................................... 58

6.3 PWM Modulators and Sample Rate Converters ............................................................................ 58

6.4 Output Filters ................................................................................................................................. 59

6.4.1 Half-Bridge Output Filter ....................................................................................................... 59

6.4.2 Full-Bridge Output Filter (Stereo or Parallel) ........................................................................ 60

6.5 Analog Inputs ................................................................................................................................. 61

6.6 Serial Audio Interfaces ................................................................................................................... 62

6.6.1 I²S Data Format .................................................................................................................... 62

6.6.2 Left-Justified Data Format .................................................................................................... 62

6.6.3 Right-Justified Data Format .................................................................................................. 63

6.7 Integrated VD Regulator ................................................................................................................ 63

6.8 I²C Control Port Description and Timing ........................................................................................ 64

7. PCB LAYOUT CONSIDERATIONS ..................................................................................................... 65

7.1 Power Supply, Grounding .............................................................................................................. 65

7.2 QFN Thermal Pad .......................................................................................................................... 65

8. REGISTER QUICK REFERENCE ........................................................................................................ 66

9. REGISTER DESCRIPTIONS ................................................................................................................ 69

9.1 Clock Configuration (Address 01h) ................................................................................................ 69

9.1.1 SYS_CLK Output Enable (EnSysClk) ................................................................................... 69

9.1.2 SYS_CLK Output Divider (DivSysClk) .................................................................................. 69

9.1.3 Clock Frequency (ClkFreq[1:0]) ............................................................................................ 69

9.1.4 HP_Detect/Mute Pin Active Logic Level (HP/MutePol) ...................... ................... ................ 70

9.1.5 HP_Detect/Mute Pin Mode (HP/Mute) .................................................................................. 70

9.1.6 Modulator Phase Shifting (PhaseShift) ................................. ............................................. ... 70

9.1.7 AM Frequency Shifting (FreqShift) ....................................................................................... 70

9.2 Input Configuration (Address 02h) ................................................................................................. 71

9.2.1 Input Source Selection (ADC/SP) ................................... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ......... 71

9.2.2 ADC High-Pass Filter Enable (EnAnHPF) ................................... ... ... ... .... ... ... ... ... .... ... ... ... ... 71

9.2.3 Serial Port Sample Rate (SPRate[1:0]) - Read Only ................................ ... ... ... ... .... ... ... ... ... 71

9.2.4 Input Serial Port Digital Interface Format (DIF [2:0]) ............................................................ 71

9.3 AUX Port Configuration (Address 03h) .......................................................................................... 72

9.3.1 Enable Aux Serial Port (EnAuxPort) ..................................................................................... 72

9.3.2 Delay & Warning Port Configuration (DlyPortCfg[1:0]) ......................................................... 72

9.3.3 Aux/Delay Serial Port Digital Interface Format (AuxI²S/LJ) ............... ... .... ... ... ... ....... ... ... ... ... 72

9.3.4 Aux Serial Port Right Channel Data Select (RChDSel[1:0]) ................................................. 72

9.3.5 Aux Serial Port Left Channel Data Select (LChDSel[1:0]) .................................................... 73

9.4 Output Configuration (Address 04h) ............................................................................................. 73

9.4.1 Output Configuration (OutputCfg[1:0]) .................................................................................. 7

9.4.2 PWM Signals Output Data Select (PWMDSel[1:0]) ........................ ...................................... 73

9.4.3 Channel Delay Settings (OutputDly[3:0]) .............................................................................. 73

9.5 Foldback and Ramp Configuration (Address 05h) ......................................................................... 74

9.5.1 Select VP Level (SelectVP) .................................................................................................. 74

9.5.2 Enable Thermal Foldback (EnTherm) ................................................................................... 74

9.5.3 Lock Foldback Adjust (LockAdj) ...........................................................................................74

9.5.4 Foldback Attack Delay (AttackDly[1:0]) ................................................................................ 75

9.5.5 Enable Foldback Floor (EnFloor) .......................... ............................................. ...................75

4 DS726PP2

CS4525

9.5.6 Ramp Speed (RmpSpd[1:0]) ................................................................................................ 75

9.6 Mixer / Pre-Scale Configuration (Address 06h) ............................................................................. 75

9.6.1 Pre-Scale Attenuation (PreScale[2:0]) .................................................................................. 75

9.6.2 Right Channel Mixer (RChMix[1:0]) ...................................................................................... 76

9.6.3 Left Channel Mixer (LChMix[1:0]) .........................................................................................76

9.7 Tone Configuration (Address 07h) ................................. ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ......... 76

9.7.1 De-Emphasis Control (DeEmph) .......................................................................................... 76

9.7.2 Adaptive Loudness Compensation Control (Loudness) ....................................................... 76

9.7.3 Digital Signal Processing High-Pass Filter (EnDigHPF) ....................................................... 77

9.7.4 Treble Corner Frequency (TrebFc[1:0]) ....................... ................................................ ......... 77

9.7.5 Bass Corner Frequency (BassFc[1:0]) ................................................................................. 77

9.7.6 Tone Control Enable (EnToneCtrl) ....................................................................................... 77

9.8 Tone Control (Address 08h) ........................ ... ... ... .... ... ... ... .......................................... ... .... ............ 78

9.8.1 Treble Gain Level (Treb[3:0]) ................................................................................................78

9.8.2 Bass Gain Level (Bass[3:0]) ................................................................................................. 78

9.9 2.1 Bass Manager/Parametric EQ Control (Address 09h) ............................................................. 78

9.9.1 Freeze Controls (Freeze) ................................ ............. ................ ................ ................ ......... 78

9.9.2 Hi-Z PWM_SIG Outputs (HiZPSig) ....................................................................................... 79

9.9.3 Bass Cross-Over Frequency (BassMgr[2:0]) ........................................................................ 79

9.9.4 Enable Channel B Parametric EQ (EnChBPEq) ................................................................... 79

9.9.5 Enable Channel A Parametric EQ (EnChAPEq) ................................................................... 79

9.10 Volume and 2-Way Cross-Over Configuration (Address 55h) .................................. ... .... ... ... ... ... 80

9.10.1 Soft Ramp and Zero Cross Control (SZCMode[1:0]) .......................................................... 80

9.10.2 Enable 50% Duty Cycle for Mute Condition (Mute50/50) ................................................... 80

9.10.3 Auto-Mute (AutoMute) ........................................................................................................ 80

9.10.4 Enable 2-Way Crossover (En2Way) ...................... .... ... ... ... .......................................... ... ... 81

9.10.5 2-Way Cross-Over Frequency (2WayFreq[2:0]) ................................................................. 81

9.11 Channel A & B: 2-Way Sensitivity Control (Address 56h) ............................................................ 81

9.11.1 Channel A and Channel B Low-Pass Sensitivity Adjust (LowPass[3:0]) ............................ 81

9.11.2 Channel A and Channel B High-Pass Sensitivity Adjust (HighPass[3:0]) ........................... 82

9.12 Master Volume Control (Address 57h) ............................... ... ... ... ... .... ......................................... 82

9.12.1 Master Volume Control (MVol[7:0]) .................................................................................... 82

9.13 Channel A and B Volume Control (Address 58h & 59h) ........................... ... .... ... ... ... ... .... ............ 83

9.13.1 Channel X Volume Control (ChXVol[7:0]) ........................................................................... 83

9.14 Sub Channel Volume Control (Address 5Ah) ........ ... ... ... .... ... ... ... .......................................... ... ... 83

9.14.1 Sub Channel Volume Control (SubVol[7:0]) ....................................................................... 83

9.15 Mute/Invert Control (Address 5Bh) .............................................................................................. 84

9.15.1 ADC Invert Signal Polarity (InvADC) .................................................................................. 84

9.15.2 Invert Channel PWM Signal Polarity (InvChX) ................................................................... 84

9.15.3 Invert Sub PWM Signal Polarity (InvSub) ........................................................................... 84

9.15.4 ADC Channel Mute (MuteADC) .......................................................................................... 84

9.15.5 Independent Channel A & B Mute (MuteChX) .................................................................... 84

9.15.6 Sub Channel Mute (MuteSub) ............................................................................................ 85

9.16 Limiter Configuration 1 (Address 5Ch) ......................................................................................... 85

9.16.1 Maximum Threshold (Max[2:0]) .......................................................................................... 85

9.16.2 Minimum Threshold (Min[2:0]) ............................................ ... .............................................85

9.16.3 Peak Signal Limit All Channels (LimitAll) ............................................................................ 86

9.16.4 Peak Detect and Limiter Enable (EnLimiter) ....................... .................... ................... ......... 86

9.17 Limiter Configuration 2 (Address 5Dh) ......................................................................................... 87

9.17.1 Limiter Release Rate (RRate[5:0]) ...................................... ................ ................ ................ 87

9.18 Limiter Configuration 3 (Address 5Eh) ......................................................................................... 87

9.18.1 Enable Thermal Limiter (EnThLim) ..................................................................................... 87

9.18.2 Limiter Attack Rate (ARate[5:0]) ......................................................................................... 87

9.19 Power Control (Address 5Fh) ......................................................... .... ... ...................................... 88

DS726PP2 5

CS4525

9.19.1 Automatic Power Stage Retry (AutoRetry) ......................................................................... 88

9.19.2 Enable Over-Current Protection (EnOCProt) ...................................................................... 88

9.19.3 Select VD Level (SelectVD) ................................................................................................ 88

9.19.4 Power Down ADC (PDnADC) ............................................................................................. 88

9.19.5 Power Down PWM Power Output X (PDnOutX) ........................ ................ ................ ......... 88

9.19.6 Power Down (PDnAll) ......................................................................................................... 89

9.20 Interrupt (Address 60h) ............................ ................................................................................... 89

9.20.1 SRC Lock State Transition Interrupt (SRCLock) ................................................................ 89

9.20.2 ADC Overflow Interrupt (ADCOvfl) ..................................................................................... 90

9.20.3 Channel Overflow Interrupt (ChOvfl) .................................................................................. 90

9.20.4 Amplifier Error Interrupt Bit (AmpErr) ..................................................................................90

9.20.5 Mask for SRC State (SRCLockM) ...................................................................................... 91

9.20.6 Mask for ADC Overflow (ADCOvflM) .................................................................................. 91

9.20.7 Mask for Channel X and Sub Overflow (ChOvflM) ............................................................. 91

9.20.8 Mask for Amplifier Error (AmpErrM) ................................................................................... 92

9.21 Interrupt Status (Address 61h) - Read Only ................................................................................. 92

9.21.1 SRC State Transition (SRCLockSt) .................................................................................... 92

9.21.2 ADC Overflow (ADCOvflSt) ................................................................................................92

9.21.3 Sub Overflow (SubOvflSt) ................................................................................................... 92

9.21.4 Channel X Overflow (ChXOvflSt) ........................................................................................ 93

9.21.5 Ramp-Up Cycle Complete (RampDone) ............................................................................ 93

9.22 Amplifier Error Status (Address 62h) - Read Only ....................................................................... 93

9.22.1 Over-Current Detected On Channel X (OverCurrX) ........... ... .... ... ... ... .... ... ... ... ... .... ... ... ... ... 93

9.22.2 External Amplifier State (ExtAmpSt) ................................................................................... 93

9.22.3 Under Voltage / Thermal Error State (UVTE[1:0]) .............................................................. 94

9.23 Device I.D. and Revision (Address 63h) - Read Only .................................................................. 94

9.23.1 Device Identification (DeviceID[4:0]) ...................................................................................94

9.23.2 Device Revision (RevID[2:0]) .............................................................................................. 94

10. PARAMETER DEFINITIONS .............................................................................................................. 95

11. REFERENCES .................................................................................................................................... 95

12. PACKAGE DIMENSIONS .................................................................................................................. 96

13. THERMAL CHARACTERISTICS ....................................................................................................... 97

13.1 Thermal Flag ... ... ... ... .......................................... .... ... ... ... .... ... ... ... ... .... ......................................... 97

14. ORDERING INFORMATION .............................................................................................................. 97

15. REVISION HISTORY .......................................................................................................................... 98

LIST OF FIGURES

Figure 1.Typical Connection Diagram - Software Mode ........................................................................... 13

Figure 2.Typical Connection Diagram - Hardware Mode .................... ...................................................... 14

Figure 3.Typical System Configuration 1 .................................................................................................. 15

Figure 4.Typical System Configuration 2 .................................................................................................. 15

Figure 5.Typical System Configuration 3 .................................................................................................. 16

Figure 6.Typical System Configuration 4 .................................................................................................. 17

Figure 7.Serial Audio Input Port Timing ................. ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... ................ 21

Figure 8.AUX Serial Port Interface Master Mode Timing .......................................................... ................22

Figure 9.SYS_CLK Timing from Reset ..................................................................................................... 23

Figure 10.PWM_SIGX Timing ................................... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ............................ 23

Figure 11.Control Port Timing - I²C ........................................................................................................... 24

Figure 12.Typical SYS_CLK Input Clocking Configuration .......................................................................26

Figure 13.Typical Crystal Oscillator Clocking Configuration ..................................................................... 27

Figure 14.Digital Signal Flow .................................................................................................................... 29

Figure 15.De-Emphasis Filter ............................ .... ... ... ... .... ... ... ... .... ... ... ................................................... 31

Figure 16.Bi-Quad Filter Architecture .............................. .......... .......... ...... .......... .......... ......... ................... 33

6 DS726PP2

Figure 17.Peak Signal Detection & Limiting .............................................................................................. 37

Figure 18.Foldback Process ..................................................................................................................... 40

Figure 19.Popguard Connection Diagram ................................................................................................. 46

Figure 20.2-Channel Full-Bridge PWM Output Delay ...............................................................................50

Figure 21.3-Channel PWM Output Delay .................................................................................................. 50

Figure 22.Typical SYS_CLK Input Clocking Configuration .... ................ ................................................... 54

Figure 23.Hardware Mode PWM Output Delay ......................................................................................... 55

Figure 24.Hardware Mode Digital Signal Flow .......................................................................................... 56

Figure 25.Foldback Process ..................................................................................................................... 57

Figure 26.Output Filter - Half-Bridge ......................................................................................................... 59

Figure 27.Output Filter - Full-Bridge .......................................................................................................... 60

Figure 28.Recommended Unity Gain Input Filter ...................................................................................... 61

Figure 29.Recommended 2 V

Figure 30.I²S Serial Audio Formats ........................................................................................................... 62

Figure 31.Left-Justified Serial Audio Formats ........................................................................................... 62

Figure 32.Right-Justified Serial Audio Formats ................... ... ... ... .... ... ... ... ................................................ 63

Figure 33.Control Port Timing, I²C Write ................................................................................................... 64

Figure 34.Control Port Timing, I²C Read ................................................................................................... 64

LIST OF TABLES

Table 1. I/O Power Rails ........................................................................................................................... 12

Table 2. Bass Shelving Filter Corner Frequencies ....................... .......................................... ... .... ... ......... 31

Table 3. Treble Shelving Filter Corner Frequencies ................................................................................. 32

Table 4. Bass Management Cross-Over Frequencies ..................................... ... ... ... .... ... ... ... ... .... ............ 35

Table 5. 2-Way Cross-Over Frequencies .................................................................................................. 41

Table 6. Auxiliary Serial Port Data Output .......................... ... ... ... .... ... ...................................................... 43

Table 7. Nominal Switching Frequencies of the Auxiliary Serial Output ................................................... 43

Table 8. PWM Power Output Configurations ............................................................................................ 45

Table 9. Typical Ramp Times for Various VP Voltages ............................................................................46

Table 10. PWM Logic-Level Output Configurations .................................................................................. 49

Table 11. PWM Output Switching Rates and Quantization Levels ..................................... ... ... .... ... ... ... ... 51

Table 12. Output of PWM_SIG Outputs .................................................................................................... 52

Table 13. SYS_CLOCK Frequency Selection ........................................................................................... 54

Table 14. Input Source Selection .................................... .......................................................................... 55

Table 15. Serial Audio Interface Format Selection .................................................................................... 55

Table 16. Thermal Foldback Enable Selection ...................... ... ... .... ... ... ... ... .... ......................................... 57

Table 17. PWM Output Switching Rates and Quantization Levels ..................................... ... ... .... ... ... ... ... 58

Table 18. Low-Pass Filter Components - Half-Bridge ............................................................................... 59

Table 19. DC-Blocking Capacitors Values - Half-Bridge .............................. ............................................. 59

Table 20. Low-Pass Filter Components - Full-Bridge ............................................................................... 60

Table 21. Power Supply Configuration and Settings ................................................................................. 63

CS4525

Input Filter ........................................................................................... 61

RMS

DS726PP2 7

1. PIN DESCRIPTIONS - SOFTWARE MODE

XTI

XTO

SYS_CLK

AUX_LRCK/AD0

AUX_SCLK

AUX_SDOUT

DLY_SDIN/EX_TWR

4748 46

44 43 42 41

DLY_SDOUT

PWM_SIG1

PWM_SIG2

40 39 38 37

PGND

CS4525

INT

SCL

SDA

LRCK SCLK

SDIN

HP_DETECT/MUTE

RST

LVD

DGND

VD_REG

Thermal Pad

1413 15

AGND

VA_REG

Top-Down (Through Package) View

48-Pin QFN Package

17 18 19 20

FILT+

AFILTL

AINL

AFILTR

21 22 23 24

AINR

OCREF

PGND

VP OUT1 PGND PGND

OUT2 VP VP OUT3 PGND PGND OUT4 VP

RAMP_CAP

Pin Name Pin # Pin Description

INT 1Interrupt (Output) - Indicates an interrupt condition has occurred. SCL 2 Serial Control Port Clock (Input) - Serial clock for the I²C control port. SDA 3 Serial Control Data (Input/Output) - Bi-directional data I/O for the I²C control port.

LRCK 4

Left Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial

audio data line. SCLK 5 Serial Clock (Input) - Serial bit clock for the serial audio interface. SDIN 6 Serial Audio Data Input (Input) - Input for two’s complement serial audio data. HP_DETECT/

MUTE

RST

Headphone Detect / Mute (Input) - Headphone detection or mute input signal as configured via the

I²C control port.

Reset (Input) - The device enters a low power mode and all internal registers are reset to their

default settings when this pin is driven low.

8 DS726PP2

CS4525

VD Voltage Level Indicator (Input) - Identifies the voltage level attached to VD. When applying

LVD 9

DGND 10 Digital Ground (Input) - Ground for the internal logic and digital I/O. VD_REG 11 Core Logic Power (Output) - Internally generated low voltage power supply for digital logic. VD 12 Power (Input) - Positive power supply for the internal regulators and digital I/O. VA_REG 13 Analog Power (Output) - Internally generated positive power for the analog section and I/O. AGND 14 Analog Ground (Input) - Ground reference for the internal analog section and I/O.

FILT+ 15 VQ 16 Common Mode Voltage (Output) - Filter connection for internal common mode voltage.

AFILTL AFILTR

AINL AINR

OCREF 21 Over Current Reference Setting (Input) - Sets the reference for over current detection.

22,23

PGND

RAMP_CAP 24

VP OUT4

OUT3 OUT2 OUT1

PWM_SIG2 PWM_SIG1

DL Y_SDOUT 41 Delay Serial Audio Data Out (Output) - Output for two’s complement serial audio data. DL Y_SDIN/

EX_TWR

AUX_SDOUT 43 AUX_SCLK 44 Auxiliary Port Serial Clock (Output) - Serial clock for the auxiliary port serial interface. AUX_LRCK/

AD0

SYS_CLK 46 XTO 47 Crystal Oscillator Output (Output) - Crystal oscillator driver output.

XTI 48 Crystal Oscillator Input (Input) - Crystal oscillator driver input. Thermal Pad -

27,28 33,34 37,38

25,30,

31,36

5.0 V to VD, LVD must be connected to VD. When applying 2.5 V or 3.3 V to VD, L VD must be DGND.

Positive Voltage Reference (Output) - Positive reference voltage for the internal ADC sampling circuits.

Antialias Filter Connection (Output) - Antialias filter connection for ADC inputs.

18 1920Analog Input (Input) - The full-scale input level is specified in the ADC Analog Characteristics

specification table.

Power Ground (Input) - Ground for the individual output power half-bridge devices.

Output Ramp Capacitor (Input) - Used by the PWM Popguard Transient Control to suppress the

initial pop in half-bridge-configured outputs. High Voltage Power (Input) - High voltage power supply for the individual half-bridge devices.

26 29

PWM Output (Output) - Amplified PWM power outputs.

32 35

Logic Level PWM Output (Output) - Logic Level PWM switching signals.

Delay Serial Audio Data Input (Input) - Input for two’s complement serial audio data.

External Thermal Warning (Input) - Input for an external thermal warning signal. Configurable via the I²C control port.

Auxiliary Port Serial Audio Data Out (Output) - Output for two’s complement auxiliary port serial data.

Auxiliary Port Left Right Clock (Output) - Determines which channel, Left or Right, is currently

active on the serial audio data line.

AD0 (Input) - Sets the LSB of the I²C device address. Sensed on the release of RST System Clock (Input/Output) -Clock source for the internal logic, processing, and modulators. This

pin should be connected to through a 10kΩ to ground when unused.

Thermal Pad - Thermal relief pad for optimized heat dissipation. See “QFN Thermal Pad” on

page 65 for more information.

DS726PP2 9

2. PIN DESCRIPTIONS - HARDWARE MODE

EN_TFB

ERROC

TSTI

4748 46

TSTO

SYS_CLK

I2S/LJ

44 43 42 41

ERRUVTE

TWR

TSTO

40 39 38 37

PGND

CS4525

CLK_FREQ0 CLK_FREQ1

ADC/SP

LRCK SCLK

SDIN

MUTE

RST

LVD

DGND

VD_REG

Thermal Pad

1413 15

AGND

VA_REG

Top-Down (Through Package) View

48-Pin QFN Package

17 18 19 20

FILT+

AFILTL

AINL

AFILTR

21 22 23 24

AINR

OCREF

PGND

VP OUT1 PGND PGND

OUT2 VP VP OUT3 PGND PGND OUT4 VP

RAMP_CAP

Pin Name Pin # Pin Description

CLK_FREQ0 CLK_FREQ1

ADC/SP 3

LRCK 4 SCLK 5 Serial Clock (Input) - Serial bit clock for the serial audio interface.

SDIN 6 Serial Audio Data Input (Input) - Input for two’s complement serial audio data.

MUTE

RST

12Clock Frequency (Input) - Determines the frequency of the clock expected to be driven into the

SYS_CLK pin. ADC/Serial Port (Input) - Selects between the Analog to Digital Converter and the Serial Port for

audio input. Selects the ADC when high or the serial port when low. Left Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial

audio data line.

Mute (Input) - The PWM outputs will output silence as a 50% duty cycle signa l when this pin is driven low.

Reset (Input) - The device enters a low power mode and all internal registers are reset to their default settings when this pin is driven low.

10 DS726PP2

CS4525

VD Voltage Level Indicator (Input) - Identifies the voltage level attached to VD. When applying

LVD 9

DGND 10 Digital Ground (Input) - Ground for the internal logic and I/O. VD_REG 11 Core Logic Power (Output) - Internally generated low voltage power supply for digital logic. VD 12 Digital Power (Input) - Positive power supply for the internal regulators and digital I/O. VA_REG 13 Analog Power (Output) - Internally generated positive power for the analog section and I/O. AGND 14 Analog Ground (Input) - Ground reference for the internal analog section and I/O.

FILT+ 15 VQ 16 Common Mode Voltage (Output) - Filter connection for internal common mode voltage.

AFILTL AFILTR

AINL AINR

OCREF 21 Over Current Reference Setting (Input) - Sets the reference for over current detection.

22,23

PGND

RAMP_CAP 24 Output Ramp Capacitor (Input) - This pin should be connected directly to VP in hardware mode. VP OUT4

OUT3 OUT2 OUT1

TSTO

41 Thermal Warning Output (Output) - Thermal warning output.

TWR ERRUVTE 42 ERROC

EN_TFB 44 Enable Thermal Feedback (Input) - Enables the thermal foldback feature when high. I2S/LJ SYS_CLK 46 System Clock (Input/Output) -Clock source for the delta-sigma modulators. TSTO 47

TSTI 48

Thermal Pad -

43 Overcurrent Error Output (Output) - Overcurrent error flag.

27,28 33,34 37,38

25,30,

31,36

5.0 V to VD, LVD must be connected to VD. When applying 2.5 V or 3.3 V to VD, LVD must be connected to DGND.

Positive Voltage Reference (Output) - Positive reference voltage for the internal ADC sampling circuits.

Antialias Filter Connection (Output) - Antialias filter connection for ADC inputs.

18 1920Analog Input (Input) - The full-scale input level is specified in the ADC Analog Characteristics

specification table.

Power Ground (Input) - Ground for the individual output power half-bridge devices.

High Voltage Power (Input) - High voltage power supply for the individual half-bridge devices.

26 29

PWM Output (Output) - Amplified PWM power outputs.

32 35

3940Test Output (Output) - These pins are outputs used for the Logic Level PWM switching signals

available only in software mode. They must be left unconnected for hardware mode operation.

Thermal and Undervoltage Error Outp ut (Output) - Error flag for thermal shutdown and under- voltage.

I²S/Left Justified (Input) - Selects between I²S and Left-Justified data format for the serial input

port. Selects I²S when high and LJ when low.

Test Output (Output) - This pin is an output used for the crystal oscillator driver available only in software mode. It must be left unconnected for normal hardware mode operation.

Test Input (Input) - This pin is an input used for the crystal oscillator driver available only in soft- ware mode. It must be tied to digital ground for normal hardware mode operation.

Thermal Pad - Thermal relief pad for optimized heat dissipation. See “QFN Thermal Pad” on

page 65 for more information.

DS726PP2 11

CS4525

2.1 Digital I/O Pin Characteristics

The logic level for each input is set by its corresponding power su pply and should not exceed the maximum ratings.

Power

Supply

Number

Pin Name I/O Driver Receiver

Software Mode

VD 1 INT Output 2.5 V-5.0 V, Open Drain

2 SCL Input - 2.5 V-5.0 V, with Hysteresis 3 SDA Input/Output 2.5 V-5.0 V, Open Drain 2.5 V-5.0 V, with Hysteresis 7HP_DETECT

MUTE 41 DLY_SDOUT Output 2.5 V-5.0V, CMOS 42 DLY_SDIN

EX_TWR 43 AUX_SDOUT Output 2.5 V-5.0V, CMOS 44 AUX_SCLK Output 2.5 V-5.0 V, CMOS 45 AUX_LRCK Output 2.5 V-5.0 V, CMOS -

VD_REG 39 PWM_SIG2 Output 2.5 V, CMOS -

40 PWM_SIG1 Output 2.5 V, CMOS -

Input Input

2.5 V-5.0 V

Hardware Mode

VD 1 SEL_OSC0 Input - 2.5 V-5.0 V

2 SEL_OSC1 Input - 2.5 V-5.0 V 3 ADC/SP

7 MUTE Input - 2.5 V-5.0 V 41 TWR 42 ERRUVTE 43 ERROC 44 EN_TFB Input - 2.5 V-5.0 V 45 I²S/LJ

Input - 2.5 V-5.0 V

Output 2.5 V-5.0 V, Open Drain Output 2.5 V-5.0 V, Open Drain Output 2.5 V-5.0 V, Open Drain -

Input - 2.5 V-5.0 V

All Modes

VD 4 LRCK Input - 2.5 V-5.0 V

5 SCLK Input - 2.5 V-5.0 V

6 SDIN Input - 2.5 V-5.0 V

8 RST Input - 2.5 V-5.0 V

9 LVD Input - 2.5 V-5.0 V 46 SYS_CLK Input/Output 2.5 V-5.0 V, CMOS 2.5 V-5.0 V

VP 26 OUT4 Output 8.0 V-18.0 V Power MOSFET -

29 OUT3 Output 8.0 V-18.0 V Power MOSFET 32 OUT2 Output 8.0 V-18.0 V Power MOSFET 35 OUT1 Output 8.0 V-18.0 V Power MOSFET -

Table 1. I/O Power Rails

12 DS726PP2

3. TYPICAL CONNECTION DIAGRAMS

CS4525

+3.3 or +5 V

Analog

Audio

Inputs

Analog

Audio

Switch

Analog

Monitor

Output

Crystal

24.576 MHz

MPEG

Audio

Processor

- or -

HDMI

Receiver

Lip-Synch

Delay

NJU26902

+2.5V

0.1 µF

10 µF

22 kΩ

Micro-

Controller

*Note: Resistors are required for I²C control port

operation.

†

Note: On release of RST, AD0 is read as input on the

AUX_LRCK line.

0.1 µF10 µF

AINL

AINR

XTI

XTO

SYS_CLK SCLK5

LRCK

SDIN

HP_DETECT/MUTE

22 kΩ

AUX_SDOUT

AUX_LRCK/AD0

AUX_SCLK

DLY_SDOUT

†

DLY_SDIN

22 kΩ

VD_REG

2 kΩ

SCL

SDA

INT

RST

10 2322 28 33 34 37 3827

470 µF 0.1 µF 0.1 µF 0.1 µF 0.1 µF 470 µF

313025

RAMP_CAP

CS4525

PWM_SIG1

PWM_SIG2

VA_REG

OUT1

OUT2

OUT3

OUT4

LVD

OCREF

FILT+

AGND

AFILTA AFILTB

15 13

17 18 16

Output

Filter

Output

Filter

16.2 kΩ

0.1 µF 10 µF

150 pF 150 pF

Line

Output

- or -

Headphone

Output

VD or GND

10 µF

1 µF

+8 V to +18 V

Figure 1. Typical Connection Diagram - Software Mode

DS726PP2 13

CS4525

Analog

Audio

Inputs

Analog

Monitor

Output

+3.3 or +5 V

Analog

Audio

Switch

Audio

Processor

Clock

24.576 MHz

10 µF

0.1 µF

4 6

1 2

AINL AINR

SCLK5 LRCK SDIN

SYS_CLK

CLK_FREQ0 CLK_FREQ1

470 µF 0.1 µF 0.1 µF 0.1 µF 0.1 µF 470 µF

313025

RAMP_CAP

OUT1

OUT2

CS4525

OUT3

OUT4

TSTO

+8 V to +18 V

Output

Filter

Output

Filter

Micro-

Controller

TSTO

22 kΩ

TWR

ERRUVTE

VA_REG

PGND

LVD

OCREF

FILT+

AGND

AFILTA AFILTB

PGND

15 13

17 18 16

ERROC

EN_TFB

I²S/LJ

ADC/SP

MUTE

RST

TSTO

TSTI

0.1 µF10 µF

VD_REG

GND

PGND

10 2322 28 33 34 37 3827

PGN

Figure 2. Typical Connection Diagram - Hardware Mode

16.2 kΩ

0.1 µF 10 µF

150 pF 150 pF

VD or GND

10 µF

1 µF

14 DS726PP2

4. TYPICAL SYSTEM CONFIGURATION DIAGRAMS

2 x 7 W Stereo + 1 x 15 W Subwoofer

CS4525

Main Tuner

PIP Tuner

A/V In 1

A/V In 2

A/V In X

Main Tuner

PIP Tuner

A/V In 1

A/V In 2

A/V In X

Digital Out

Control Port

A/V Switch

MPEG

Audio Delay

Decoder

Clock

Out

27 MHz

Crystal In

Crystal Out

Figure 3. Typical System Configuration 1

2 x 15 W Stereo + 1 x 30 W Subwoofer

Analog

Out

Sound

Processor

Analog

27 MHz

Crystal In

Crystal Out

Analog Out

Control

Port

Clock

Out

Audio Delay

A/V Switch

CS4525

Analog In Digital In Control

Port Delay

Port Aux

Out SYS_CLK Power

Foldback

Analog In Digital In Control

Port Delay

Port Aux

Out SYS_CLK Power

Foldback

Monitor Out

Gate Drive

PWM_SIG1 PWM_SIG2

Monitor Out

Var/Fixed Out

CS4525

Gate Drive

PWM_SIG1 PWM_SIG2

Left Speaker

Right Speaker

Subwoofer

HP/

Line

Out

Left Speaker

Right Speaker

CS4412A

PWM In

22 kΩ

Status Out

Gate Drive

Subwoofer

Figure 4. Typical System Configuration 2

DS726PP2 15

2 x 30 W Stereo + 1 x 30 W Subwoofer

CS4525

Main Tuner

PIP Tuner

A/V In 1

A/V In 2

A/V In X

A/V Switch

18.432 MHz

Sound

Processor

Analog In

Crystal In

Crystal Out

Analog Out

Analog

Out

Control

Port

Clock

Out

Audio Delay

Monitor Out

Var/Fixed Out

CS4525

Analog In Digital In Control

Port Delay

Port Aux

Out SYS_CLK Power

Foldback

Gate Drive

PWM_SIG1 PWM_SIG2

Left Speaker

CS4412A

PWM In

22 kΩ

Gate

Drive

Gate Drive

Right Speaker

22 kΩ

Figure 5. Typical System Configuration 3

Status Out

CS4412A

PWM In

Status Out

Gate Drive

Subwoofer

16 DS726PP2

2 x 15 W Bi-Amp Stereo with Subwoofer Output

CS4525

Main Tuner

PIP Tuner

A/V In 1

A/V In 2

A/V In X

A/V Switch

18.432 MHz

Sound

Processor

Analog In

Crystal In

Crystal Out

Analog Out

Analog

Out

Digital

Out

Control

Port

Clock

Out

Audio Delay

CS4525

Analog In Digital In Control

Port Delay

Port Aux

Out SYS_CLK Power

Foldback

CS4525

Analog In Digital In Control

Port Delay

Port Aux

Out SYS_CLK Power

Foldback

Monitor Out

Var/Fixed Out

Gate Drive

PWM_SIG1 PWM_SIG2

Gate Drive

PWM_SIG1 PWM_SIG2

Left Tweeter

Left Woofer

Sub Out

Right Tweeter

Right Woofer

Figure 6. Typical System Configuration 4

DS726PP2 17

CS4525

5. CHARACTERISTICS AND SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

AGND = DGND = PGND = 0 V; all voltages with respect to ground.

Parameters Symbol Min Nom Max Units

DC Power Supply

Digital and Analog Core (Note 1) VD 2.375 2.5 2.625 V

VD 3.135 3.3 3.465 V VD 4.75 5.0 5.25 V

Amplifier Outputs VP 8.0 - 18.0 V

Temperature

Ambient Temperature Commercial T Junction Temperature T

-10 - +70 °C

-10 - +125 °C

Notes: 1. For VD = 2.5 V, VA_REG and VD_REG must be connected to VD. See section 6.7 on page 63 for

details.

ABSOLUTE MAXIMUM RATINGS

AGND = DGND = PGND = 0 V; all voltages with respect to ground.

Parameters Symbol Min Max Units

DC Power Supply

Power Stage Outputs Switching and Under Load Power Stage No Output Switching Digital and Analog Core

VP VP VD

-0.3

19.8

23.0

6.0

V V V

Inputs

Input Current (Note 2) I Analog Input Voltage (Note 3) V Digital Input Voltage (Note 3) V

in INA IND

-±10mA

AGND - 0.7 VA_REG + 0.7 V

-0.3 VD + 0.4 V

Temperature

Ambient Operating Temperature - Power Applied

Commercial T

Storage Temperature T

stg

-20 +85 °C

-65 +150 °C

WARNING:Operation beyond these limits may result in permanent damage to the device. Normal operation is not

guaranteed at these extremes.

Notes: 2. Any pin except supplies. Transie nt currents of up to ±100 mA on the analog input pins wi ll not cause

SCR latch-up.

3. The maximum over/under voltage is limited by the input current.

18 DS726PP2

CS4525

ANALOG INPUT CHARACTERISTICS

Test Conditions (unless otherwise specified): AGND = DGND = PGND = 0 V; All voltages with respect to ground; T

= 25°C; VD = 3.3 V; Input Signal: 1 kHz sine wave through the recommended passive input filter shown in Fig-

ure 28 on page 61; Capacitor values connected to AFILTA, AFILTB, FILT+, VQ, VD_REG, and VA_REG as shown

in Figure 1 on page 13; Sample Frequency = 48 kHz; 10 Hz to 20 kHz Measurement Bandwidth; Power outputs in power-down state (PDnOut1 = 1, PDnOut2 = 1, PDnOut3/4 = 1).

Parameter Min Typ Max Unit

Dynamic Range (Note 4) A-weighted

unweighted

Total Harmonic Distortion + Noise -1 dB

-20 dB

-60 dB DC Accuracy Interchannel Gain Mismatch - 0.05 - dB Gain Drift - ±100 - ppm/°C Interchannel Isolation - 90 - dB Full-scale Input Voltage VD = 2.5V (Note 5)

VD = 3.3V VD = 5.0V

Input Impedance (Note 6) 40 - - kΩ

90 87

0.786*VD

0.590*VD

0.398*VD

95 92

-86

-72

-32

0.827*VD

0.621*VD

0.419*VD

-77

0.868*VD

0.652*VD

0.440*VD

dB dB

dB dB dB

Vpp Vpp Vpp

Notes: 4. Referred to the typical full-scale voltage

5. For VD = 2.5 V, VA_REG and VD_REG must be connected to VD. See section 6.7 on page 63 for details.

6. Measured between AINx and AGND.

ADC DIGITAL FILTER CHARACTERISTICS

Parameter Min Typ Max Unit

Passband (Frequency Response) (Note 7) to -0.1 dB corner 0 - 0.4948 Fs Passband Ripple -0.09 - 0 dB Stopband (Note 7) 0.6677 - - Fs Stopband Attenuation 48.4 - - dB Total Group Delay - 2.7/Fs - s

High-Pass Filter Characteristics

Frequency Response -3.0 dB

-0.13 dB Phase Deviation 20 Hz - 10 - Deg Passband Ripple - - 0.17 dB Filter Settling Time -10

Notes: 7. Filter response is clock dependent and scales with the ADC sampling frequency (Fs). With a

27.000 MHz or 24.576 MHz XTAL/SYS_CLK, Fs is equal to the applied clock divided by 512. With an

18.432 MHz XTAL/SYS_CLK, Fs is equal to the applied clock divided by 384.

3.7

24.2

/Fs - s

Hz Hz

DS726PP2 19

CS4525

PWM POWER OUTPUT CHARACTERISTICS

Test Conditions (unless otherwise specified): AGND = DGND = PGND = 0 V; All voltages with respect to ground; T

= 25°C; VD = 3.3 V; VP = 18 V; RL = 8 Ω for full-bridge, RL = 4 Ω for half-bridge and parallel full-bridge;

OutputDly[3:0] = 1111; PhaseShift = 1 for half-bridge, PhaseShift = 0 for full-bridge and parallel full-bridge; Input Signal: full-scale 997 Hz sine wave through serial audio input port, 48 kHz sample rate; Capacitor values connected to AFILTA, AFILTB, FILT+, VQ, VD_REG, and VA_REG as shown in Figur e 1 on page 13; PWM Switch Rate = 384 kHz; 10 Hz to 20 kHz Measurement Bandwidth; Performance measurements taken through AES17 filter.

Parameters Symbol Conditions Min Typ Max Units

Power Output per Channel

Stereo Full-Bridge

Half-Bridge

Parallel Full-Bridge

Total Harmonic Distortion + Noise

Stereo Full-Bridge

Half-Bridge

Parallel Full-Bridge

Dynamic Range

Stereo Full-Bridge

Half-Bridge

Parallel Full-Bridge

MOSFET On Resistance R

THD+N

DYR

DS(ON)

THD+N < 10%

THD+N < 1%

THD+N < 10%

THD+N < 1%

THD+N < 10%

THD+N < 1%

= 1 W

PO = 0 dBFS = 11.3 W

= 1 W

PO = 0 dBFS = 5.0 W

PO = 1 W

= 0 dBFS = 22.6 W

= -60 dBFS, A-Weighted

= -60 dBFS, Unweighted

PO = -60 dBFS, A-Weighted PO = -60 dBFS, Unweighted

= -60 dBFS, A-Weighted

PO = -60 dBFS, Unweighted

15 12

5.5 30

23.5

0.05

0.10

0.12

0.28

0.1

0.3

102

99 99 96

102

Id= 0.5 A, TJ=50°C-280-mΩ

W W W W W W

% % % % % %

dB dB dB dB dB dB

Efficiency h PO = 2 x 15 W, RL = 8 Ω -85-% Minimum Output Pulse Width PW Rise Time of OUTx t Fall Time of OUTx t PWM Output Over-Current Error Trigger Point

Junction Thermal Warning Trigger Point T Junction Thermal Error Trigger Point T VP Under-Voltage Error Falling Trigger Point V VP Under-Voltage Error Rising Trigger Point V

UVFALL UVRISE

r f

min

TA = 25°C, OCREF = 16.2 kΩ

No Load - 50 - ns Resistive Load - 20 - ns Resistive Load - 20 - ns

= 25°C, OCREF = 18 kΩ = 25°C, OCREF = 22 kΩ

2.5

2.1

1.7

A A A

-105-°C

-125-°C TA = 25°C-4.74.9V TA = 25°C - 4.95 5.4 V

20 DS726PP2

CS4525

SERIAL AUDIO INPUT PORT SWITCHING SPECIFICATIONS

AGND = DGND = PGND = 0 V; TA = 25°C; VD = 3.3 V; Inputs: Logic 0 = DGND; Logic 1 = VD.

Parameters Symbol Min Nominal Max Units

28.5

Supported Input Sample Rates F

LRCK Duty Cycle 45 - 55 % SCLK Frequency (Note 8),(Note 9) 1/t SCLK Duty Cycle 45 - 55 % LRCK Setup Time Before SCLK Rising Edge t SDIN Setup Time Before SCLK Rising Edge t SDIN Hold Time After SCLK Rising Edge t RST

pin Low Pulse Width (Note 10) 1--ms

s(LK-SK)

s(SD-SK)

39.5

86.4

FSI*2*N

bits

40 - - ns 25 - - ns 10 - - ns

44.1 48 96

-F

35.2

52.8

105.6

/3 Hz

CLK

kHz kHz kHz kHz

Notes: 8. F

10. After powering up the CS4525, RST

is the frequency of the crystal connected to the XTI/XTO pins or the input SYS_CLK signal.

CLK

is the number of bits per sample of the serial digital input.

bits

should be held low until the power supplies and clocks are stab le.

LRCK

MSB MSB-1

SCLK

SDIN

s(LK-SK)

s(SD-SK)

Figure 7. Serial Audio Input Port Timing

DS726PP2 21

CS4525

AUX SERIAL AUDIO I/O PORT SWITCHING SPECIFICATIONS

AGND = DGND = PGND = 0 V; TA= 25°C; VD = 3.3 V; AUX_SDOUT & DLY_SDOUT CL= 15 pF; Inputs: Logic 0 = DGND; Logic 1 = VD;

Parameters Symbol Min Typ Max Units

Input Source: Analog Inputs (Internal ADC)

Output Sample Rate ClkFreq[1:0] = ‘00’

AUX_LRCK Duty Cycle - 50 - % AUX_LRCK Period - 1/F AUX_SCLK Frequency ClkFreq[1:0] = ‘00’

AUX_SCLK Duty Cycle - 50 - % AUX_SCLK Period - 1/F

Input Source: Serial Audio Input Port

Output Sample Rate F

AUX_LRCK Duty Cycle (Note 13) 45 - 55 % AUX_LRCK Period (Note 12, 13)T AUX_SCLK Frequency F

(Note 14) F

AUX_SCLK Duty Cycle 30 - 70 % AUX_SCLK Period F

(Note 13, 14)F

Input Source: Analog Inputs or Serial Audio Input Port

AUX_LRCK Rising Edge to AUX_SCLK Falling Edge t AUX_SCLK Rising Edge to Data Output Valid t DLY_SDIN Setup Time Before AUX_SCLK Rising Edge t DL Y_SDIN Hold Time After AUX_SCLK Rising Edge t

(Note 11).

ClkFreq[1:0] = ‘01’ ClkFreq[1:0] = ‘10’

= 32kHz, 44.1 kHz, 48 kHz

S-In

= 32kHz, 44.1 kHz, 48 kHz

S-In

= 32kHz, 44.1 kHz, 48 kHz

S-In

=96kHz

SCLKO

LTSF

SRDV

DIS DIH

2*T

SCLKI

- T

CLK

- T

CLK

48*F 64*F 64*F

2*T

/384 /512 /512

SCLKO

FSI/2

SCLKI

SO SO SO

TSI + T

SCLKI

2*T

SCLKI

- - 20 ns

--T

CLK

25 - - ns 10 - - ns

Hz Hz Hz

-s

Hz Hz Hz

-s

CLK

+ T

CLK

Hz Hz

s s

+ 20 ns

Notes: 11. F

12. F

is the frequency of the crystal connected to the XTI/XTO pins or the input SYS_CLK signal.

CLK

=1/F

CLK

is the frequency of the input LRCK signal. TSI=1/F

CLK

13. May vary during normal operation.

14. F

is the frequency of the input SCLK signal. T

SCLKI

AUX_LRCK

AUX_SCLK

AUX_SDOUT

DLY_SDOUT

DLY_SDIN

LSB

DISU

LTSF

MSB

SCLKI

=1/F

SRDV

DIH

SCLKI

MSB - 1

Figure 8. AUX Serial Port Interface Master Mode Timin

22 DS726PP2

CS4525

XTI SWITCHING SPECIFICATIONS

Parameter Symbol Min Typ Max Unit

External Crystal Operating Frequency ClkFreq[1:0] = ‘00’

(Note 15) ClkFreq[1:0] = ‘01’

ClkFreq[1:0] = ‘10’

XTI Duty Cycle 45 50 55 %

CLK

18.240

24.330

26.730

18.432

24.576

27.000

18.617

24.822

27.270

MHz MHz MHz

Notes: 15. See “Clock Frequency (ClkFreq[1:0])” on page 69.

SYS_CLK SWITCHING SPECIFICATIONS

AGND = DGND = PGND = 0 V; TA = 25°C; VD = 3.3 V; Input: Logic 0 = DGND; Logic 1 = VD, SYS_CLK Output:

=20pF.

Parameter Symbol Min Typ Max Unit

External Clock Operating Frequency ClkFreq[1:0] = ‘00’

(Note 15) ClkFreq[1:0] = ‘01’

ClkFreq[1:0] = ‘10’ Rising Edge RST SYS_CLK Period t SYS_CLK Duty Cycle 45 50 55 % SYS_CLK high time t SYS_CLK low time t

to start of SYS_CLK t

sclko

CLK

sclki

clkih

clkil

18.240

24.330

26.730

- 1024*t

37.04 - 54.25 ns

16.67 - 29.84 ns

18.432

24.576

27.000

sclki

18.617

24.822

27.270

MHz MHz MHz

SYS_CLK

(output)

___

RST

sclko

Figure 9. SYS_CLK Timing from Reset

PWM_SIGX SWITCHING SPECIFICATIONS

AGND = DGND = PGND = 0 V; TA = 25°C; VD = 3.3 V; Load = 10 pF.

Parameter Symbol Min Typ Max Unit

Rise Time of PWM_SIGx t Fall Time of PWM_SIGx t

PWM_SIGx

Figure 10. PWM_SIGX Timing

r f

-2.1-ns

-1.4-ns

DS726PP2 23

CS4525

I²C CONTROL PORT SWITCHING SPECIFICATIONS

AGND = DGND = PGND = 0 V; TA = 25°C; VD = 3.3 V; Inputs: Logic 0 = DGND; Logic 1 = VD; SDA CL=30pF.

Parameter Symbol Min Max Unit

SCL Clock Frequency f

Rising Edge to Start t

RST Bus Free Time Between Transmissions t Start Condition Hold Time (prior to first clock pulse) t Clock Low time t Clock High Time t Setup Time for Repeated Start Condition t SDA Hold Time from SCL Falling (Note 16) t SDA Setup time to SCL Rising t Rise Time of SCL and SDA t Fall Time SCL and SDA t Setup Time for Stop Condition t Acknowledge Delay from SCL Falling t

scl

irs

buf

hdst

low high sust hdd

sud

rc fc

susp

ack

- 100 kHz

500 - ns

4.7 - µs

4.0 - µs

4.7 - µs

4.0 - µs

4.7 - µs 10 - ns

250 - ns

-1µs

- 300 ns

4.7 - µs

300 1000 ns

Notes: 16. Data must be held for sufficient time to bridge the transition time, t

RST

SDA

SCL

irs

Stop Start

buf

hdst

low

hdd

high

sud

Repeated

Start

sust

hdst

Figure 11. Control Port Timing - I²C

, of SCL.

Stop

susp

24 DS726PP2

CS4525

DC ELECTRICAL CHARACTERISTICS

AGND = DGND = PGND = 0 V; All voltages with respect to ground; PWM switch rate = 384 kHz; Unless otherwise specified.

Parameters Min Typ Max Units

Normal Operation

Power Supply Current VD = 3.3 V - 54 - mA Power Dissipation VD = 3.3 V - 180 - mW

Power-Down Mode (Note 18)

Power Supply Current VD = 3.3 V - 2.8 - mA

VD_REG Characteristics

Nominal Voltage 2.25 2.5 2.75 V DC current source - - 3 mA

VA_REG Characteristics

Nominal Voltage 2.25 2.5 2.75 V DC current source - - 1 mA

VQ Characteristics

Nominal Voltage - 0.5*VA_REG - V Output Impedance - 23 - kΩ DC current source/sink (Note 19) --10μA Filt+ Nominal Voltage - VA_REG - V Power Supply Rejection Ratio (Note 20) 1 kHz

(Note 17)

60 Hz

60 40

dB dB

Notes: 17. Normal operation is defined as RST

18. Power-Down Mode is defined as RST

= HI.

= LOW with all input lines held static.

19. The DC current drain represents the allowed current from the VQ pin due to typ ica l leakag e thr ough the electrolytic de-coupling capacitors.

20. Valid with the recommended capacitor values on FILT+ and VQ. Increasing the capacitance will increase the PSRR.

DIGITAL INTERFACE SPECIFICATIONS

AGND = DGND = PGND = 0 V; All voltages with respect to ground; Unless otherwise specified.

Parameters Symbol Min Max Units

Digital Interface Signal Characteristics

High-Level Input Voltage V Low-Level Input Voltage V High-Level Output Voltage Io=2 mA

Low-Level Output Voltage Io=2 mA Input Leakage Current I

Input Capacitance - 8 pF

PWM_SIGx Characteristics

High-Level PWM_SIGx Output Voltage Io=2 mA Low-Level PWM_SIGx Output Voltage Io=2 mA

(Note 21)

V V

IH IL

OL in

OHPS OLPS

0.75*VD_REG - V

- 0.20*VD_REG V

0.90*VD - V

-0.2V

-±10uA

0.90*VD_REG - V

-0.2V

Notes: 21. Digital interface signals include all pins sourced from the VD supply as shown in “Digital I/O Pin

Characteristics” on page 12.

DS726PP2 25

6. APPLICATIONS

6.1 Software Mode

Maximum device flexibility and features are available when the CS4525 is used in software mode. The available features are described in the following sections. All device configu ration is achieved via the I²C control port as described in the I²C Control Port Description and Timing section on page 64.

6.1.1 System Clocking

In software mode, the CS4525 can be clocked by a stable external clock source input on the SYS_CLK pin or by a clock internally generated through the use of its internal oscillator driver circuit in conjunction with an external crystal oscillator. The device automatically selects which of these clocks to use within 10 ms of the re lea se of RST

The internal clock is used to synchronize the input serial audio signals with the internal clock domain and to clock the internal digital processing, sample-rate con verter, and PWM modulators. It is also used to determine the sample rate of the serial audio input signals in order to automatically co nfigure the various internal filter coefficients.

To ensure proper operation, the CS4525 must be informed of the nominal frequency of the supplied SYS_CLK signal or the attached crystal via the ClkFreq[1:0] bits in the Clock Config register. These bits must be set to the appropriate value before the PDnAll bit is cleared to initiate a power-up sequence. See the SYS_CLK Switching Specifications and XTI Switching Specifications tables on page 23 for complete input frequency range specifications.

CS4525

WARNING: The system clock source must never be removed or stopped while any of the power output stages are powered-up (the PDnAll bit and any of the PDnOut1, PDnOut2, or PDnOut3/4 bits are cleared) and connected to a load. Doing so may result in permanent dam age to the CS4525 and connected tra nsducers.

Referenced Control Register Location

ClkFreq[1:0]......................... “Clock Frequency (ClkFreq[1:0])” on page 69

PDnAll.................................“Power Down (PDnAll)” on page 89

PDnOutX............................. “Power Down PWM Power Output X (PDnOutX)” on page 88

6.1.1.1 SYS_CLK Input Clock Mode

If an input clock is detected on the SYS_CLK pin following the release of RST, the device will automatically use the SYS_CLK input as its clock source. The applied SYS_CLK clock signal must oscillate within the frequency ranges specified in the SYS_CLK switching specifications table on page 23. In this mode, XTI should be connected to ground and XTO should be left unconnected.

Figure 12 below demonstrates a typical clocking configuration using the SYS_CLK input.

Clock

Clock_In

DSP

Reset_Out

RST

SYS_CLK

CS4525

XTI

XTO

Figure 12. Typical SYS_CLK Input Clocking Configuration

26 DS726PP2

CS4525

6.1.1.2 Crystal Oscillator Mode

To use an external crystal in conjunction with the internal crystal driver, a 20 pF fundamental mode parallel resonant crystal must be connected between the XTI and XTO pins. This crystal must oscillate within the frequency ranges specified in the XTI switching specifications table on page 23. Nothing other than the crystal and its load capacitors should be connected to XTI and XTO. The SYS_CLK pin should be connected to ground through a 22 kΩ pull-down resistor to prevent the CS4525 from r ecogn izing syste m noise on the SYS_CLK pin as a valid clocking signal.

In this mode, the CS4525 will automatically drive the generated internal clock out of the SYS_CLK pin. This can be disabled with the EnSysClk bit which will cause the SYS_CLK pin to become high-impedance. Also, the DivSysClk bit allows the frequency of the generated internal clock to be divided by 2 prior to being driven out of the SYS_CLK.

It should be noted that the internal oscillator driver is disabled when the CS4525 is in reset (RST

is low). Any external devices connected to the SYS_CLK output will not receive a clock signal until the CS4525 is taken out of reset.

If an external crystal is connected to the XTI/XTO pins while an input clock signal is present on the SYS_CLK pin following the release of RST

, then the CS4525 will automatically use the SYS_CLK pin for

its internal clock. Refer to Section 6.1.1.1 for a details about this mode of operation.

Figure 13 below demonstrates a typical clocking configuration using the crystal oscillator.

Reset

XTI

XTO

RST RST

CS4525

SYS_CLK Clock_In

DSP

Figure 13. Typical Crystal Oscillator Clocking Configuration

Referenced Control Register Location

EnSysClk.............................“SYS_CLK Output Enable (EnSysClk)” on page 69

DivSysClk............................ “SYS_CLK Output Divider (DivSysClk)” on page 69

DS726PP2 27

6.1.2 Power-Up and Power-Down

The CS4525 will remain in a completely powered-down state with the control port inaccessible until the RST

pin is brought high. Once RST is high, the control port will be accessible, but all other internal blocks will remain powered-down until they are powered-up via the control port or until hardware mode is entered.

When an external crystal is present on the XTI/XTO pins, software mode will be automatically entered 10 ms a fter the re lease of RST

. If SYS_CLK is used as an input, software mode is entered by writing to the control port within 10 ms after the release of RST device will begin to operate in hardware mode.

6.1.2.1 Recommended Power-Up Sequence

1. Hold RST low until the power supplies and the input SYS_CLK (if used) are stable.

2. Bring RST

The device will remain in a low-power state and the control port will be accessible. The device will automatically enter software mode after 10 ms if an external crystal is present on the XTI/XTO pins, at which time the output SYS_CLK signal will become active.

3. If SYS_CLK is used as an input, initiate a control port write to set the PDnAll bit in register 5Fh within

10 ms following the release of RST

This operation causes the device to enter software mode and places it in power-down mode.

4. If the LVD pin is tied low and VD, VD_REG, and VA_ REG are connected to 2.5 V, clear the SelectVD

bit in the Power Ctrl register to indicate the 2.5 V VD supply level. See section 6.7 on page 63 for details.

5. If VP is connected to a supply voltage less than or equal to 14 V nominal, clear the SelectVP bit in the

Foldback Cfg register to indicate the VP supply level.

6. The desired register settings can be loaded while keeping the PDnAll bit set. Typical initialization set-

tings include Input Configuration, Output Configuration, Master Volume, and Clock Frequency.

7. Clear the PDnAll bit to initiate the power-up sequence.

high.

CS4525

. If the control port is not written within this time, the

6.1.2.2 Recommended Power-Down Sequence

1. Set the MuteChA, MuteChB, and MuteSub bits in the Mute Control register to mute the audio outp ut.

2. Set the PDnAll bit to power-down the device.

3. Bring RST

4. Remove power.

Referenced Control Register Location

PDnAll.................................“Power Down (PDnAll)” on page 89

SelectVD.............................“Select VD Level (SelectVD)” on page 88

SelectVP ............................. “Select VP Level (SelectVP)” on page 74

MuteChX.............................“Independent Channel A & B Mute (MuteChX)” on page 84

MuteSub.............................. “Sub Channel Mute (MuteSub)” on page 85

Input Configuration..............“Input Configuration (Address 02h)” on page 71

Output Configuration........... “Output Configuration (Address 04h)” on page 73

Master Volume.................... “Master Volume Control (Address 57h)” on page 82

Clock Frequency.................“Clock Frequency (ClkFreq[1:0])” on page 69

28 DS726PP2

low to bring the device’s power consumption to an absolute minimum.

6.1.3 Input Source Selection

The CS4525 can accept analog or digital audio input signals. Digital audio input signals are supplied through the serial audio input port as outlined in “Ser ial Audio In terfaces” o n page62. Analog audio input signals are supplied through the internal ADC as outlin ed in “Analog Inputs” on p age 61. The input source is selected by the ADC/SP

bit in the Input Config register.

In software mode, the serial audio input port supports I²S, Left-Justified and Right-Justified data formats. The serial audio input port digital interface format is configured by the DIF[2:0] bits in the Input Conf ig register.

The CS4525 internal ADC includes a dedicated high-pass filter to remove any DC content from the ADC output signal prior to the internal ADC/serial audio input port in put multiplexor. This high-pass filter can be bypassed by clearing the EnAnHPF bit.

Referenced Control Register Location

ADC/SP............................... “Input Source Selection (ADC/SP)” on page 71

DIF[2:0] ............................... “Input Serial Port Digital Interface Format (DIF [2:0])” on page 71

EnAnHPF............................“ADC High-Pass Filter Enable (EnAnHPF)” on page 71

6.1.4 Digital Sound Processing

The CS4525 implements flexible digital sound processing operation s including ba ss manageme nt crossover, 2-way speaker crossovers, high- and low-pass shelving filters, programmabl e parametric EQ filters, adaptive loudness compensation, channel mixers, and volume controls.

CS4525

Stereo

Analog In

Serial Audio

Clocks & Data

Serial Audio

Data I/O

Serial Audio

Clocks & Data

Temperature

Sense

Serial Audio

Data In

The digital signal flow is shown in Figure 14 below. The signal processing blocks are described in detail in the following sections.

ADC

Left

Right

HighPass

Serial Audio

Input Port

Serial Audio

Delay

Interface

Auxiliary

Serial Port

Pre-Scaler

Audio

Processing

Parametric EQ High-Pass Bass/Treble Adaptive

Loudness Compensation

2-Ch Mixer

2.1 Bass Mgr Linkwitz-Riley

Crossover De-Emphasis Volume

Ch. A

Mixer

Ch. B

High-Pass Filter

De-Emphasis

Param. EQ

Bass Tone Ctrl

Sample

Ch. 1

Rate

Converter

Sample

Ch. 2

Rate

Converter

Sample

Sub

Rate

Converter

Temperature Sense

Thermal Foldback Thermal Limiter

Ch. A

Ch. B

Sub

Bass Manager

Treble Tone Ctrl

Loudness

Modulator

Ch. Vol Control

PWM

PWM Output Config

Limiter

Master Vol Control

Aux Serial Data Select

Gate Drive

Ch. A HPF Ch. A LPF

Ch. B HPF

X-Over

Ch. B LPF

Ch. B HPF Ch. B LPF

Ch. A HPF

Ch. A LPF

Sensitivity

Power Stage

Ch. A

Ch. B

Amplifier Out 1

Amplifier Out 2

Amplifier Out 3

Amplifier Out 4

PWM Modulator Output 1

PWM Modulator Output 2

Ch. 1

Ch. 2

Sub

Data to Aux Port

Figure 14. Digital Signal Flow

DS726PP2 29

CS4525

6.1.4.1 Pre-Scaler

Applying any gain to a full-scale signal in the digital domain will cause the signal to clip. To prevent this, a pre-scaler block is included prior to the internal digital signal processing blocks. This allows the input signal to be attenuated before processing to ensure that any signal boosting, such as gain in a shelving filter, will not cause a channel to clip.

The pre-scaler block allows up to -14.0 dB of attenuation in 2.0 dB increments and is controlled with the PreScale[2:0] bits.

Referenced Control Register Location

PreScale[2:0].......................“Pre-Scale Attenuation (PreScale[2:0])” on page 75

6.1.4.2 Digital Signal Processing High-Pass Filter

The CS4525 includes a high-pass filter at the beginning of the digital signal processing chain to remove any DC content from the input signal prior to the remaining internal digital signal processing blocks. The high-pass filter operates by continuously subtracting a measure of the DC offset from the inpu t signal and may be used regardless of the input data source.

The digital signal processing high-pass filter can be disabled by clearing the EnDigHPF bit.

Referenced Control Register Location

EnDigHPF...........................“Digital Signal Processing High-Pass Filter (EnDigHPF)” on page 77

6.1.4.3 Channel Mixer

The CS4525 implements independent channel mi xers to provide for b oth mono mixes and channel swap s for the left and right channels. The channel mi xers are controlled by the LChMix[1:0] and RChMix[1:0] bits in the Mixer Config register.

To allow stereo operation when a mono mix is configured, when the HP_DETECT/MUTE pin is con figured for headphone detection (the HP/Mute active state of the headphone detection input signal. In this configuration, when the left channel mixer is configured for a mono mix (LChMix[1:0] = 01 or 10) and the headphone detection input signal becomes active, the left channel mixer will be automatically reconfigured to output the left channel, thereby disabling the mono mix. When the headphone detection input signal becomes inactive, the mixer will be automatically reconfigured to operate as dictated by the LChMix[1:0] bits.

It should be noted that the right channel mixer output is un affected by the head phone detectio n input signal and will always operate as dictated by the RChMix[1:0] bits.

Referenced Control Register Location

LChMix[1:0]......................... “Left Channel Mixer (LChMix[1:0])” on page 76

RChMix[1:0] ........................ “Right Channel Mixer (RChMix[1:0])” on page 76

HP/Mute

..............................“HP_Detect/Mute Pin Mode (HP/Mute)” on page 70

bit is set), the operation of the left channel mixer is affecte d by the

30 DS726PP2

+ 68 hidden pages

CIRRUS LOGIC CS4525 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

1. PIN DESCRIPTIONS - SOFTWARE MODE

2. PIN DESCRIPTIONS - HARDWARE MODE

2.1 Digital I/O Pin Characteristics

Table 1. I/O Power Rails

3. TYPICAL CONNECTION DIAGRAMS

Figure 1. Typical Connection Diagram - Software Mode

Figure 2. Typical Connection Diagram - Hardware Mode

4. TYPICAL SYSTEM CONFIGURATION DIAGRAMS

Figure 3. Typical System Configuration 1

Figure 4. Typical System Configuration 2

Figure 5. Typical System Configuration 3

Figure 6. Typical System Configuration 4

5. CHARACTERISTICS AND SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

ABSOLUTE MAXIMUM RATINGS

ANALOG INPUT CHARACTERISTICS

ADC DIGITAL FILTER CHARACTERISTICS

PWM POWER OUTPUT CHARACTERISTICS

SERIAL AUDIO INPUT PORT SWITCHING SPECIFICATIONS

Figure 7. Serial Audio Input Port Timing

AUX SERIAL AUDIO I/O PORT SWITCHING SPECIFICATIONS

XTI SWITCHING SPECIFICATIONS

SYS_CLK SWITCHING SPECIFICATIONS

Figure 9. SYS_CLK Timing from Reset

PWM_SIGX SWITCHING SPECIFICATIONS

Figure 10. PWM_SIGX Timing

DC ELECTRICAL CHARACTERISTICS

DIGITAL INTERFACE SPECIFICATIONS

6. APPLICATIONS

6.1 Software Mode

6.1.1 System Clocking

Figure 12. Typical SYS_CLK Input Clocking Configuration

Figure 13. Typical Crystal Oscillator Clocking Configuration

6.1.2 Power-Up and Power-Down

6.1.3 Input Source Selection

6.1.4 Digital Sound Processing

Figure 14. Digital Signal Flow