Cirrus Logic CS4383-KQ, CS4383-BQ, CDB4383 Datasheet

CS4383

114 dB, 192 kHz 8-Channel D/A Converter

Features



24-Bit Conversion



Up to 192 kHz Sample Rates



114 dB Dynamic Range



-100 dB THD+N



Supports PCM and DSD Data Formats



Selectable Digital Filters



Volume Control with Soft Ramp

–1dBStepSize
– Zero Crossing Click-Free Transitions



Dedicated DSD inputs



Low Clock Jitter Sensitivity



µC or Stand-Alone Operation



3 Mute Control pins for Left, Right, and
Surrounds

I

DSD_SCLK(M 3)

SCL/CCLK(M1)

SDA/CDIN(M2) AD0/CS(M0)

Description

The C S4383 is a com plete 8-channel digital-to-analog
system including digital i nterpolation, fifth-order delta­sigma digital-to-analog conversion, digital de-em phas is,
volume control and analog filtering. The advantages of
this architecture include: ideal differential linearity, no
distortion mechanism s due to resistor matching errors,
no linearity drift over time and temperat ure and a high
tolerance to clock jitter.

The CS4383 accepts PCM data at sample rates from
4 k Hz to 192 kHz, DSD audio data, and operates over a
wide power supply range. These features are ideal for
multi-channel audio systems including D VD players,
SACD players, A/V receivers, digital T V’s and VCR’s,
mixing consoles, effects processors, set-top boxes, and
automotive audio systems.

ORDERING INFORM ATION

CS4383-KQ -10 to 70 °C 48-pin LQ FP
CS4383-BQ -40 to 85 °C 48-pin LQ FP
CDB4383 Evaluation Board

VLC

MUTEC1

MUTEC3MUTEC2

RST

VLS
SCLK
LRCK

SD IN1
SD IN2
SD IN3

SD IN4

MCLK

DSDxx

Serial Port

2

÷

8

Control Port(Stand-Alone M ode Select)

Volume Control

Mixer

Volum e Control

Volume Control

Mixer

Volum e Control

Volume Control

Mixer

Volum e Control ∆Σ

Volume Control

Mixer

Volum e Control

Preliminary Product Information

P.O. Box 17847, Austin, Texas 78760
[phone] FAX: [phone]
http://www.cirrus.com

External

Mute Control

VA

∆Σ

∆Σ

∆Σ

∆Σ

∆Σ

∆Σ

∆Σ

DAC

DAC

DAC

DAC

DAC

DAC

DAC

DAC

Analog Filter

Analog Filter

Analog Filter

Analog Filter

Inte rpolation Filte r A nalog Filte r

Interp olation Filte r

In te r p o la ti o n F ilte r A n a lo g F ilte r

Interpolation Filter

In te r p o la ti o n F ilte r A n a lo g F ilte r

Interpolation Filter

In te r p o la ti o n F ilte r A n a lo g F ilte r

Interpolation Filter

GNDVD

GND

This document contains information for a new product.
Cirrus Logic reserves the right to modify this product withoutnotice.

CopyrightCirrus Logic, Inc. 2002

(All Rights Reserved)

AOUTA1+
AOUTA1-

AOUTB1+
AOUTB1-

AOUTA2+
AOUTA2-

AOUTB2+
AOUTB2-

AOUTA3+
AOUTA3-

AOUTB3+
AOUTB3-

AOUTA4+
AOUTA4-

AOUTB4+
AOUTB4-

VQ

FILT+

MAR ‘02

DS548PP2

1

TABLE OF CONTENTS

1. CHARACTERISTICS AND SPECIFICATIONS ................................................................. 4

2. REGISTER QUICK REFERENCE ................................................................................... 14

3. REGISTER DESCRIPTION ............................................................................................. 15

4. PIN DESCRIPTION .......................................................................................................... 24

5. APPLICATIONS .............................................................................................................. 27

5.1 Grounding and Power Supply Decoupling ........................................................... 27

5.2 Oversampling Modes ........................................................................................... 27

5.3 Recommended Power-up Sequence ................................................................... 27

5.4 Analog Output and Filtering ................................................................................. 27

5.5 Interpolation Filter ................................................................................................ 27

5.6 Using DSD mode ................................................................................................. 28

6. CONTROL PORT INTERFACE ....................................................................................... 28

6.1 Enabling the Control Port ..................................................................................... 28

6.2 Format Selection .................................................................................................. 28

2

6.3 I

C Format ............................................................................................................ 28

6.3.1 Writing in I2C Format .......................................................................28

6.3.2 Reading in I

6.4 SPI Format ........................................................................................................... 29

6.4.1 Writing in SPI ..................................................................................29

6.5 Memory Address Pointer (MAP) ..................................................................... 30

7. PARAMETER DEFINITIONS ........................................................................................... 38

8. REFERENCES ................................................................................................................. 38

9. PACKAGE DIMENSIONS ............................................................................................... 39

2

C Format ....................................................................29

CS4383

LIST OF FIGURES

Figure 1 . Serial Mode Input Timing .................................................................................................8

Figure 2. Direct Stream Digital - Serial Audio Input Timing.............................................................9

Figure 3. Control Port Timing - I

Figure 4 . Contro l PortTiming - SPI Format...................................................................................11

Figure 5 . Typical Connection Diagram Control Port...................................................................... 12

Contacting Cirrus Logic Support

For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts

IMPORTANT NOTICE
"Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. "Advance" product informa-

tion describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information
contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any
kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied
onis current and complete. All products aresoldsubject to the termsand conditions of salesupplied at thetimeof order acknowledgment,includingthosepertaining
to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of thisinformatio nas
the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document isthe property of Cirrus and by furnishing
this information, Cirrus grantsno license, express or impliedunderany patents, mask workrights, copyrights, trademarks, trade secretsor other intellectual property
rights. Cirrus owns the copyrights of the information containedhereinand gives consent for copies to be made of the information only for usewithin your organization
with respect to Cirrus integrated circuitsor other parts of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising
or promotional purposes, or for creating any work for resale.

An export permit needs to be obtained fromthe competent authorities of the Japanese Government if any of the products or technologies described in this material
and controlled under the"Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. An export license and/or quota needs to be obtained
from the competent authorities of the ChineseGovernment if any of the products or technologies described in this material is subject to thePRC Foreign Trade Law
and is to be exported or taken out of the PRC.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP­ERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TOBE
SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH
APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK.

Purchase of I
those components in a standard I

Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. A ll otherbrand and product names inthis document may be trademarks
or service marks of their respective owners.

2

C components of Cirrus Logic, Inc., or one of its sublicensed Associated Companies conveys a license under the Phillips I2C Patent Rights to use

2

Csystem.

2

C Format ...................................................................................10

2

CS4383

Figure 6 . Typical Connection Diagram Stand-Alone..................................................................... 13

Figure 7. Control Port Timing, I

Figure 8 . Control Port Timing, SPI Format....................................................................................29

Figure 9 . Single Speed (fast) Stopband Rejection........................................................................ 31

Figure 1 0. Single Speed (fast) Transition Band ............................................................................ 31

Figure 1 1. Single Speed (fast) Transition Band (detail) ................................................................31

Figure 1 2. Single Speed (fast) Passband Ripple .......................................................................... 31

Figure 13. Single Speed (slow) Stopband Rejection..................................................................... 31

Figure 14. Single Speed (slow) Transition Band........................................................................... 31

Figure 1 5. Single Speed (slow) Transition Band (detail)............................................................... 32

Figure 16. Single Speed (slow) Passband Ripple......................................................................... 32

Figure 1 7. Double Spee d (fast) Stopband Rejection ..................................................................... 32

Figure 1 8. Double Spee d (fast) Transition Band........................................................................... 32

Figure 1 9. Double Spee d (fast) Transition Band (detail)............................................................... 32

Figure 2 0. Double Spee d (fast) Passband Ripple......................................................................... 32

Figure 2 1. Double Speed (slow) Stopband Rejection ................................................................... 33

Figure 2 2. Double Speed (slow) Transition Band .........................................................................33

Figure 2 3. Double Speed (slow) Transition Band (detail) .............................................................33

Figure 2 4. Double Speed (slow) Passband Ripple ....................................................................... 33

Figure 2 5. Quad Speed (fast) Stopband Rejection....................................................................... 33

Figure 2 6. Quad Speed (fast) Transition Band ............................................................................. 33

Figure 2 7. Quad Speed (fast) Transition Band (detail).................................................................34

Figure 2 8. Quad Speed (fast) Passband Ripple ...........................................................................34

Figure 2 9. Quad Speed (slow) Stopband Rejection...................................................................... 34

Figure 3 0. Quad Speed (slow) Transition Band............................................................................ 34

Figure 3 1. Quad Speed (slow) Transition Band (detail)................................................................34

Figure 3 2. Quad Speed (slow) Passband Ripple.......................................................................... 34

Figure 3 3. Format 0 - Left Justified up to 24-bit Data.................................................................... 35

Figure 34. Format1 - I

Figure 3 5. Format 2 - Right Justified 16-bit Da ta .......................................................................... 35

Figure 3 6. Format 3 - Right Justified 24-bit Da ta .......................................................................... 35

Figure 3 7. Format 4 - Right Justified 20-bit Da ta .......................................................................... 36

Figure 3 8. Format 5 - Right Justified 18-bit Da ta .......................................................................... 36

Figure 3 9. De-Emphasis Curve..................................................................................................... 36

Figure 4 0. Chann el Pair Routing Diagram (x = C hannel Pair 1, 2, 3, or 4)................................... 36

Figure 4 1. ATAPI Block Diagram (x = channel pair 1, 2, 3, or 4)..................................................37

Figure 4 2. Recommended Output Filter........................................................................................37

2

S up to 24-bit Data................................................................................... 35

2

C Format .................................................................................... 29

LIST OF TABLES

Table 1. Digital Interface Formats - PCM Mode............................................................................ 16

Table 2. Digital Interface Formats - DSD Mode............................................................................16

Table 3. ATAPI Decode ................................................................................................................ 21

Table 4. Example Digital Volume Settings ....................................................................................22

Table 5. Commo n Clock Frequenc ies........................................................................................... 26

Table 6. Digital Interface Format, Stand-Alone M ode Options...................................................... 26

Table 7. Mode Selection, Stand-Alone Mode O ptions..................................................................26

Table 8. Direct Stream Digital (DSD), Stand-Alone Mode Options............................................... 26

3

CS4383

1. CHARACTERISTICS AND SPECIFICATIONS

ANALOG CHARACTERISTICS (Full-Scale Output Sine Wave, 997 Hz; Measuremen t Bandwid th

10 Hz to 20 kHz, unless otherwise specified; Test load R
For Single speed Mode Fs = 48 kHz, SCLK = 3.072 MHz, MCLK = 12.288 MHz;

For Double Speed Mode Fs = 96 kHz, SCLK = 6. 144 MHz, MCLK = 12.288 MHz;
For Quad Speed Mode Fs = 192 kHz, SCLK = 12.288 MHz, MCLK = 24.576 MHz;
For Direct Stream Digital Mode Fs = 128 x 48 kHz, DSD_S CLK = 6.144 MHz, MCLK = 12.288 MHz).

Parameters Symbol Min Typ Max Unit

CS4383-KQ Dynamic Performance - All PCM mo des and DSD (Note 1)

Specified Temperature Range T
Dynamic Range (Note 2) 24-bit unweighted

A-Weighted

16-bit unweighted

(Note 3) A-Weighted

Total Harmonic Distortion + Noise (Note 2 )

24-bit 0 dB

-20 dB

-60 dB

16-bit 0 dB

(Note 3) -20 dB

-60 dB
Idle Channel Noise / Signal-to-noise ratio - 114 - dB
Interchannel Isolation (1 k Hz ) - 90 - dB

CS4383-BQ Dynamic Performance - All PCM mo des and DSD (Note 4)

Specified Temperature Range T
Dynamic Range (Note 2) 24-bit unweighted

A-Weighted

16-bit unweighted

(Note 3) A-Weighted

Total Harmonic Distortion + Noise (Note 2 )

24-bit 0 dB

-20 dB

-60 dB

16-bit 0 dB

(Note 3) -20 dB

-60 dB
Idle Channel Noise / Signal-to-noise ratio - 114 - dB
Interchannel Isolation (1 k Hz ) - 90 - dB

=3kΩ,CL= 100 pF, VA = 5 V, VD = 3.3V (see Figure 5)

L

A

THD+N

A

THD+N

-10 - 70 °C

105
108

-

-

-

-

-

-

-

-

-40 - 85 °C

102
105

-

-

-

-

-

-

-

-

111
114

94
97

-100

-91

-51

-94

-74

-34

111
114

94
97

-100

-91

-51

-94

-74

-34

-

-

-

-

-94

-

-

-

-

-

-

-

-

-

-91

-

-

-

-

-

dB
dB
dB
dB

dB
dB
dB
dB
dB
dB

dB
dB
dB
dB

dB
dB
dB
dB
dB
dB

Notes: 1. CS4383-KQ parts are tested at 25 °C .

2. One-halfLSB of triangular PDF dither is added to data.

3. Performance limited by 16-bit quantizationnoise.

4. CS4383-BQ parts are tested at the extremes of the specified temperature range and Min/Max
performance numbers are guaranteed across the s pecified temperature range, T
takenat25°C.

4

. Typical numbers are

A

CS4383

ANALOG CHARACTERISTICS (Continued)

Parameters Symbol Min Typ Max Units

Analog Output - All PCM mo des an d DSD

FullScaleDifferential Output Voltage (Note 5) V
Quiescent Voltage V
Max Currentfrom V

Q

FS

I

QMAX

Q

Interchannel Gain Mismatch - 0.1 - dB
Gain Drift - 100 - ppm/°C
Output Impedance (Note 5) Z
AC-Load Resistance R
Load C apacitance C

OUT

L
L

POWER AND THERMAL CHARACTERISTICS

Parameters Symbol Min Typ Max Units

Power Supplies

Power Supply Current normal operation, V
(Note 6) V

Interface current, VLC=5V (Note 7, 8)

power-down state (all supplies) (Note 9)

Power Dissipation (Note 6)
VA = 5 V, VD = 3.3 V normal operation

power-down (Not e 9)

VA = 5 V, VD = 5 V normal operation

power-down (Not e 9)

Package Thermal Resistance θ

Power Supply Rejection Ratio (Note 10) (1 k Hz )

A
D

V

=3.3V

D

VLS=5V

(60 Hz)

=5V
=5V

88% V

A

92% V

A

94% V

A

Vpp

-50%VA-VDC

-1 -µA

- 100 - Ω

3- -kΩ

- - 100 pF

I

A

I

D

I

D

I

LC

I

LS

I

pd

JA

θ

JC

PSRR -

-

-

-

-

-

-

-

-

-

-

-

-

60
45
30

2

84

200

400

1

525

1

48
15

60

-

40

66
70
46

-

-

-

485

-

680

-

-

-

-

-

mA
mA
mA

µA
µA
µA

mW
mW
mW
mW

°C/Watt
°C/Watt

dB
dB

Notes: 5. VFSis tested under load RLand includes attenuation due to Z

6. Current consumption increases with increasing FS within a given speed mode andis s ignal dependant.
Max values are based on highest FS and highest MCLK.

7. I

measured wi th no external loading on the SDA pin.

LC

8. This specification is violated when the VLC supply is greater than VD and when pin 16 (M1 /SDA ) i s tied
or pulled low. Logic tied to pin 16 needs to be able to sink this current.

9. Power down mode is defined as RST

pin = L ow w ith all clock and data lines held static.

10. Valid with the recommended capacitor values on FILT+ and VQ as shown in Fi gures 5 and 6.

OUT

5

CS4383

ANALOG FILTER RESPONSE

Fast Roll-Off Slow Roll-Off (Note 11)

Parameter

Combined Digital and On-chip Analog Filter Response - Single Speed Mode (Note 12)

Passband (Note 13) to -0.01 dB corner

to -3 dB corner00
Frequency Response 10 Hz to 20 k Hz -0.01 - +0.01 -0.01 - +0.01 dB
StopBand .547 - - .583 - - Fs
StopBand Attenuation (Note 14) 90 - - 64 - - dB
Group Delay - 12/Fs - - 6.5/Fs - s
Passband Group Delay Deviation 0 - 20 kHz - - ±0.41/Fs - ±0.14/Fs s
De-emphasis Error (Note 1 5) Fs = 32 kHz
(Relative to 1kHz) Fs = 44.1 kHz

Fs = 48 kHz

Combined Digital an d On -chip Analog Filter Response - Double Speed Mode - 96kHz (Note 12)

Passband (Note 13) to -0.01 dB corner

to -3 dB corner00
Frequency Response 10 Hz to 20 kHz -0.01 - 0.01 -0.01 - 0.01 dB
StopBand .583 - - .792 - - Fs
StopBand Attenuation (Note 14) 80 - - 70 - - dB
Group Delay - 4.6/Fs - - 3 .9/Fs - s
Passband Group Delay Deviation 0 - 20 kHz - - ±0.03/Fs - ±0.01/Fs s

Combined Digital and On-chip Analog Filter Respons e - Quad Speed Mode - 192kHz (Note 12)

Passband (Note 13) to -0.01 dB corner

to -3 dB corner00
Frequency Response 10 Hz to 20 kHz -0.01 - 0.01 -0.01 - 0.01 dB
StopBand .635 - - .868 - - Fs
StopBand Attenuation (Note 14) 90 - - 75 - - dB
Group Delay - 4.7/Fs - - 4 .2/Fs - s
Passband Group Delay Deviation 0 - 20 kHz - - ±0.01/Fs - ±0.01/Fs s

Combined Digital and On-chip Analog Filter Response - DSD Mode (Note 12)

Passband (Note 13) to -0.1 dB c orner

to -3 dB corner
Frequency Response 10 Hz to 20 kHz - - - -.01 - 0.1 dB

Notes: 11. Slow Roll-Offinterpolationfilter is only availablein control port mode.

12. Filter response is not tested but is guaranteed by design.

13. Response is clock dependent and will scale with Fs. Note that the response plots(Figures 9 t o 32) have
been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.

14. Single and Double Speed Mode Measurement Bandwidth is from stopband to 3 Fs.
Quad Speed Mode Measurement Bandwidth is from stopband to 1.34 Fs.

15. De-emphasis is available only in Single Speed Mode; Only 44.1kHz De-emphasis is av ailable in Stand­Alone Mode

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

.454
.499

±0.23
±0.14
±0.09

.430
.499

.105
.490

-

-

0
0

-

-

-

0
0

0
0

0
0

-

-

-

-

-

-

-

-

-

-

-

0.417

0.499

±0.23
±0.14
±0.09

.296
.499

.104
.481

20

120

UnitMin Typ Max Min Typ Max

kHz
kHz

Fs
Fs

dB
dB
dB

Fs
Fs

Fs
Fs

6

CS4383

DIGITAL CHAR ACTERISTICS (For KQ T

=-10to+70°C;ForBQTA=-40to+85°C;VLC=VLS=

A

1.8 V to 5.5 V)

Parameters Symbol Min Typ Max Units

High-Level Input Voltage Serial Data Port

Control P ort

Low-Level Input Voltage Serial Data Port

Control P ort

Input Leakage Current (Note 8) I

V
V

V
V

IH
IH

IL
IL

in

70% VLS
70% VLC

-

-

-

-

-

20% VLS

-

20% VLCVV

-

-

--±10µA

V
V

Input Capacitance - 8 - pF
Maximum MUTEC Sink Current - 3 - mA
MUTEC High-Level Output Voltage V
MUTEC Low-Level Output Voltage V

OH

OL

-VA-V

-0-V

ABSOLUTE MAXIMUM RATINGS (GND = 0V; all voltages wi th respect to ground.)

Parameters Symbol Min Max Units

DC Power Supply Analog power

Digital internal power

Serial data port interface power

Control port interface power
Input Current, Any Pin Except Supplies I
Digital InputVoltage Serial data port interface

Control port interface
Ambient Operating Temperature (power applied) T
Storage Temperature T

WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is

not gu aranteed at these extremes.

VD
VLS
VLC

V

IND-S

V

IND-C

VA

stg

-0.3

-0.3

-0.3

-0.3

in

-±10mA

-0.3

-0.3

A

-55 125 °C

6.0

6.0

6.0

6.0

VLS+ 0.4
VLC+ 0.4

V
V
V
V

V
V

-65 150 °C

RECOMMENDED OPERATING CONDITIONS (GND = 0V; all voltages with respect to ground.)

Parameters Symbol Min Typ Max Units

DC Power Supply Analog powe r

Digital internal power

Serial data port interface power

Control port interface power

VA

VD
VLS
VLC

4.5

3.0

1.8

1.8

5.0

3.3

5.0

5.0

5.5

5.5

5.5

5.5

V
V
V
V

7

CS4383

SWITCHING CHARACTERISTI CS (For KQ T

1.8 V to 5.5 V; Inputs: Logic 0 = GND, Logic 1 = VLS, C

=-10to+70°C;ForBQTA=-40to+85°C;VLS=

A

= 30pF)

L

Parameters Symbol Min Typ Max Units

MCLK Frequency (Note 16)

Single Speed Mode 1.024 - 51.2 MHz

Double Speed Mode 6.400 - 51.2 MHz

Quad Speed Mode 6.400 - 51.2 MHz
MCLK Duty Cycle 40 50 60 %
Input S ample Rate Single Speed Mode

Double Speed Mode

Quad Speed Mode

Fs
Fs
Fs

4

50

100

-

-

-

50
100
200

kHz
kHz

kHz
LRCK Duty Cycle 45 50 55 %
SCLK Pulse Wi dth Low t
SCLK Pulse Width High t
SCLK Period t

(Note 17) t

SCLK rising to LRCK edge delay t
SCLK rising to LRCK edge setup t im e t
SDATA valid to SCLK rising setup time t
SCLK rising to SDATA hold time t

sclkl

sclkh

sclkw

sclkw

slrd

slrs

sdlrs

sdh

20 - - ns
20 - - ns

2

------------------

MCLK

4

------------------

MCLK

--ns

--ns

20 - - ns
20 - - ns
20 - - ns
20 - - ns

Notes: 16. See Table 5 on page 26 for suggested MCLK frequencies

17. This serial clock is available only in Control Port Mode when the MCLK Divide bit is enabled.

.

LRCK

t

t

slrd

SCLK

t

sdlrs

SDATA

Figure 1. Serial Mode Input Timing

slrs

t

sclkl

t

sdh

t

sclkh

8

CS4383

DSD - SWITCHING CHARACTERISTICS (

Logic 0 = GND; VLS = 1.8 V to 5.5 V; Logic 1 = VLS Volts; C

Parameter Symbol Min Typ Max Unit

Master Clock Frequency (Note 18) 4.096 - 38.4 MHz
MCLK Duty Cycle (All DSD modes) 40 50 60 %
DSD_SCLK Pulse Width Low t
DSD_SCLK Pulse W idth High t
DSD_SCLK Frequency (64x Oversam pled)

(128x Oversampled)
DSD_L / _R valid to DSD_SCLK rising setup time t
DSD_SCLK rising to DSD_L or DSD_R hold time t

Note: 18. Min is 4 times 64 x DSD or 2 times 128x DSD, and Max is 12 times 64x DSD or 6 times 128x DSD. The

proper MCLK to DSD_SCLK ratio must be set either by the DIF registers or the M0:2 pins

For KQ TA=-10to+70°C; For BQ TA=-40to+85°C;

=30pF)

L

sclkl

sclkh

sdlrs

sdh

20 --ns
20 --ns

1.024

2.048
20 --ns
20 --ns

t

sclkh

t

sclkl

-

-

3.2

6.4

MHz
MHz

DSD_SCLK

DSD_L, DSD_R

Figure 2. Direct Stre am Digital - Serial Audio Input Timing

sdlrstsdh

t

9

CS4383

SWITCHING CHARACTERISTICS - CONTROL PORT - I2CFORMAT (For KQ T

=-10to+70°C; For BQ TA=-40to+85°C; VLC = 1.8 V to 5.5 V; Inputs: Logic 0 = GND, Logic 1 = VLC,
C

=30pF)

L

Parameter Symbol Min Max Unit

SCL Clock Frequency f

Rising Edge to Start t

RST
Bus F ree Time Between Transmissions t
Start Condition Hold Time (prior to first clock pulse) t
Clock Low time t
Clock High Time t
Setup Time for Repeated Start Condition t
SDA Hold Time from SCL Falling (Note 17) t
SDA Setup time to SCL Rising t
Rise Time of SCL and SDA t
Fall TimeSCL and SDA t
Setup Time for Stop Condition t
Acknowledge Delay from SCL Falling (Note 18) t

scl

irs

buf

hdst

low
high
sust

hdd
sud

rc,trc

fc,tfc

susp

ack

- 100 kHz

500 - ns

4.7 - µs

4.0 - µs

4.7 - µs

4.0 - µs

4.7 - µs
0-µs

250 - ns

-1µs

- 300 ns

4.7 - µs

-(Note21)ns

A

Notes: 19. Dat a must be held for sufficient time to bridge the transition time, t

20. The acknowledge delay is based on MCLK and can limit the maximum transaction speed.

15

21. forSingle-Speed Mode, forDouble-Speed Mode, for Quad-SpeedMode.

RST

SDA

SCL

--------------------­256 Fs×

t

irs

Stop S t a rt

t

buf

t

hdst

t

low

t

hdd

t

high

15

-------------------- ­128 Fs×

t

sud

t

ack

Repeated

t

Figure 3. Control Port Timing - I2CFormat

,ofSCL.

fc

----------------- ­64 Fs×

Start

t

sust

15

t

hdst

Stop

rd

t

rc

t

fd

t

fc

t

susp

10

CS4383

SWITCHING CHARACTERISTI CS - CONTROL PORT - SPI FORMAT

(For KQ TA=-10to+70°C; For BQ TA=-40to+85°C; VLC = 1.8 V to 5.5 V; Inputs: Logic 0 = GND, Logic 1 = VLC,
C

=30pF)

L

Parameter Symbol Min Max Unit

CCLK Clock Fr equency f

RST

Rising Edge to CS Falling t

CCLK Edge to CS

High Time Between Transmissions t

CS

Falling to CCLK Edge t

CS

Falling (Note 20) t

CCLK Low Time t

sclk

srs

spi
csh
css

scl

-MHz

MCLK

----------------- ­2

500 - ns
500 - ns

1.0 - µs
20 - ns

1

----------------- ­MCLK

-ns

CCLK High Time t

CDIN to CCLK Rising Setup Time t
CCLK Rising to DATA Hold Time (Note 21) t
Rise Time of CCLK and CDIN (Note 22) t
Fall Time of CCLK and CDIN (Note 22) t

Notes: 22. t

only needed before first falling edge of CS after RST rising edge. t

spi

23. Data must be held for sufficient time to bridge t he transition time of CCLK.

24. For F

SCK

<1MHz.

RST

t

srs

CS

t

t

spi

css

t

scl

t

sch

CCLK

sch

dsu

dh

r2
f2

1

----------------- ­MCLK

-ns

40 - ns
15 - ns

- 100 ns

- 100 ns

= 0 at all other times.

spi

t

csh

CDIN

t

r2

t

f2

t

dsu

t

dh

Figure 4. Control Port Timing - SPI Format

11

CS4383

+3.3Vto+5V

+1.8Vto+5V

PCM

Digital

Audio

Source

DSD

Audio

Source

1µF

0.1 µF

9
8

11
12
13

43

48

47
46
45

44
42

+

0.1 µF

6
7

3
2
1

VD

MCLK
LRCK

SCLK
SDIN1
SDIN2
SDIN3
SDIN4

VLS

DSDA1
DSDB1
DSDA2

DSDB2

DSDA3
DSDB3

DSDA4

DSDB4
DSD_SCLK

4

CS4383

32

VA

AOUTA1+

AOUTA1-

MUTEC1

AOUTB1+

AOUTB1-

MUTEC2

AOUTA2+

AOUTA2-

AOUTB2+

AOUTB2-

AOUTA3+

AOUTA3-

AOUTB3+

AOUTB3-

AOUTA4+

AOUTA4-

AOUTB4+

AOUTB4-

MUTEC3

0.1 µ F

39
40

41

38
37

22

35
36

34
33

29
30

28
27

25
26

24
23

19

+

1µF

Analog Conditioning

and Muting

Analog Co nditioning

and Muting

Analog Conditioning

and Muting

Analog Conditioning

and Muting

Analog Conditioning

and Muting

Analog Conditioning

and Muting

Analog Conditioning

and Muting

Analog Conditioning

and Muting

+5 V

+1.8Vto+5V

12

Micro-

C o n t ro ller

Ω

2K

Note*

Note: Necessary for I2C
control port operation

18

RST

14

SCL/CC LK

15

SDA/CDIN

16

ADO/CS

Ω

2K

20

FILT+

0.1 µF

17

VLC

GND

5

GND

31

VQ

21

0.1 µ

Figure 5. Typical Connection Diagram Control Port

+

F

F

1µF

+

0.1 µ

47 µF