CIRRUS LOGIC CS4382A Service Manual

CS4382A

114 dB, 192 kHz 8-channel D/A Converter

Features

 Advanced Multi-bit Delta Sigma Architecture
 24-bit Conversion
 Up to 192 kHz Sample Rates
 114 dB Dynamic Range
 -100 dB THD+N
 Direct Stream Digital Mode

– On-chip 50 kHz filter
– Matched PCM and DSD analog output

levels

 Selectable Digital Filters
 Volume Control with 1-dB Step Size and Soft

Ramp

 Low Clock Jitter Sensitivity
 +5 V Analog Supply, +2.5 V Digital Supply
 Separate 1.8 to 5 V Logic Supplies for the

Control & Serial Ports

Description

The CS4382A is a complete 8-channel digi tal-to-analog
system. This D/A system includes digital de-emphasis,
one-dB step size volume control, ATAPI channel mix­ing, selectable fast and slow digital interpolation filters
followed by an oversampled, multi-bit delta sigma mod­ulator which includes mismatch shaping technology that
eliminates distortion due to capacitor mismatch. Follow­ing this stage is a multi-element switched capacitor
stage and low-pass filter with differential analog
outputs.

The CS4382A also has a proprietary DSD processor
which allows for 50 kHz on-chip filtering without an in­termediate decimation stage.

The CS4382A accepts PCM data at sample rates from
4 kHz to 216 kHz, DSD audio data, and delivers excel­lent sound quality. These featu res are ideal for multi­channel audio systems including SACD players, A/V re­ceivers, digital TV’s, mixing consoles, effects
processors, sound cards and automotive audio
systems.

ORDERING INFORMATION

Hardware Mode or

2

C/SPI Software Mode

I

http://www.cirrus.com

Control & Serial Audio Port
Supplies = 1.8 V to 5 V

Control Data

Reset

PCM Serial

Audio Input

DSD Audio

Input

See page 41.

Digital Supply = 2.5 V

Register/Hardware

Configuration

Level TranslatorLevel Translator

8

Serial Interface

Volume

Controls

DSD Processor

-50 kHz filter

Digital
Filters

Copyright © Cirrus Logic, Inc. 2005

(All Rights Reserved)

Multi-bit ∆Σ
Modulators

Analog Supply = 5 V

Internal Voltage

Reference

Switch-Cap

DAC and

Analog Filters

External Mute

Control

8

8

2

Differential
Outputs

Mute Signals

APR '05

DS618PP1

TABLE OF CONTENTS

1. PIN DESCRIPTION..................................................................................................................... 6

2. CHARACTERISTICS AND SPECIFICATIONS.......................................................................... 8

3. APPLICATIONS ....................................................................................................................... 20

3.1 Master Clock..................................................................................................................... 20

3.2 Mode Select...................................................................................................................... 20

3.3 Digital Interface Formats .................................................................................................. 22

3.4 Oversampling Modes........................................................................................................ 23

3.5 Interpolation Filter............................................................................................................. 23

3.6 De-Emphasis.................................................................................................................... 23

3.7 ATAPI Specification.......................................................................................................... 24

3.8 Direct Stream Digital (DSD) Mode. ... ... ... .... ... ... ... .... ... ... .......................................... ... ... ... 25

3.9 Grounding and Power Supply Arrangements................................................................... 25

3.9.1 Capacitor Placement............................................................................................ 25

3.10 Analog Output and Filtering...................... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... ... 25

3.11 Mute Control...................................... ... .... ... ... ... .......................................... .... ............... 26

3.12 Recommended Power-Up Sequence............................................................................. 27

3.12.1 Hardware Mode ........................................ ... .......................................... ... ... ... ... 27

3.12.2 Software Mode.......................................................................... ... ... .... ... ... ... ...... 27

3.13 Recommended Procedure for Switching Operational Modes......................................... 27

3.14 Control Port Interface ..................... ... .............................................................................28

3.14.1 MAP Auto Increment.......................................................................................... 28

3.14.2 I

3.14.3 SPI™ Mode.................................................................. ... ... .... ... ... ... ................... 30

3.15 Memory Address Pointer (MAP) ............................................................................... 30

4. REGISTER QUICK REFERENCE............................................................................................ 31

5. REGISTER DESCRIPTION ...................................................................................................... 32

5.1 Mode Control 1 (address 01h).......................................................................................... 32

5.1.1 Control Port Enable (CPEN)................................................................................ 32

5.1.2 Freeze Controls (Freeze)..................................................................................... 32

5.1.3 Master Clock DIVIDE ENABLE (mclkdiv) ............................................................ 32

5.1.4 DAC Pair Disable (DACx_DIS) ............................................................................ 32

5.1.5 Power Down (PDN).............................................................................................. 33

5.2 Mode Control 2 (address 02h)......................................................................................... 33

5.2.1 Digital Interface Format (dif) ................................................................................ 33

5.2.2 Mode Control 3 (address 03h)............................................................................ 34

5.2.3 Soft Ramp AND Zero Cross CONTROL (SZC) ................................................... 34

5.2.4 Single Volume Control (Snglvol).......................................................................... 34

5.2.5 Soft Volume Ramp-Up after Error (RMP_UP) ..................................................... 35

5.2.6 MUTEC Polarity (MUTEC+/-)............................................................................... 35

5.2.7 Auto-Mute (AMUTE) ........................................................................................... 35

5.3 Mutec Pin Control (MUTEC)............................................................................................. 35

5.4 Filter Control (address 04h)............................................................................................. 36

5.4.1 Interpolation Filter Select (FILT_SEL).................. .... ... ... ... ... .... ... ... ...................... 36

5.4.2 De-Emphasis Control (DEM) ............................................................................... 36

5.4.3 Soft Ramp-Down before Filter Mode Change (RMP_DN) ................................... 36

5.5 Invert Control (address 05h)............................................................................................ 37

5.5.1 Invert Signal Polarity (Inv_Xx).............................................................................. 37

5.6 Mixing Control Pair 1 (Channels A1 & B1)(address 06h)
Mixing Control Pair 2 (Channels A2 & B2)(address 09h)

2

C Mode .. ... .......................................... .... .......................................... ... ............ 28

3.14.2.1 I

3.14.2.2 I

3.14.3.1 SPI Write...................... ... ... ... .... ... ... .......................................... ... ...... 30

CS4382A

2

C Write ............................ ... .... .......................................... ............... 28

2

C Read.................. .... ... ... ... .... ... ... .......................................... ... ...... 29

2 DS618PP1

CS4382A

Mixing Control Pair 3 (Channels A3 & B3)(address 0Ch)

Mixing Control Pair 4 (Channels A4 & B4)(address 0Fh) ............................................. 37

5.6.1 Channel A Volume = Channel B Volume (A=B)................................................... 37

5.6.2 ATAPI Channel Mixing and Muting (ATAPI)............... ... ... ... .... ... ... ... .... ... ... ... ... ... 37

5.6.3 Functional Mode (FM).......................................................................................... 38

5.7 Volume Control (addresses 07h, 08h, 0Ah, 0Bh, 0Dh, 0Eh).............. ... ... ... .... ... ... ... ...... 39

5.7.1 Mute (MUTE) ....................... ... ... .... ...................................... .... ... ... ... .... ............... 39

5.7.2 Volume Control (xx_VOL)........................................ ... ... ... ... .... ... ......................... 39

5.8 Chip Revision (address 12h) ........................................................................................... 40

5.8.1 Part Number ID (part) [Read Only] ...................................................................... 40

6. PARAMETER DEFINITIONS.................................................................................................... 41

7. REFERENCES.......................................................................................................................... 41

8. ORDERING INFORMATION .................................................................................................... 41

9. PACKAGE DIMENSIONS ........................................................................................................ 42

10. APPENDIX ............................................................................................................................. 43

DS618PP1 3

LIST OF FIGURES

Figure 1. Serial Audio Interface Timing..................................................................................................... 14

Figure 2. Direct Stream Digital - Serial Audio Input Timing....................................................................... 15

Figure 3. Control Port Timing - I

Figure 4. Control Port Timing - SPI Format............................................................................................... 17

Figure 5. Typical Connection Diagram, Software Mode............................................................................ 18

Figure 6. Typical Connection Diagram, Hardware Mode .......................................................................... 19

Figure 7. Format 0 - Left-Justified up to 24-bit Data ................................................................................. 22

Figure 8. Format 1 - I

Figure 9. Format 2 - Right-Justified 16-bit Data........................................................................................ 22

Figure 10. Format 3 - Right-Justified 24-bit Data...................................................................................... 22

Figure 11. Format 4 - Right-Justified 20-bit Data...................................................................................... 23

Figure 12. Format 5 - Right-Justified 18-bit Data...................................................................................... 23

Figure 13. De-Emphasis Curve................................................................................................................. 24

Figure 14. ATAPI Block Diagram (x = channel pair 1, 2, or 3) .................................................................. 24

Figure 15. Full-Scale Output..................................................................................................................... 26

Figure 16. Recommended Output Filter.................................................................................................... 26

Figure 17. Control Port Timing, I

Figure 18. Control Port Timing, SPI mode........................... ... ... ... .... ... ... ... ... .... ... ... ... .... ........................... 30

Figure 19. Single-Speed (fast) Stopband Rejection.................................................................................. 43

Figure 20. Single-Speed (fast) Transition Band........................................................................................ 43

Figure 21. Single-Speed (fast) Transition Band (detail)............................................................................ 43

Figure 22. Single-Speed (fast) Passband Ripple.............................................. ... ... ... .... ........................... 43

Figure 23. Single-Speed (slow) Stopband Rejection ........................ ... ... ... ... ............................................ 43

Figure 24. Single-Speed (slow) Transition Band....................................................................................... 43

Figure 25. Single-Speed (slow) Transition Band (detail)........................................................................... 44

Figure 26. Single-Speed (slow) Passband Ripple..................................................................................... 44

Figure 27. Double-Speed (fast) Stopband Rejection ................................................................................ 44

Figure 28. Double-Speed (fast) Transition Band....................................................................................... 44

Figure 29. Double-Speed (fast) Transition Band (detail)........................................................................... 44

Figure 30. Double-Speed (fast) Passband Ripple..................................................................................... 44

Figure 31. Double-Speed (slow) Stopband Rejection............................................................................... 45

Figure 32. Double-Speed (slow) Transition Band............................. ... ... ... ... ............................................ 45

Figure 33. Double-Speed (slow) Transition Band (detail)............................. .... ... ... ... .... ... ... ..................... 45

Figure 34. Double-Speed (slow) Passband Ripple................................................................................... 45

Figure 35. Quad-Speed (fast) Stopband Rejection................................. ... ... .... ... ... .................................. 45

Figure 36. Quad-Speed (fast) Transition Band ......................................................................................... 45

Figure 37. Quad-Speed (fast) Transition Band (detail)................. .... ... ... ... ... .... ... ..................................... 46

Figure 38. Quad-Speed (fast) Passband Ripple....................................................................................... 46

Figure 39. Quad-Speed (slow) Stopband Rejection.................................................................................. 46

Figure 40. Quad-Speed (slow) Transition Band........................................................................................ 46

Figure 41. Quad-Speed (slow) Transition Band (detail)............................................................................ 46

Figure 42. Quad-Speed (slow) Passband Ripple...................................................................................... 46

CS4382A

2

C Format...................... .... ... ... ... .... ... ... ... ... .......................................... .. 16

2

S up to 24-bit Data................................................................................................. 22

2

C Mode................................................................................................. 29

4 DS618PP1

LIST OF TABLES

Table 1. Common Clock Frequencies........................................................................................... 20

Table 2. Digital Interface Format, Stand-Alone Mode Options... ... .... ... ... ... ... ................................ 21

Table 3. Mode Selection, Stand-Alone Mode Options......................... ... ... ... .... ... ... ... .... ... ... ... ... ... 21

Table 4. Direct Stream Digital (DSD), Stand-Alone Mode Options............................................... 21

Table 5. Digital Interface Formats - PCM Mode............................................................................ 33

Table 6. Digital Interface Formats - DSD Mode ............................................................................ 33

Table 7. ATAPI Decode ................................... ... .... .......................................... ... ......................... 38

Table 8. Example Digital Volume Settings.................................................................................... 39

Table 9. Revision History ............................................................................................................. 47

CS4382A

DS618PP1 5

1. PIN DESCRIPTION

DSDA2

DSDB1
DSDA1

GND

MCLK

LRCK(DSD_EN)

SDIN1
SCLK

TST

SDIN2

TST

DSDB4

DSDB3

DSDA3

DSDA4

DSDB2

48 47 46 45 44 4 3 42 41 40 39 38 37

1
2
3
4

VD

5
6
7
8
9
10
11

2

1

13 14 15 16 17 1 8 19 20 21 22 23 24

SDIN3

SDIN4

M2(SCL/CCLK)

CS4382A

M0(AD0/CS)

M1(SDA/CDIN)

CS4382A

AOUTB1+

AOUTB1-

AOUTA1-

AOUTA1+

MUTEC1

VLS

M3(DSD_SCLK)

AOUTA2-

36

AOUTA2+

35

AOUTB2+

34

AOUTB2-

33
32

VA
GND

31
30

AOUTA3­AOUTA3+

29

AOUTB3+

28

AOUTB3-

27
26

AOUTA4-

25

AOUTA4+

VQ

VLC

RST

FILT+

MUTEC2

AOUTB4-

AOUTB4+

Pin Name # Pin Description

VD 4 Digital Power (Input) - Positive power supply for the digital section.
GND 531Ground (Input) - Ground reference. Should be connected to analog ground.

MCLK 6 Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters.
LRCK 7 Left Right Clock (Input) - Determines which channe l, Left or Right, is currently active on

the serial audio data line. The frequency of the left/right clock must be at the audio sample
rate, Fs.

Serial Audio Data Input (Input) - Input for two’s complement serial audio data.

SDIN1
SDIN2
SDIN3
SDIN4

8
11
13
14

SCLK 9 Serial Clock (Input) - Serial clock for the serial audio interface.
VLC 18 Control Port Power (Input) - Determines the required signal level for the control port.

Refer to the Recommended Operating Conditions for appropriate voltages.

RST 19 Reset (Input) - The device enters a low power mode and all internal registers are reset to

their default settings when low.

FILT+ 20 Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling

circuits. Requires the capacitive decoupling to analog ground, as shown in the Typical Con­nection Diagram.

VQ 21 Quiescent Voltage (Output) - Filter connection for internal quiescent voltage. VQ must be

capacitively coupled to analog ground, as shown in the Typical Connection Diagram. The
nominal voltage level is specified in the Analog Characteristics and Specifications section.
VQ presents an appreciable source impedance and any current drawn from this pin will
alter device performance. However, VQ can be used to bias the analog circuitry assuming
there is no AC signal component and the DC current is less than the maximum specified in
the Analog Characteristics and Specifications section.

6 DS618PP1

CS4382A

Pin Name # Pin Description

MUTEC1
MUTEC234

AOUTA1 +,­AOUTB1 +,­AOUTA2 +,­AOUTB2 +,­AOUTA3 +,­AOUTB3 +,­AOUTA4 +,­AOUTB4 +,-

VA 32 Analog Power (Input) - Positive power supply for the analog section.
VLS 43 Serial Audio Interface Power (Input) - Determines the required signal level for the serial

TST 10

Software Mode Definitions

SCL/CCLK 15 Serial Control Port Clock (Input) - Serial clock for the serial control port. Requires an

SDA/CDIN 16

AD0/CS

Stand-Alone Definitions

M0
M1
M2
M3

DSD Definitions

DSD_SCLK 42 DSD Serial Clock (Input) - Serial clock for the Direct Stream Digital audio interface.
DSD_EN 7 DSD-Enable (Input) - When held at logic ‘1’ the device will enter DSD mode (Stand-Alone

DSDA1
DSDB1
DSDA2
DSDB2
DSDA3
DSDB3
DSDA4
DSDB4

4122Mute Control (Output) - The Mute Control pins go high during power-up initialization, reset,

muting, power-down or if the master clock to left/right clock frequency ratio is incorrect.
These pins are intended to be used as a control for external mute circuits to prevent the
clicks and pops that can occur in any single supply system. The use of external mute cir­cuits are not mandatory but may be desired for designs requiring the absolute minimum in
extraneous clicks and pops.

39, 40
38, 37
35, 36
34, 33
29, 30
28, 27
25, 26
24, 23

Differential Analog Output (Output) - The full scale differential analog output level is sp ec-
ified in the Analog Characteristics specification table.

audio interface. Refer to the Recommended Operating Conditions for appropriate voltages.

Test - These pins need to be tied to analog ground.

12

external pull-up resistor to the logic inter fac e vo ltage in I
Connection Diagram.

Serial Control Data (Input/Output) - SDA is a data I/O line in I
external pull-up resistor to the logic interface voltage, as shown in the Typical Connection
Diagram. CDIN is the input data line for the control port interface in SPI mode.

17

Address Bit 0 (I

2

C mode; CS is the chip select signal for SPI format.

I

Mode Selection (Input) - Determines the operational mode of the device.

17
16
15
42

mode only).
Direct Stream Digital Input (Input) - Input for Direct Stream Digital serial audio data.

3
2

1
48
47
46
45
44

2

C) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in

2

C mode as shown in the Typical

2

C mode and requires an

DS618PP1 7

CS4382A

2. CHARACTERISTICS AND SPECIFICATIONS

All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical
performance characteristics and spe cif icat ion s ar e de ri ved from measurements taken at nominal supply voltage
and T

= 25°C.

A

SPECIFIED OPERATING CONDITIONS

(GND = 0 V; all voltages with respect to ground.)

Parameters Symbol Min Typ Max Units

4.75

2.37

1.71

1.71

-10

-40

-0.3

-0.3

-0.3

-0.3

-0.3

-0.3

VLS
VLC

VA
VD

VLS

VLC

V

IND-S

V

IND-C

VA

VD

T

in

op

stg

A

DC Power Supply Analog power

Digital internal power

Serial data port interface power

Control port interface power

Specified Temperature Range -CQZ

-EQZ

Absolute Maximum Ratings
(GND = 0 V; all voltages with respect to ground.)

Parameters Symbol Min Max Units

DC Power Supply Analog power

Digital internal power

Serial data port interface power

Control port interface power
Input Current Any Pin Except Supplies I
Digital Input Voltage Serial data port interface

Control port interface
Ambient Operating Temperature (power applied) T
Storag e Temperature T

WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation

is not guaranteed at these extremes.

5.0

2.5

5.0

5.0

-

-

-±10mA

-55 125 °C

-65 150 °C

5.25

2.63

5.25

5.25
+70

+105

6.0

3.2

6.0

6.0

VLS+ 0.4
VLC+ 0.4

V
V
V
V

°C
°C

V
V
V
V

V
V

8 DS618PP1

CS4382A

DAC ANALOG CHARACTERISTICS

Full-Scale Output Sine Wave, 997 Hz (Note 1); Fs = 48/96/192 kHz; Test load RL = 3 kΩ, CL = 100 pF; Measure-
ment Bandwidth 10 Hz to 20 kHz, unless otherwise specified.

Parameters Symbol Min Typ Max Unit

CS4382A-CQZ Dynamic Performance - All PCM modes and DSD

Specified Temperature Rang e T
Dynamic Range 24-bit A-weighted

unweighted

16-bit A-weighted

(Note 2) unweighted

Total Harmonic Distortion + Noise

24-bit 0 dB

-20 dB

-60 dB

(Note 2) 16-bit 0 dB

-20 dB

-60 dB

Idle Channel Noise / Signal-to-noise ratio - 114 - dB

CS4382A-EQZ Dynamic Performance - All PCM modes and DSD

Specified Temperature Rang e T
Dynamic Range (Note 1) 24-bit A-weighted

unweighted

16-bit A-weighted

(Note 2) unweighted

Total Harmonic Distortion + Noise (Note 1)

24-bit 0 dB

-20 dB

-60 dB

(Note 2) 16-bit 0 dB

-20 dB

-60 dB

Idle Channel Noise / Signal-to-noise ratio - 114 - dB

A

THD+N

A

THD+N

-10 - 70 °C

108
105

-

-

-

-

-

-

-

-

-40 - 105 °C

105
102

-

-

-

-

-

-

-

-

114
111

97
94

-100

-91

-51

-94

-74

-34

114
111

97
94

-100

-91

-51

-94

-74

-34

-

-

-

-

-94

-

-45

-

-

-

-

-

-

-

-91

-

-42

-

-

-

dB
dB
dB
dB

dB
dB
dB
dB
dB
dB

dB
dB
dB
dB

dB
dB
dB
dB
dB
dB

Notes:

1. One-half LSB of triangular PDF dither is added to data.

2. Performance limited by 16-bit quantization noise.

DS618PP1 9

CS4382A

DAC ANALOG CHARACTERISTICS - ALL MODES (CONTINUED)

Parameters Symbol Min Typ Max Units

Interchannel Isolation (1 kHz) - 110 - dB

DC Accuracy

Interchannel Gain Mismatch - 0.1 - dB
Gain Drift - 100 - ppm/°C

Analog Output

Full Scale Differential- PCM, DSD processor
Output Voltage Direct DSD mode

Output Impedance (Note 3) Z
Max DC Current draw from an AOUT pin I
Min AC-Load Resistance R
Max Load Capacitance C
Quiescent Voltage V
Max Current draw from V

Q

V

FS

OUT

OUTmax

L
L

Q

I

QMAX

132%•V

94%•V

A

A

134%•V

96%•V

A

A

136%•V

98%•V

Vpp

A

Vpp

A

-130-Ω

-1.0-mA

-3-kΩ

-100-pF

- 50% VA-VDC

-10-µA

POWER AND THERMAL CHARACTERISTICS

Parameters Symbol Min Typ Max Units

Power Supplies

Power Supply Current normal operation, VA= 5 V
(Note 4) VD= 2.5 V

(Note 5) Interface current, VLC=5 V

VLS=5 V

(Note 6) power-down state (all supplies)

Power Dissipation (Note 4) VA = 5 V, VD = 2.5 V

normal operation

(Note 6) power-down

Package Thermal Resistance θ

Power Supply Rejection Ratio (Note 7) (1 kHz)

PSRR -

(60 Hz)

I

A

I

D

I

LC

I

LS

I

pd

-

-

-

-

-

-

-

JA

θ

JC

-

-

75
20

2

84

200

426

1

48
15

60

-

40

83
26

-

-

-

482

-

-

-

-

-

mA
mA

µA
µA
µA

mW
mW

°C/Watt
°C/Watt

dB
dB

Notes:

3. V

is tested under load RL and includes attenuation due to Z

FS

OUT

4. Current consumption incr eases with increasing FS within a given speed mode and is signal dependant.
Max values are based on highest FS and highest MCLK.

5. I

6. Power down mode is defined as RST

measured with no external loading on the SDA pin.

LC

pin = Low with all clock and data lines held static.

7. Valid with the recommended capacitor values on FILT+ and VQ as shown in Figures 5 and 6.

10 DS618PP1

CS4382A

COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE

The filter characteristics have been normalized to the sample rate (Fs) and can be referenced to the desired sam­ple rate by multiplying the given characteristic by Fs.
(See note 12.)

Parameter

Combined Digital and On-chip Analog Filter Response - Single-Speed Mode - 48 kHz

Passband (Note 9) to -0.01 dB corner
Frequency Response 10 Hz to 20 kHz -0.01 - +0.01 dB

StopBand 0.547 - - Fs
StopBand Attenuation (Note 10) 102 - - dB
Group Delay - 10.4/Fs - s
De-emphasis Error (Note 11) Fs = 32 kHz
(Relative to 1 kHz) Fs = 44.1 kHz

Combined Digital and On-chip Analog Filter Response - Double-Speed Mode - 96 kHz

Passband (Note 9) to -0.01 dB corner
Frequency Response 10 Hz to 20 kHz -0.01 - +0.01 dB

StopBand .583 - - Fs
StopBand Attenuation (Note 10) 80 - - dB
Group Delay - 6.15/Fs - s

Combined Digital and On-chip Analog Filter Response - Quad-Speed Mode - 192 kHz

Passband (Note 9) to -0.01 dB corner
Frequency Response 10 Hz to 20 kHz -0.01 - +0.01 dB

StopBand .635 - - Fs
StopBand Attenuation (Note 10) 90 - - dB
Group Delay - 7.1/Fs - s

to -3 dB corner

Fs = 48 kHz

to -3 dB corner

to -3 dB corner

0
0

-

-

-

0
0

0
0

Fast Roll-Off

-

-

-

-

-

-

-

-

-

.454
.499

±0.23
±0.14
±0.09

.430
.499

.105
.490

UnitMin Typ Max

Fs
Fs

dB
dB
dB

Fs
Fs

Fs
Fs

Notes:

8. Slow Roll-off interpolation filter is only available in software mode.

9. Response is clock dependent and will scale with Fs.

10. For Single-Speed Mode, the Measurement Bandwidth is from stopband to 3 Fs.
For Double-Speed Mode, the Measurement Bandwidth is from stopband to 3 Fs.
For Quad-Speed Mode, the Measurement Bandwidth is from stopband to 1.34 Fs.

11. De-emphasis is available only in Single-Speed Mode; Only 44.1 kHz De-emphasis is available in hard­ware mode.

12. Amplitude vs. Frequency plots of this data are available starting on page 43.

DS618PP1 11

CS4382A

COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE

(CONTINED)

Slow Roll-Off (Note 8)

Parameter

Single-Speed Mode - 48 kHz

Passband (Note 9) to -0.01 dB corner

to -3 dB corner
Frequency Response 10 Hz to 20 kHz -0.01 - +0.01 dB
StopBand .583 - - Fs
StopBand Attenuation (Note 10) 64 - - dB
Group Delay - 7.8/Fs - s
De-emphasis Error (Note 11) Fs = 32 kHz
(Relative to 1 kHz) Fs = 44.1 kHz

Fs = 48 kHz

Double-Speed Mode - 96 kHz

Passband (Note 9) to -0.01 dB corner

to -3 dB corner
Frequency Response 10 Hz to 20 kHz -0.01 - +0.01 dB
StopBand .792 - - Fs
StopBand Attenuation (Note 10) 70 - - dB
Group Delay - 5.4/Fs - s

Quad-Speed Mode - 192 kHz

Passband (Note 9) to -0.01 dB corner

to -3 dB corner
Frequency Response 10 Hz to 20 kHz -0.01 - +0.01 dB
StopBand .868 - - Fs
StopBand Attenuation (Note 10) 75 - - dB
Group Delay - 6.6/Fs - s

0
0

-

-

-

0
0

0
0

-

-

-

-

-

-

-

-

-

0.417

0.499

±0.36
±0.21
±0.14

.296
.499

.104
.481

UnitMin Typ Max

Fs
Fs

dB
dB
dB

Fs
Fs

Fs
Fs

DSD COMBINED DIGITAL & ON-CHIP ANALOG FILTER RESPONSE

Parameter Min Typ Max Unit

DSD Processor mode

Passband (Note 9) to -3 dB corner 0 - 50 kHz
Frequency Response 10 Hz to 20 kHz -0.05 - +0.05 dB
Roll-off 27 - - dB/Oct

12 DS618PP1

CS4382A

DIGITAL CHARACTERISTICS

Parameters Symbol Min Typ Max Units

Input Leakage Current (Note 13) I

in

Input Capacitance - 8 - pF
High-Level Input Voltage Serial I/O

Control I/O

Low-Level Input Voltage Serial I/O

Control I/O

High-Level Output Voltage (IOH= -1.2 mA) Control I/O V
Low-Level Output Voltage (IOL= 1.2 mA) Control I/O V
Maximum MUTEC Drive Current I

MUTEC High-Level Output Voltage V
MUTEC Low-Level Output Voltage V

V
V

V
V

OH

max

OH

IH
IH

IL
IL

OL

OL

13. Any pin except supplies. Transient currents of up to ±100 mA on the input pins will not cause SCR latch­up

--±10µA

70%
70%

-

-

-

-

-

-

-

-

30%
30%

V
V

V
V

80% - - V

--20%V

-3-mA

-VA-V

-0-V

LS
LC

LS
LC

LC
LC

DS618PP1 13

CS4382A

SWITCHING CHARACTERISTICS - PCM

(Inputs: Logic 0 = GND, Logic 1 = VLS, CL = 30 pF)

Parameters Symbol Min Max Units

pin Low Pulse Width (Note 14) 1 - ms

RST
MCLK Frequency 1.024 55.2 MHz

MCLK Duty Cycle (Note 15) 45 55 %
Input Sample Rate - LRCK Single-Speed Mode

Double-Speed Mode

Quad-Speed Mode
LRCK Duty Cycle 45 55 %
SCLK Duty Cycle 45 55 %
SCLK High Time t
SCLK Low Time t
LRCK Edge to SCLK Rising Edge t
SDIN Setup Time Before SCLK Rising Edge t
SDIN Hold Time After SCLK Rising Edge t

Notes:

F

s

F

s

F

s

sckh

sckl
lcks

ds
dh

4

50

100

54
108
216

kHz
kHz
kHz

8-ns
8-ns
5-ns
3-ns
5-ns

14. After powering up, RST

should be held low until after the power supplies and clocks are settled.

15. See Table 1 on page 20 for suggested MCLK frequencies.

LRCK

t

sckh

t

dh

SCLK

t

lcks

t

ds

t

sckl

SDINx

Figure 1. Serial Audio Interface Timing

MSB

MSB-1

14 DS618PP1

CS4382A

SWITCHING CHARACTERISTICS - DSD

(Logic 0 = AGND = DGND; Logic 1 = VLS; CL=20pF)

Parameter Symbol Min Typ Max Unit

MCLK Duty Cycle 40 - 60 %
DSD_SCLK Pulse Width Low t
DSD_SCLK Pulse Width High t
DSD_SCLK Frequency (64x Oversampled)

(128x Oversampled)
DSD_A / _B valid to DSD_SCLK rising setup time t
DSD_SCLK rising to DSD_A or DSD_B hold time t

DSD_SCLK

sclkl

sclkh

sdlrs

sdh

t

160 - - ns
160 - - ns

1.024

2.048

-

­20 - - ns
20 - - ns

t

sclkh

sclkl

3.2

6.4

MHz
MHz

DSDxx

sdlrstsdh

Figure 2. Direct Stream Digital - Serial Audio Input Timing

t

DS618PP1 15