Advanced Multi-bit Delta Sigma Architecture
24-bit Conversion
Up to 192 kHz Sample Rates
114 dB Dynamic Range
-100 dB THD+N
Direct Stream Digital Mode
–On-chip 50 kHz filter
–Matched PCM and DSD analog output
levels
Selectable Digital Filters
Volume Control with 1-dB Step Size and Soft
Ramp
Low Clock Jitter Sensitivity
+5 V Analog Supply, +2.5 V Digital Supply
Separate 1.8 to 5 V Logic Supplies for the
Control & Serial Ports
Description
The CS4382A is a complete 8-channel digi tal-to-analog
system. This D/A system includes digital de-emphasis,
one-dB step size volume control, ATAPI channel mixing, selectable fast and slow digital interpolation filters
followed by an oversampled, multi-bit delta sigma modulator which includes mismatch shaping technology that
eliminates distortion due to capacitor mismatch. Following this stage is a multi-element switched capacitor
stage and low-pass filter with differential analog
outputs.
The CS4382A also has a proprietary DSD processor
which allows for 50 kHz on-chip filtering without an intermediate decimation stage.
The CS4382A accepts PCM data at sample rates from
4 kHz to 216 kHz, DSD audio data, and delivers excellent sound quality. These featu res are ideal for multichannel audio systems including SACD players, A/V receivers, digital TV’s, mixing consoles, effects
processors, sound cards and automotive audio
systems.
ORDERING INFORMATION
Hardware Mode or
2
C/SPI Software Mode
I
http://www.cirrus.com
Control & Serial Audio Port
Supplies = 1.8 V to 5 V
Table 8. Example Digital Volume Settings.................................................................................... 39
Table 9. Revision History ............................................................................................................. 47
CS4382A
DS618PP15
1. PIN DESCRIPTION
DSDA2
DSDB1
DSDA1
GND
MCLK
LRCK(DSD_EN)
SDIN1
SCLK
TST
SDIN2
TST
DSDB4
DSDB3
DSDA3
DSDA4
DSDB2
48 47 46 45 44 4 3 42 41 40 39 38 37
1
2
3
4
VD
5
6
7
8
9
10
11
2
1
13 14 15 16 17 1 8 19 20 21 22 23 24
SDIN3
SDIN4
M2(SCL/CCLK)
CS4382A
M0(AD0/CS)
M1(SDA/CDIN)
CS4382A
AOUTB1+
AOUTB1-
AOUTA1-
AOUTA1+
MUTEC1
VLS
M3(DSD_SCLK)
AOUTA2-
36
AOUTA2+
35
AOUTB2+
34
AOUTB2-
33
32
VA
GND
31
30
AOUTA3AOUTA3+
29
AOUTB3+
28
AOUTB3-
27
26
AOUTA4-
25
AOUTA4+
VQ
VLC
RST
FILT+
MUTEC2
AOUTB4-
AOUTB4+
Pin Name#Pin Description
VD4Digital Power (Input) - Positive power supply for the digital section.
GND531Ground (Input) - Ground reference. Should be connected to analog ground.
MCLK6Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters.
LRCK7Left Right Clock (Input) - Determines which channe l, Left or Right, is currently active on
the serial audio data line. The frequency of the left/right clock must be at the audio sample
rate, Fs.
Serial Audio Data Input (Input) - Input for two’s complement serial audio data.
SDIN1
SDIN2
SDIN3
SDIN4
8
11
13
14
SCLK 9Serial Clock (Input) - Serial clock for the serial audio interface.
VLC18Control Port Power (Input) - Determines the required signal level for the control port.
Refer to the Recommended Operating Conditions for appropriate voltages.
RST19Reset (Input) - The device enters a low power mode and all internal registers are reset to
their default settings when low.
FILT+20Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling
circuits. Requires the capacitive decoupling to analog ground, as shown in the Typical Connection Diagram.
VQ21Quiescent Voltage (Output) - Filter connection for internal quiescent voltage. VQ must be
capacitively coupled to analog ground, as shown in the Typical Connection Diagram. The
nominal voltage level is specified in the Analog Characteristics and Specifications section.
VQ presents an appreciable source impedance and any current drawn from this pin will
alter device performance. However, VQ can be used to bias the analog circuitry assuming
there is no AC signal component and the DC current is less than the maximum specified in
the Analog Characteristics and Specifications section.
VA32Analog Power (Input) - Positive power supply for the analog section.
VLS43Serial Audio Interface Power (Input) - Determines the required signal level for the serial
TST10
Software Mode Definitions
SCL/CCLK15Serial Control Port Clock (Input) - Serial clock for the serial control port. Requires an
SDA/CDIN16
AD0/CS
Stand-Alone Definitions
M0
M1
M2
M3
DSD Definitions
DSD_SCLK42DSD SerialClock (Input) - Serial clock for the Direct Stream Digital audio interface.
DSD_EN7DSD-Enable(Input) - When held at logic ‘1’ the device will enter DSD mode (Stand-Alone
DSDA1
DSDB1
DSDA2
DSDB2
DSDA3
DSDB3
DSDA4
DSDB4
4122Mute Control (Output) - The Mute Control pins go high during power-up initialization, reset,
muting, power-down or if the master clock to left/right clock frequency ratio is incorrect.
These pins are intended to be used as a control for external mute circuits to prevent the
clicks and pops that can occur in any single supply system. The use of external mute circuits are not mandatory but may be desired for designs requiring the absolute minimum in
extraneous clicks and pops.
Differential Analog Output (Output) - The full scale differential analog output level is sp ec-
ified in the Analog Characteristics specification table.
audio interface. Refer to the Recommended Operating Conditions for appropriate voltages.
Test - These pins need to be tied to analog ground.
12
external pull-up resistor to the logic inter fac e vo ltage in I
Connection Diagram.
Serial Control Data (Input/Output) - SDA is a data I/O line in I
external pull-up resistor to the logic interface voltage, as shown in the Typical Connection
Diagram. CDIN is the input data line for the control port interface in SPI mode.
17
Address Bit 0 (I
2
C mode; CS is the chip select signal for SPI format.
I
Mode Selection (Input) - Determines the operational mode of the device.
17
16
15
42
mode only).
Direct Stream Digital Input (Input) - Input for Direct Stream Digital serial audio data.
3
2
1
48
47
46
45
44
2
C) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in
2
C mode as shown in the Typical
2
C mode and requires an
DS618PP17
CS4382A
2. CHARACTERISTICS AND SPECIFICATIONS
All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical
performance characteristics and spe cif icat ion s ar e de ri ved from measurements taken at nominal supply voltage
and T
= 25°C.
A
SPECIFIED OPERATING CONDITIONS
(GND = 0 V; all voltages with respect to ground.)
ParametersSymbol Min TypMaxUnits
4.75
2.37
1.71
1.71
-10
-40
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
VLS
VLC
VA
VD
VLS
VLC
V
IND-S
V
IND-C
VA
VD
T
in
op
stg
A
DC Power Supply Analog power
Digital internal power
Serial data port interface power
Control port interface power
Specified Temperature Range -CQZ
-EQZ
Absolute Maximum Ratings
(GND = 0 V; all voltages with respect to ground.)
ParametersSymbolMinMaxUnits
DC Power Supply Analog power
Digital internal power
Serial data port interface power
Control port interface power
Input Current Any Pin Except SuppliesI
Digital Input Voltage Serial data port interface
Control port interface
Ambient Operating Temperature (power applied)T
Storag e TemperatureT
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation
is not guaranteed at these extremes.
5.0
2.5
5.0
5.0
-
-
-±10mA
-55125°C
-65150°C
5.25
2.63
5.25
5.25
+70
+105
6.0
3.2
6.0
6.0
VLS+ 0.4
VLC+ 0.4
V
V
V
V
°C
°C
V
V
V
V
V
V
8DS618PP1
CS4382A
DAC ANALOG CHARACTERISTICS
Full-Scale Output Sine Wave, 997 Hz (Note 1); Fs = 48/96/192 kHz; Test load RL = 3 kΩ, CL = 100 pF; Measure-
ment Bandwidth 10 Hz to 20 kHz, unless otherwise specified.
ParametersSymbolMinTypMaxUnit
CS4382A-CQZ Dynamic Performance - All PCM modes and DSD
Specified Temperature Rang eT
Dynamic Range 24-bit A-weighted
unweighted
16-bit A-weighted
(Note 2) unweighted
Total Harmonic Distortion + Noise
24-bit 0 dB
-20 dB
-60 dB
(Note 2) 16-bit 0 dB
-20 dB
-60 dB
Idle Channel Noise / Signal-to-noise ratio-114-dB
CS4382A-EQZ Dynamic Performance - All PCM modes and DSD
Specified Temperature Rang eT
Dynamic Range (Note 1) 24-bit A-weighted
unweighted
16-bit A-weighted
(Note 2) unweighted
Total Harmonic Distortion + Noise (Note 1)
24-bit 0 dB
-20 dB
-60 dB
(Note 2) 16-bit 0 dB
-20 dB
-60 dB
Idle Channel Noise / Signal-to-noise ratio-114-dB
A
THD+N
A
THD+N
-10-70°C
108
105
-
-
-
-
-
-
-
-
-40-105°C
105
102
-
-
-
-
-
-
-
-
114
111
97
94
-100
-91
-51
-94
-74
-34
114
111
97
94
-100
-91
-51
-94
-74
-34
-
-
-
-
-94
-
-45
-
-
-
-
-
-
-
-91
-
-42
-
-
-
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Notes:
1. One-half LSB of triangular PDF dither is added to data.
2. Performance limited by 16-bit quantization noise.
DS618PP19
CS4382A
DAC ANALOG CHARACTERISTICS - ALL MODES (CONTINUED)
ParametersSymbolMinTypMaxUnits
Interchannel Isolation (1 kHz)-110-dB
DC Accuracy
Interchannel Gain Mismatch-0.1-dB
Gain Drift-100-ppm/°C
Analog Output
Full Scale Differential- PCM, DSD processor
Output VoltageDirect DSD mode
Output Impedance (Note 3)Z
Max DC Current draw from an AOUT pinI
Min AC-Load ResistanceR
Max Load CapacitanceC
Quiescent VoltageV
Max Current draw from V
Q
V
FS
OUT
OUTmax
L
L
Q
I
QMAX
132%•V
94%•V
A
A
134%•V
96%•V
A
A
136%•V
98%•V
Vpp
A
Vpp
A
-130-Ω
-1.0-mA
-3-kΩ
-100-pF
- 50% VA-VDC
-10-µA
POWER AND THERMAL CHARACTERISTICS
ParametersSymbolMinTypMaxUnits
Power Supplies
Power Supply Current normal operation, VA= 5 V
(Note 4) VD= 2.5 V
(Note 5) Interface current, VLC=5 V
VLS=5 V
(Note 6) power-down state (all supplies)
Power Dissipation (Note 4)VA = 5 V, VD = 2.5 V
normal operation
(Note 6) power-down
Package Thermal Resistanceθ
Power Supply Rejection Ratio (Note 7) (1 kHz)
PSRR-
(60 Hz)
I
A
I
D
I
LC
I
LS
I
pd
-
-
-
-
-
-
-
JA
θ
JC
-
-
75
20
2
84
200
426
1
48
15
60
-
40
83
26
-
-
-
482
-
-
-
-
-
mA
mA
µA
µA
µA
mW
mW
°C/Watt
°C/Watt
dB
dB
Notes:
3. V
is tested under load RL and includes attenuation due to Z
FS
OUT
4. Current consumption incr eases with increasing FS within a given speed mode and is signal dependant.
Max values are based on highest FS and highest MCLK.
5. I
6. Power down mode is defined as RST
measured with no external loading on the SDA pin.
LC
pin = Low with all clock and data lines held static.
7. Valid with the recommended capacitor values on FILT+ and VQ as shown in Figures 5 and 6.
10DS618PP1
CS4382A
COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE
The filter characteristics have been normalized to the sample rate (Fs) and can be referenced to the desired sample rate by multiplying the given characteristic by Fs.
(See note 12.)
Parameter
Combined Digital and On-chip Analog Filter Response - Single-Speed Mode - 48 kHz
Passband (Note 9)to -0.01 dB corner
Frequency Response 10 Hz to 20 kHz-0.01-+0.01dB
Combined Digital and On-chip Analog Filter Response - Double-Speed Mode - 96 kHz
Passband (Note 9)to -0.01 dB corner
Frequency Response 10 Hz to 20 kHz-0.01-+0.01dB
StopBand.583--Fs
StopBand Attenuation(Note 10)80--dB
Group Delay-6.15/Fs-s
Combined Digital and On-chip Analog Filter Response - Quad-Speed Mode - 192 kHz
Passband (Note 9) to -0.01 dB corner
Frequency Response 10 Hz to 20 kHz-0.01-+0.01dB
StopBand.635--Fs
StopBand Attenuation(Note 10)90--dB
Group Delay-7.1/Fs-s
to -3 dB corner
Fs = 48 kHz
to -3 dB corner
to -3 dB corner
0
0
-
-
-
0
0
0
0
Fast Roll-Off
-
-
-
-
-
-
-
-
-
.454
.499
±0.23
±0.14
±0.09
.430
.499
.105
.490
UnitMin Typ Max
Fs
Fs
dB
dB
dB
Fs
Fs
Fs
Fs
Notes:
8. Slow Roll-off interpolation filter is only available in software mode.
9. Response is clock dependent and will scale with Fs.
10. For Single-Speed Mode, the Measurement Bandwidth is from stopband to 3 Fs.
For Double-Speed Mode, the Measurement Bandwidth is from stopband to 3 Fs.
For Quad-Speed Mode, the Measurement Bandwidth is from stopband to 1.34 Fs.
11. De-emphasis is available only in Single-Speed Mode; Only 44.1 kHz De-emphasis is available in hardware mode.
12. Amplitude vs. Frequency plots of this data are available starting on page 43.
DS618PP111
CS4382A
COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE
(CONTINED)
Slow Roll-Off (Note 8)
Parameter
Single-Speed Mode - 48 kHz
Passband (Note 9)to -0.01 dB corner
to -3 dB corner
Frequency Response 10 Hz to 20 kHz-0.01-+0.01dB
StopBand.583--Fs
StopBand Attenuation(Note 10)64--dB
Group Delay -7.8/Fs-s
De-emphasis Error (Note 11)Fs = 32 kHz
(Relative to 1 kHz)Fs = 44.1 kHz
Fs = 48 kHz
Double-Speed Mode - 96 kHz
Passband (Note 9)to -0.01 dB corner
to -3 dB corner
Frequency Response 10 Hz to 20 kHz-0.01-+0.01dB
StopBand.792--Fs
StopBand Attenuation(Note 10)70--dB
Group Delay-5.4/Fs-s
Quad-Speed Mode - 192 kHz
Passband (Note 9) to -0.01 dB corner
to -3 dB corner
Frequency Response 10 Hz to 20 kHz-0.01-+0.01dB
StopBand.868--Fs
StopBand Attenuation(Note 10)75--dB
Group Delay-6.6/Fs-s
0
0
-
-
-
0
0
0
0
-
-
-
-
-
-
-
-
-
0.417
0.499
±0.36
±0.21
±0.14
.296
.499
.104
.481
UnitMinTypMax
Fs
Fs
dB
dB
dB
Fs
Fs
Fs
Fs
DSD COMBINED DIGITAL & ON-CHIP ANALOG FILTER RESPONSE
ParameterMinTypMaxUnit
DSD Processor mode
Passband (Note 9)to -3 dB corner0-50kHz
Frequency Response 10 Hz to 20 kHz-0.05-+0.05dB
Roll-off27--dB/Oct
Quad-Speed Mode
LRCK Duty Cycle4555%
SCLK Duty Cycle4555%
SCLK High Timet
SCLK Low Timet
LRCK Edge to SCLK Rising Edget
SDIN Setup Time Before SCLK Rising Edget
SDIN Hold Time After SCLK Rising Edget
Notes:
F
s
F
s
F
s
sckh
sckl
lcks
ds
dh
4
50
100
54
108
216
kHz
kHz
kHz
8-ns
8-ns
5-ns
3-ns
5-ns
14. After powering up, RST
should be held low until after the power supplies and clocks are settled.
15. See Table 1 on page 20 for suggested MCLK frequencies.
(128x Oversampled)
DSD_A / _B valid to DSD_SCLK rising setup timet
DSD_SCLK rising to DSD_A or DSD_B hold timet
DSD_SCLK
sclkl
sclkh
sdlrs
sdh
t
160--ns
160--ns
1.024
2.048
-
20--ns
20--ns
t
sclkh
sclkl
3.2
6.4
MHz
MHz
DSDxx
sdlrstsdh
Figure 2. Direct Stream Digital - Serial Audio Input Timing
t
DS618PP115
SWITCHING CHARACTERISTICS - CONTROL PORT - I2C FORMAT
(Inputs: Logic 0 = GND, Logic 1 = VLC, C
ParameterSymbolMinMaxUnit
SCL Clock Frequencyf
RST
Rising Edge to Startt
Bus Free Time Between Transmissionst
Start Condition Hold Time (prior to first clock pulse)t
Clock Low timet
Clock High Timet
Setup Time for Repeated Start Conditiont
SDA Hold Time from SCL Falling
(Note 16)
SDA Setup time to SCL Risingt
Rise Time of SCL and SDAt
Fall Time SCL and SDAt
Setup Time for Stop Conditiont
Acknowledge Delay from SCL Falling t
=30pF)
L
scl
buf
hdst
low
high
sust
t
hdd
sud
rc
fc
susp
ack
irs
, t
, t
-100kHz
500-ns
4.7-µs
4.0-µs
4.7-µs
4.0-µs
4.7-µs
0-µs
250-ns
rc
fc
-1µs
-300ns
4.7-µs
3001000ns
CS4382A
Notes:
16. Data must be held for sufficient time to bridge the transition time, t
RST
t
irs
StopStart
SDA
SCL
t
buf
t
hdst
t
low
t
Figure 3. Control Port Timing - I2C Format
hdd
t
high
t
sud
Repeated
Start
t
sust
, of SCL.
fc
t
hdst
Stop
t
f
t
r
t
susp
16DS618PP1
CS4382A
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI™ FORMAT
(Inputs: Logic 0 = GND, Logic 1 = VLC, CL=30pF)
ParameterSymbolMinMaxUnit
CCLK Clock Frequencyf
RST
Rising Edge to CS Fallingt
CCLK Edge to CS
Falling
(Note 17)
CS
High Time Between Transmissionst
CS
Falling to CCLK Edget
CCLK Low Timet
CCLK High Timet
CDIN to CCLK Rising Setup Timet
CCLK Rising to DATA Hold Time
(Note 18)
Rise Time of CCLK and CDIN
(Note 19)
Fall Time of CCLK and CDIN
(Note 19)
sclk
srs
t
spi
csh
css
scl
sch
dsu
t
dh
t
r2
t
f2
-6MHz
500-ns
500-ns
1.0-µs
20-ns
66-ns
66-ns
40-ns
15-ns
-100ns
-100ns
Notes:
17. t
only needed before first falling edge of CS after RST rising edge. t
spi
18. Data must be held for sufficient time to bridge the transition time of CCLK.
The CS4382A serially accepts twos complement formatted PCM data at standard aud io sample ra tes inclu ding 48 ,
44.1 and 32 kHz in SSM, 96, 88.2 and 64 kHz in DSM, and 192, 176.4 and 128 kHz in QSM. Audio data is input via
the serial data input pins (SDINx). The Left/Right Clock (LRCK) determines which channel is currently being input
on SDINx, and the Serial Clock (SCLK) clocks audio data into the input data buffer.
The CS4382A can be configured in hardware mode by the M0, M1, M2 , M3 and DSD_EN pins and in software
mode through I
3.1Master Clock
MCLK/LRCK must be an integer ratio as shown in Table 1. The LRCK frequency is equal to Fs, the frequency at which words for each channel are input to the device. The MCLK-to-LRCK frequency ratio is detected
automatically during the initialization sequence by co unting the num ber of MCLK tr ansitions during a single
LRCK period. Internal dividers are then set to generate the proper internal clocks. Table 1 illustrates several
standard audio sample rates and the required MCLK and LRCK frequencies. Please note there is no required phase relationship, but MCLK, LRCK and SCLK must be synchronous.
Speed Mode
(sample-rate range)
Single-Speed
(4 to 50 kHz)
Double-Speed
(50 to 100 kHz)
Quad-Speed
(100 to 200 kHz)
Note: These modes are only available in software mode by setting the MCLKDIV bit = 1.
In hardware mode operation is determined by the Mode Select pins. The state of these pins are continually
scanned for any changes. These pins require connection to supply or ground as outlined in figure 6. For
M0, M1, M2 supply is VLC and for M3 and DSD_EN supply is VLS. Tables 2 - 4 show the decode of these
pins.
In software mode the operational mode and data format are set in the FM and DIF registers. “Parameter
Definitions” on page 41.
20DS618PP1
M1
(DIF1)
M0
(DIF0)
00
01
10
11
DESCRIPTIONFORMATFIGURE
Left Justified, up to 24-bit data
2
I
S, up to 24-bit data
Right Justified, 16-bit Data
Right Justified, 24-bit Data
T able 2. Digital Interface Format, Stand-Alone Mode Options
CS4382A
033
134
235
336
M3M2
(DEM)
00
01
10
11
DSD_EN
M2M1M0DESCRIPTION
Single-Speed without De-Emp hasis (4 to 50 kHz sample rates)
Single-Speed with 44.1 kHz De-Emphasis; see Figure 13
Double-Speed (50 to 100 kHz sample rates)
Quad-Speed (100 to 200 kHz sample rates)
Table 3. Mode Selection, Stand-Alone Mode Options
(LRCK)
1000
1001
1010
1011
1100
1101
1110
1111
Table 4. Direct Stream Digital (DSD), Stand-Alone Mode Options
DESCRIPTION
64x oversampled DSD data with a 4x MCLK to DSD data rate
64x oversampled DSD data with a 6x MCLK to DSD data rate
64x oversampled DSD data with a 8x MCLK to DSD data rate
64x oversampled DSD data with a 12x MCLK to DSD data rate
128x oversampled DSD data with a 2x MCLK to DSD data rate
128x oversampled DSD data with a 3x MCLK to DSD data rate
128x oversampled DSD data with a 4x MCLK to DSD data rate
128x oversampled DSD data with a 6x MCLK to DSD data rate
DS618PP121
3.3Digital Interface Formats
The serial port operates as a slave and supports the I²S, Left-Justified, and Right-Justified digital interface
formats with varying bit depths from 16 to 24 as shown in Figures 7-12. Data is clocked into the DAC on the
rising edge.
CS4382A
LRCK
SCLK
SDINx+3 +2 +1+5 +4
LRCK
SCLK
SDINx+3 +2 +1+5 +4
LRCK
SCLK
SDINx
MSBLSBMSBLSB
-1 -2 -3 -4 -5
MSB
-2 -3 -4 -5
-1
15 14 13 12 11 10
Left Channel
Left Channel
Left Channel
-2 -3 -4
-1
Figure 7. Format 0 - Left-Justified up to 24-bit Data
LSBLSB
MSB
-1
-2 -3 -4
Figure 8. Format 1 - I2S up to 24-bit Data
Right Channel
6543210987
15 14 13 12 11 10
Right Channel
+3 +2 +1+5 +4
Right Channel
+3 +2 +1+5 +4
6543210987
32 clocks
Figure 9. Format 2 - Right-Justified 16-bit Data
LRCK
SCLK
SDINx
Left Channel
0
23 22 21 20 19 18
32 clocks
65432107
23 22 21 20 19 18
Right Channel
65432107
Figure 10. Format 3 - Right-Justified 24-bit Data
22DS618PP1
CS4382A
LRCK
SCLK
SDINx
LRCK
SCLK
SDINx
10
10
Left Channel
17 1617 16
19 1819 18
15 14 13 12 11 10
32 clocks
6543210987
Figure 11. Format 4 - Right-Justified 20-bit Data
Left Channel
17 1617 16
15 14 13 12 11 10
32 clocks
6543210987
Figure 12. Format 5 - Right-Justified 18-bit Data
Right Channel
15 14 13 12 11 10
Right Channel
15 14 13 12 11 10
6543210987
6543210987
3.4Oversampling Modes
The CS4382A operates in one of three oversampling modes based on the input sample rate. Mode selection
is determined by the DSD_EN, M3 and M2 pins in hardware mode or th e FM bits in software mode. SingleSpeed mode supports input sample rates up to 5 0 kHz and uses a 128 x oversampling ratio. Double-Speed
mode supports input sample rates up to 100 kHz and uses an oversampling ratio of 64x. Quad-speed mode
supports input sample rates up to 200 kHz and uses an oversampling ratio of 32x.
3.5Interpolation Filter
To accommodate the increasingly complex requirements of digital audio systems, the CS4382A incorporates selectable interpolation filters for each mode of oper ation. A “fast” and a “slow” roll-off filter is available
in each of Single, Double, and Quad-Speed modes. These filters have been designed to accommodate a
variety of musical tastes and styles. The FILT_SEL bit is used to select which filter is used (see the “Parameter Definitions” on page 41 for more details).
When in hardware mode, only the “fast” roll-off filter is available.
Filter specifications can be found in Section 2, and filter response plots can be found in Figures 19 to42.
3.6De-Emphasis
The CS4382A includes on-chip digital de-emphasis filters. The de-emphasis feature is included to accommodate older audio recordings that utilize pre-emphasis equalization as a means of noise reduction. Figure
13 shows the de-emphasis curve. The frequency response of the de-emphasis curve will scale proportionally with changes in sample rate, Fs if the input sample rate does not match the coefficient which has been
selected.
DS618PP123
CS4382A
In software mode the required de-emphasis filter coefficients for 32 kHz, 44. 1 kHz, or 48 kH z are selected
via the de-emphasis control bits.
In hardware mode only the 44.1 kHz coefficient is available (enabled through the M2 pin). If the input sample rate is not 44.1 kHz and de-emphasis has been selected then the corner frequencies of the de-emphasis
filter will be scaled by a factor of the actual Fs over 44,100.
Gain
dB
T1=50 µs
0dB
T2 = 15 µs
-10dB
3.7ATAPI Specification
The CS4382A implements the channel mixing functions of the ATAPI CD-ROM specification. The
ATAPI functions are applied per A-B pair. Refer to Table 7 on page 38 and Figure 14 for additional information.
In stand-alone mode, DSD operation is selected by holding DSD_EN(LRCK) high and applying the DSD
data and clocks to the appropriate pins. The M[2:0] pins set the expected DSD rate and MCLK ratio.
In control-port mode the FM bits set the device into DSD mode (DSD_EN pin is not required to be held high).
The DIF register then controls the expected DSD rate and MCLK ratio.
During DSD operation, the PCM related pins should either be tied low or remain active with clocks (except
LRCK in Stand-alone mode). When the DSD related pins are not being used they should either be tied static
low, or remain active with clocks (except M3 in Stand-alone mode).
3.9Grounding and Power Supply Arrangements
As with any high resolution converter, the CS4382A r equire s care ful atten tion to po wer supply and grou nding arrangements if its potential performance is to be realized. The Typical Connection Diagr am sh ows th e
recommended power arrangements, with VA, VD, VLC, and VLS connected to clean supp lies. If the ground
planes are split between digital ground and analog ground, the GND pins of the CS4382A should be connected to the analog ground plane.
All signals, especially clocks, should be kept away from the FILT+ and VQ pins in order to avoid unwanted
coupling into the DAC.
3.9.1Capacitor Placement
CS4382A
Decoupling capacitors should be place d as close to the DAC as possible, with the low value ceramic capacitor being the closest. To further minimize impedance, these capacitors should be located on the same
layer as the DAC. If desired, all supply pins with similar volta ge ratings may be connected to the same supply, but a decoupling capacitor should still be placed on each supply pin.
Notes: All decoupling capacitors should be referenced to analog ground.
The CDB4382A evaluation board demons tr at es the op tim u m lay ou t an d po we r su pp ly arr ang em e nt s .
3.10Analog Output and Filtering
The application note “Design Note s for a 2-Pole Filter with Differential Input” discusses the second-order
Butterworth filter and differential to single-ended converter which was implemented on the CS4382A evaluation board, CDB4382A, as seen in Figure 16. The CS4382A does not include phase or amplitude compensation for an external filter. Therefore, the DAC system phase and am plitude response will be dependent
on the external analog circuitry. The off-chip filter has been desig ned to attenuate th e typical full-scale ou tput level to below 2 Vrms.
Figure 15 shows how the full-scale differential analog output level specification is derived.
The Mute Control pins go active during power-up initialization, reset, muting, or if the MCLK to LRCK ratio
is incorrect. These pins are intended to be used as control for external mute circuits to prevent the clicks
and pops that can occur in any single-ended single supply system.
Use of the Mute Control function is not mandatory but recommended for designs requiring the absolute minimum in extraneous clicks and pops. Also, use of the Mute Control function can enable the system designer
to achieve idle channel noise/signal-to-noise ratios which are only limited by the external mute circuit.
Please see the CDB4382A data sheet for a suggested mute circuit.
26DS618PP1
3.12Recommended Power-Up Sequence
3.12.1Hardware Mode
1. Hold RST low until the power supplies and configuration pins are stable, and the master and left/right
clocks are locked to the appropriate frequencies, as discussed in section 3.1. In this state, the registers
are reset to the default settings, FILT+ will remain low, and VQ will be connected to VA/2.
If RST
are stable, and if possible the RST
can not be held low long enough the SDINx pins should remain static low until all other clocks
should be toggled low again once the system is stable.
CS4382A
2. Bring RST
Hardware power-up sequence after approximately 512 LRCK cycles in Single-Speed Mode (1024
LRCK cycles in Double-Speed Mode, and 2048 LRCK cycles in Quad-Speed Mode).
high. The device will remain in a low power state with FILT+ low and will initiate the
3.12.2Software Mode
1. Hold RST low until the power supply is stable, and the master and left/right clocks are locked to the
appropriate frequencies, as discussed in section 3.1. In this state, the registers are reset to the default
settings, FILT+ will remain low, and VQ will be connected to VA/2.
2. Bring RST
Single-Speed Mode (1024 LRCK cycles in Double-Speed Mode, and 2048 LRCK cycles in QuadSpeed Mode).
3. In order to reduce the chances of clicks and pops, perform a write to the CP_EN bit prior to the
completion of approximately 512 LRCK cycles in Single-Speed Mode (1024 LRCK cycles in DoubleSpeed Mode, and 2048 LRCK cycles in Quad-Speed Mode). The desired register settings can be
loaded while keeping the PDN bit set to 1. Set the RMP_UP and RMP_DN bits to 1, then set the format
and mode control bits to the desired settings.
If more than the stated number of LRCK cycles passes before CPEN bit is written then the chip will
enter Hardware mode and begin to operate with the M0-M3 as the mode settings. CPEN bit may be
written at anytime, even after the Hardware sequence has begun. It is advised that if the CPEN bit can
not be set in time then the SDINx pins should remain static low (this way no audio data can be
converted incorrectly by the hardware mode settings).
high. The device will remain in a low power state with FILT+ low for 512 LRCK cycles in
4. Set the PDN bit to 0. This will initiate the power-up sequence, which lasts approximately 50 µs.
3.13Recommended Procedure for Switching Operational Modes
For systems where the absolute minimum in clicks and pops is required, it is recommended that the MUTE
bits are set prior to changing significant DAC functions (such as changing sample rates or clock sources).
The mute bits may then be released after clocks have settled and the proper modes have been set.
It is required to have the de vice held in reset if the minimum high/low time specs of MCLK can not be met
during clock source changes.
DS618PP127
3.14Control Port Interface
The control port is used to load all the internal register settings in order to operate in software mode (see
the “Parameter Definitions” on page 41). The operation of the control port may be complete ly asynchronous
with the audio sample rate. However, to avoid potential interference problems, the control port pins should
remain static if no operation is required.
The control port operates in one of two modes: I
3.14.1MAP Auto Increment
2
C or SPI.
CS4382A
The device has MAP (memory address pointer) auto increment capability enabled by the INCR bit (also the
MSB) of the MAP. If INCR is set to 0, MAP will stay constant for successive I
writes. If INCR is set to 1, MAP will auto increment after each byte is written, allowing block reads or writes
of successive registers.
3.14.2I2C Mode
In the I2C mode, data is clocked into and out of the bi-directional serial control data line, SDA, by the serial
control port clock, SCL (see Figure 17 for the clock to data relationship). There is no CS
ables the user to alter the chip address (001100[AD0][R/W
before powering up the device. If the device ever detects a high to low transition on the AD0/CS
power-up, SPI mode will be selected.
3.14.2.1I2C Write
To write to the device, follow the procedure belo w while ad her ing to the co ntro l port Switc hing Spec ifications in section 2.
1. Initiate a START condition to the I
001100. The seventh bit must match the setting of the AD0 pin, and the eighth must be 0. The eighth
bit of the address byte is the R/W
2. Wait for an acknowledge (ACK) from the part, then write to th e memory address pointer, M AP. This
byte points to the register to be written.
3. Wait for an acknowledge (ACK) from the part, then write the desired data to the register pointed to
by the MAP.
4. If the INCR bit (see section 3.14.1) is set to 1, repeat the previous step until all the desired registers
are written, then initiate a STOP condition to the bus.
5. If the INCR bit is set to 0 and further I
tiate a repeated START condition and follow the procedure detailed from step 1. If no further writes to
other registers are desired, initiate a STOP condition to the bus.
2
C writes or reads and SPI
pin. Pin AD0 en-
]) and should be tied to VLC or GND as required ,
2
C bus followed by the address byte. The upper 6 bits must be
bit.
2
C writes to other registers are desired, it is necessary to ini-
pin after
28DS618PP1
CS4382A
3.14.2.2I2C Read
To read from the device, follow the procedure below while adhering to th e control port Switching Specifications.
1. Initiate a START condition to the I
001100. The seventh bit must match the setting of the AD0 pin, and the eighth must be 1. The eighth
bit of the address byte is the R/W
2. After transmitting an acknowledge (ACK), the device will then transmit the contents of the register
pointed to by the MAP. The MAP register will contain the address of the last register written to the MAP,
or the default address (see section 3.14.1) if an I
3. Once the device has transmitted the contents of the register pointed to by the MAP, issu e an ACK.
4. If the INCR bit is set to 1, the device will continue to transmit the contents of successive registers.
Continue providing a clock and issue an ACK after each byte until all the desired registers are read, then
initiate a STOP condition to the bus.
5. If the INCR bit is set to 0 and further I
initiate a repeated START condition and follow the procedure detailed from steps 1 and 2 from the I
Write instructions followed by step 1 of the I
desired, initiate a STOP condition to the bus.
SDA
001100
ADDR
AD0
2
C bus followed by the address byte. The upper 6 bits must be
bit.
2
C read is the first operation performed on the device.
2
C reads from other registers are desired, it is necessary to
2
C Read section. If no further reads from other registers are
Note 1
R/W
ACK
DATA
1-8
ACK
DATA
1-8
ACK
2
C
SCL
Start
Note: If operation is a write, this byte contains the M emo ry A ddress Pointer, M AP.
Figure 17. Control Port Timing, I2C Mode
Stop
DS618PP129
3.14.3SPI™ Mode
In SPI mode, data is clocked into the serial control data line, CDIN, by the serial control port clock, CCLK
(see Figure 18 for the clock to data relationship). There is no AD0 pin. Pin CS
is used to control SPI writes to th e control port. When the devi ce detects a high to low transition on the
AD0/CS
pin after power-up, SPI mode will be selected. All signals are inputs and data is clocked in on the
rising edge of CCLK.
3.14.3.1SPI Write
To write to the device, follow the procedure belo w while ad her ing to the co ntro l port Switc hing Spec ifications in Section 2.
1. Bring CS
2. The address byte on the CDIN pin must then be 00110000.
3. Write to the memory address pointer, MAP. This byte points to the register to be written.
4. Write the desired data to the register pointed to by the MAP.
5. If the INCR bit (see section 3.14.1) is set to 1, repeat the previous step until all the desired registers
are written, then bring CS
6. If the INCR bit is set to 0 and further SPI writes to other registers are desired, it is necessary to bring
CS
high, and follow the procedure detailed from step 1. If no further writes to other registers are desired,
bring CS
high.
CS4382A
is the chip select signal and
low.
high.
CS
CCLK
CDIN
CHIP
ADDRESS
0011000
MAP = Mem ory Address Pointer
Figure 18. Control Port Timing, SPI mode
R/W
MAP
MSB
byte 1
DATA
LSB
byte n
3.15 Memory Address Pointer (MAP)
76543210
INCRReservedReservedMAP4MAP3MAP2MAP1MAP0
00000000
3.15.1 INCR (AUTO MAP INCREMENT ENABLE)
Default = ‘0’
0 - Disabled
1 - Enabled
3.15.2 MAP4-0 (MEMORY ADDRESS POINTER)
Default = ‘00000’
30DS618PP1
CS4382A
4. REGISTER QUICK REFERENCE
AddrFunction76543210
01h Mode Control 1CPENFREEZEMCLKDIV DAC4_DIS DAC3_DIS DAC2_DIS DAC1_DISPDN
default
02h Mode Control 2ReservedDIF2DIF1DIF0ReservedReservedReservedReserved
default
03h Mode Control 3SZC1SZC0SNGLVOL RMP_UP MUTEC+/-AMUTEReservedMUTEC
Function:
This bit defaults to 0, allowing the device to power-up in Stand-Alone mode. The Control port mode can be
accessed by setting this bit to 1. This will allow the operation of the device to be controlled by the registers
and the pin definitions will conform to Control Port Mode. To accomplish a clean power-up, the user should
write this bit within 10 ms following the release of Reset.
5.1.2Freeze Controls (Freeze)
Default = 0
0 - Disabled
1 - Enabled
Function:
This function allows modifications to be made to the registers without the changes taking effect until the
FREEZE is disabled. To make multiple changes in the Control port registers take effect simultaneously, e nable the FREEZE Bit, make all register changes, then Disable the FREEZE bit.
5.1.3Master Clock DIVIDE ENABLE (mclkdiv)
Default = 0
0 - Disabled
1 - Enabled
Function:
The MCLKDIV bit enables a circuit which div ide s th e e xternally applied MCLK signal by 2 prior to all other
internal circuitry.
5.1.4DAC Pair Disable (DACx_DIS)
Default = 0
0 - Enabled
1 - Disabled
Function:
When enabled the respective DAC channel pairx (AOUTAx and AOUTBx) will remain in a reset state. It is
advised that changes to these bits be made while the power down bit is enabled to eliminate the possibility
of audible artifacts.
32DS618PP1
CS4382A
5.1.5Power Down (PDN)
Default = 1
0 - Disabled
1 - Enabled
Function:
The entire device will enter a low-power state when this function is enabled, and the contents of the control
registers are retained in this mode. The power- down bit defaults to ‘enable d’ on power-up and must be di sabled before normal operation in Control Port mode can occur.
Default = 000 - Format 0 (Left Justified, up to 24-bit data)
Function:
These bits select the interface format for the serial audio input. The Functional Mode bits de termine wheth-
er PCM or DSD mode is selected.
PCM Mode: The required relationship betw ee n th e Le ft/Right clock, serial clock and s eri al da ta is de fin ed
by the Digital Interface Format and the options are detailed in Figures 7-12.
DIF2DIF1DIF0DESCRIPTIONFormatFIGURE
000
001
010
011
100
101
110
111
Left Justified, up to 24-bit data
I2S, up to 24-bit data
Right Justified, 16-bit data
Right Justified, 24-bit data
Right Justified, 20-bit data
Right Justified, 18-bit data
Reserved
Reserved
Table 5. Digital Interface Formats - PCM Mode
07
18
29
310
411
512
-
-
DSD Mode: The relationship between the oversampling r atio of the DSD au dio dat a and the re quired Master clock to DSD data rate is defined by the Digital Interface Format pins.
DIF2DIF1DIFODESCRIPTION
00064x oversampled DSD data with a 4x MCLK to DSD data rate
00164x oversampled DSD data with a 6x MCLK to DSD data rate
01064x oversampled DSD data with a 8x MCLK to DSD data rate
01164x oversampled DSD data with a 12x MCLK to DSD data rate
100128x oversampled DSD data with a 2x MCLK to DSD data rate
101128x oversampled DSD data with a 3x MCLK to DSD data rate
110128x oversampled DSD data with a 4x MCLK to DSD data rate
111128x oversampled DSD data with a 6x MCLK to DSD data rate
Table 6. Digital Interface Formats - DSD Mode
DS618PP133
CS4382A
5.2.2Mode Control 3 (address 03h)
76543210
SZC1SZC0SNGLVOLRMP_UPMUTEC+/-AMUTEReservedMUTEC
10000100
5.2.3Soft Ramp AND Zero Cross CONTROL (SZC)
Default = 10
00 - Immediate Change
01 - Zero Cross
10 - Soft Ramp
11 - Soft Ramp on Zero Crossings
Function:
Immediate Change
When Immediate Change is selected all level changes will take effect immediately in one step.
Zero Cross
Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur
on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a timeout
period between 512 and 1024 sample periods (1 0.7 ms to 21.3 ms at 48 kHz sample rate ) if the signal does
not encounter a zero crossing. The zero cross function is independently monitored and implemented for
each channel.
Soft Ramp
Soft Ramp allows level changes, both muting and atte nuation, to be implemented by incrementally ramping,
in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods.
Soft Ramp on Zero Crossing
Soft Ramp and Zero Cross Enable dictates that signal level changes, either by attenuation changes or mut-
ing, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will
occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample
rate) if the signal does not encounter a zero crossing. The zero cross function is independently m onito red
and implemented for each channel.
5.2.4Single Volume Control (Snglvol)
Default = 0
0 - Disabled
1 - Enabled
Function:
The individual channel volume levels are independently controlled by their respective Volume Control Bytes
when this function is disabled. The volume on all channe ls is determined by the A1 Channel Volum e Control Byte, and the other Volume Control Bytes are ignored when this function is enabled.
34DS618PP1
CS4382A
5.2.5Soft Volume Ramp-Up after Error (RMP_UP)
Default = 0
0 - Disabled
1 - Enabled
Function:
An un-mute will be performed after a LRCK/MCLK ratio change or error, and after changing the Functional
Mode. When this feature is enabled, this un-mute is affected, similarly to attenuation changes, by the Soft
and Zero Cross bits in the Mode Control 3 register. When disable d, an immediate un-mute is performe d in
these instances.
Notes: For best results, it is recommended that this feature be used in conjunction with the RMP_DN bit.
5.2.6MUTEC Polarity (MUTEC+/-)
Default = 0
0 - Active High
1 - Active Low
Function:
The active polarity of the MUTEC pin(s) is determined by this register. When set to 0 (default) the MUTEC
pins are high when active. When set to 1 the MUTEC pin(s) are low when active.
Notes: When the on board mute circuitry is designed for active low, the MUTEC outputs will be high (un-muted)
for the period of time during reset and before this bit is enabled to 1.
5.2.7 Auto-Mute (AMUTE)
Default = 1
0 - Disabled
1 - Enabled
Function:
The Digital-to-Analog converter output will mute following the reception of 8192 consecutive audio samples
of static 0 or -1. A single sample of non-static data will release the mute. Detection and muting is done
independently for each channel. The quiescent voltage on the output will be retained and the Mute Control
pin will go active during the mute period. The muting function is affected, similar to volume control changes,
by the Soft and Zero Cross bits in the Mode Control 3 register.
5.3Mutec Pin Control (MUTEC)
Default = 0
0 - Two Mute control signals
1 - Single mute control signal on MUTEC1
Function:
Selects how the internal mute signals are routed to the MUTEC1 and MUTEC234 pins. When set to ‘0’, a
logical AND of DAC pair 1 mute control signals are output on MUTEC1 and a logical AND of the mu te control signals of DAC pairs 2, 3, and 4 are output on MUTEC234. When set to ‘1’, a logical AND of all DAC
pair mute control signals is output on the MUTEC1 pin, MUTEC234 will remain static. For more information
on the use of the mute control function see the MUTEC1 and MUTEC234 pins in section 8.
Function:
Selects the appropriate digital filter to maintain the stand ard 15 µs/50 µs digital de-emphasis filter response
at 32, 44.1 or 48 kHz sample rates. (see Figure 13)
De-emphasis is only available in Single Speed Mode.
5.4.3Soft Ramp-Down before Filter Mode Change (RMP_DN)
Default = 0
0 - Disabled
1 - Enabled
Function:
If either the FILT_SEL or DEM bits are changed the DAC will stop conversion for a period of time to change
filter values. This bit selects how the data is effected prior to and after the change of the filter values. When
this bit is enabled the DAC will ramp down the volume prior to a filter mode change and ramp from mute to
the original volume value after a filter mode change according to the settings of the Soft and Zero Cross
bits in the Mode Control 3 register. When disabled, an immediate mute and unmute is performed.
Loss of clocks or a change in the FM bits will always cause an immediate mute; Unmute in these conditions
is affected by the RMP_UP bit.
Notes: For best results, it is recommended that this feature be used in conjunction with the RMP_UP bit.
36DS618PP1
CS4382A
5.5Invert Control (address 05h)
76543210
INV_B4INV_A4INV_B3INV_A3INV_B2INV_A2INV_B1INV_A1
00000000
5.5.1Invert Signal Polarity (Inv_Xx)
Default = 0
0 - Disabled
1 - Enabled
Function:
When enabled, these bits will invert the signal polarity of their respective channels.
5.6Mixing Control Pair 1 (Channels A1 & B1)(address 06h)
Mixing Control Pair 2 (Channels A2 & B2)(address 09h)
Mixing Control Pair 3 (Channels A3 & B3)(address 0Ch)
Mixing Control Pair 4 (Channels A4 & B4)(address 0Fh)
Function:
The AOUTAx and AOUTBx volume levels are independently controlled by the A and the B Channel Volume
Control Bytes when this function is disabled. The volume on both AOUTAx and AOUTBx are determined
by the A Channel Attenuation and Volume Control Bytes (per A-B pair), and the B Channel Bytes are ignored when this function is enabled.
5.6.2ATAPI Channel Mixing and Muting (ATAPI)
Default = 01001 - AOUTAx=aL, AOUTBx=bR (Stereo)
Function:
The
CS4382A implements the channel mixing functions of the ATAPI CD-ROM specification. The ATAPI
functions are applied per A-B pair. Refer to Table 7 and Figure 14 for additional information.
00 - Single-Speed Mode (4 to 50 kHz sample rates)
01 - Double-Speed Mode (50 to 100 kHz sample rates)
10 - Quad-Speed Mode (100 to 200 kHz sample rates)
11 - Direct Stream Digital Mode
Function:
Selects the required range of input sample rates or DSD Mode. All DAC pairs are required to be set to the
same functional mode setting before a speed mode ch ang e is accepte d. When DSD mode is se lected for
any channel pair then all pairs will switch to DSD mode.
38DS618PP1
CS4382A
5.7 Volume Control (addresses 07h, 08h, 0Ah, 0Bh, 0Dh, 0Eh)
Note: These eight registers provide individual volume and mute control for each of the eight channels.
The values for “xx” in the bit fields above are as follows:
Register address 07h - xx = A1
Register address 08h - xx = B1
Register address 0Ah - xx = A2
Register address 0Bh - xx = B2
Register address 0Dh - xx = A3
Register address 0Eh - xx = B3
Register address 10h - xx = A4
Register address 11h - xx = B4
5.7.1Mute (MUTE)
Default = 0
0 - Disabled
1 - Enabled
Function:
The Digital-to-Analog converter output will mute when enabled. The quiescent voltage on the output will be
retained. The muting function is affected, similarly to attenuation changes, by the Soft and Zero Cro ss bits.
The MUTE pins will go active during the mute period according to the MUTEC bit.
5.7.2Volume Control (xx_VOL)
Default = 0 (No attenuation)
Function:
The Digital Volume Control registers allow independent control of the signal levels in 1 dB increments from
0 to -127 dB. Volume settings are decoded as shown in Table 8. The volume changes are implemented
as dictated by the Soft and Zero Cross bits. All volume settings less than -127 dB are equivalent to enabling
the MUTE bit.
Binary CodeDecimal ValueVolume Setting
0 0 0 0 0 0 000 dB
0 0 1 0 1 0 020-20 dB
0 1 0 1 0 0 040-40 dB
0 1 1 1 1 0 060-60 dB
1 0 1 1 0 1 090-90 dB
Table 8. Example Digital Volume Settings
DS618PP139
CS4382A
5.8Chip Revision (address 12h)
76543210
PART4PART3PART2PART1PART0ReservedReservedReserved
01110000
5.8.1Part Number ID (part) [Read Only]
01110 - CS4382A
000 - Revision A
Function:
This read-only register can be used to identify the model and revision number of the device.
40DS618PP1
6. PARAMETER DEFINITIONS
Total Harmonic Distortion + Noise (THD+N)
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels.
Dynamic Range
The ratio of the full scale rms value of the signal to the rms sum of all other spe ctral components over the
specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth
made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full scale. This technique ensures that the dis tor tio n comp o ne n ts ar e be low the no ise level and
do not affect the measurement. This measurement technique has been accepted by the Audio Eng ineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307.
Interchannel Isolation
A measure of crosstalk between the left and right ch annels. Measured for each channel at the con verter's
output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in
decibels.
Interchannel Gain Mismatch
The gain difference between left and right channels. Units in decibels.
CS4382A
Gain Error
The deviation from the nominal full scale analog output for a full scale digital input.
Gain Drift
The change in gain value with temperature. Units in ppm/°C.
7. REFERENCES
Note: "How to Achieve Optimum Performance from Delta-Sigma A/D & D/A Converters" by Steven Harris. Paper
presented at the 93rd Convention of the Audio Engineering Society, October 1992.
Note: CDB4382A Datasheet
Note: “Design Notes for a 2-Pole Filter with Differential Input” by Steven Green. Cirrus Logic Application Note AN48
Note: “The I
2
C-Bus Specification: Version 2.0” Philips Semiconductors, December 1998.
http://www.semiconductors.philips.com
8. ORDERING INFORMATION
ProductDescriptionPackagePb-FreeGradeTemp RangeContainer Order #
CS4382A
CDB4382A CS4382A Evaluation Board ----CDB4382A
114 dB, 192 kHz 8-
channel D/A Converter
48-pin
LQFP
YES
Commercial -10° to +70° C
Automotive -40° to +105° C
TrayCS4382A-CQZ
Tape & Reel CS4382A-CQZR
TrayCS4382A-EQZ
Tape & Reel CS4382A-EQZR
DS618PP141
9. PACKAGE DIMENSIONS
48L LQFP PACKAGE DRAWING
D1
D
CS4382A
E
E1
1
e
∝
B
A
A1
L
INCHESMILLIMETERS
DIMMINNOMMAXMINNOMMAX
A---0.0550.063---1.401.60
A10.0020.0040.0060.050.100.15
B0.0070.0090.0110.170.220.27
D0.3430.3540.3668.709.0 BSC9.30
D10.2720.280.2806.907.0 BSC7.10
E0.3430.3540.3668.709.0 BSC9.30
E10.2720.280.2806.907.0 BSC7.10
e*0.0160.0200.0240.400.50 BSC0.60
L0.0180.240.0300.450.600.75
∝
* Nominal pin pitch is 0.50 mm
0.000°4°7.000°0.00°4°7.00°
Controlling dimension is mm.
JEDEC Designation: MS022
PP1APR 2005Updated output impedance spec on page 10
Improved interchannel isolation spec on page 10
Updated Legal text
Re-formatted ordering information
CS4382A
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find the one nearest to you go to www.cirrus.com
IMPORTANT NOTICE
"Preliminary" pro duct i nformati on desc ribes product s that are in product ion, bu t for which ful l char acter izati on data i s not yet available. Cirrus Logic, Inc. and its
subsidiaries ("Cirrus") believe that the info rmation containe d in this do cumen t is accurate a nd relia ble. Howe ver, the infor mation is subject to change without notice
and is provided "AS IS" without warr anty of any kin d (express or implied ). Customers a re advised to obtain the latest version o f relevant in formation to verify, be fore
placing orders, that information being relied on is current and complete. All prod ucts are sold subject to the terms and con ditions of sale supplied at the time of orde r
acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document
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CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESI GNED, AUTHORIZED OR WARRANTED FOR
USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY
DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PU RPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT
IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL
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OTHER AGENTS FROM ANY AND ALL LIABILITY, IN CLUDING ATT ORNEYS' F EES AND COSTS, T HAT MAY RESULT FROM OR ARISE IN CONNECTION
WITH THESE USES.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks
or service marks of their respective owners.
SPI is a trademark of Motorola, Inc.
DS618PP147
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