Cirrus Logic CS4329-KS, CS4329-KP, CS4329 Datasheet

CS4329

20-Bit, Stereo D/A Converter for Digital Audio

Features

20-Bit Conversion

115 dB Signal-to-Noise-Ratio (EIAJ)

Complete Stereo DAC System

- 128X Interpolation Filter

- Delta-Sigma DAC

- Analog Post Filter

106 dB Dynamic Range

Low Clock Jitter Sensitivity

Filtered Line-Level Outputs

- Linear Phase Filtering

- Zero Phase Error Between Channels

Adjustable System Sampling Rates

- including 32 kHz, 44.1 kHz & 48 kHz

Digital De-emphasis for 32 kHz, 44.1 kHz, & 48 kHz

Pin-compatible with the CS4390

Description

The CS4329 is a complete stereo digital-to-analog output system. In addit ion to the tr aditional D/A function, t he CS4329 includes a digital interpolation filter followed by an 128X oversampled delt a-sigma modulator. The modulator output controls the reference voltage input to an ultra-linear analog low-pass filter. This architecture allows for infin ite adjustment of sample rate between 1 and 50 kHz while maintaining linear phase response simply by changing the master clock frequency.

The CS4329 also includes an extremely flexible serial port utilizing mode select pins to support multiple interface formats.

The master clock can be either 256, 384, or 512 times the input sample rate, supporting various audio environments.

ORDERING INFORMATION

CS4329-KP -10° to 70° C 20-pin Plastic DIP CS4329-KS -10° to 70° C 20-pin Plastic SSOP CDB4329 Evaluation Board

DIF0

DIF1

DIF2

12 3 6

7 9

Serial Input

Interface

Interpolator

DGND

LRCK SCLK

SDATA

AUTO_MUTE

Cirrus Logic, Inc. Crystal Semiconductor Products Division

P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.crystal.com

DEM01DEM1

De-emphasis

Delta-Sigma

Modulator

Delta-Sigma

Modulator

MCLK

VA VD

Voltage Reference

DAC

AGND

Analog

Low-Pass

Filter

Analog

Low-Pass

Filter

MUTE_R

MUTE_L

AOUTL+

AOUTL-

AOUTR+

AOUTR-

APR ‘98

DS153F1

CS4329

ANALOG CHARACTERISTICS (T

48 kHz; Input Data = 20 Bits; SCLK = 3.072 MHz; MCLK = 12.288 MHz; R

= 25°C; Full-Scale Differential Output Sine wave, 997 Hz; Fs =

= 20 kΩ differential; VD = VA = 5 V;

Logic "1" = VD; Logic "0" = DGND; Measurement Bandwidth is 10 Hz to 20 kHz, unweighted unless otherwise specified.)

Parameter Symbol Min Typ Max Unit

Specified Temperature Operating Range T

-10 - 70 °C

Dynamic Performance

Dynamic Range 20-Bit (Note 1)

(A-Weighted)

18-Bit

(A-Weighted)

16-Bit

(A-Weighted)

Total Harmonic Distortion + Noise (Note 1)

20-Bit 0 dB

-20 dB

-60 dB

18-Bit 0 dB

-20 dB

-60 dB

16-Bit 0 dB

-20 dB

-60 dB

THD+N

101

-90

-78

-38

103 106 101 104

94 96

-97

-83

-43

-96

-81

-41

-93

-74

-34

dB dB dB dB dB dB

dB dB dB dB dB dB dB dB

dB Idle Channel Noise / Signal-to-Noise-Ratio (Note 2) - 115 - dBFS Interchannel Isolation (1 kHz) - -110 - dB

Combined Digital and Analog Filter Characteristics

Frequency Response 10 Hz to 20 kHz (Note 3) - ±0.1 - dB Deviation from linear phase - ±0.5 - deg Passband: to -0.1 dB corner (Note 3) 0 - 21.77 kHz Passband Ripple - - ±0.001 dB StopBand (Note 3) 26.23 - - kHz StopBand Attenuation (Note 3) 75 - - dB Group Delay (Note 4) - 25/Fs - s De-emphasis Error (referenced to 1 kHz) Fs = 32 kHz

Fs = 44.1 kHz

Fs = 48 kHz

+0.3/-0.3 +0.2/-0.4

+0.1/-0.45

dc Accuracy

Interchannel Gain Mismatch - 0.1 - dB Ga in E rror - ±2 ±5 % Gain Drift - 200 - ppm/°C

Power Supplies

Power Supply Current: Normal Operation

Power-down

Power Dissipation Normal Operation

Power-down

I I

IA+I

A D

30 12 42

500 185

2.5

22.5

mA mA mA

µA

mW mW

Power Supply Rejection Ratio (1 kHz) PSRR - 60 - dB

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CS4329

ANALOG CHARACTERISTICS (CONTINUED)

Parameter Symbol Min Typ Max Unit

Analog Output

Differential Full Scale Output Voltage (Note 5) 1.90 2.0 2.10 Vrms Output Common Mode Voltage - 2.2 - V Differentia l Offs et - 3 15 mV AC Load Resistance R Load Capacitance C

Notes: 1. Triangular PDF Dithered Data

2. AUTO-MUTE

active. See parameter definitions

3. The passband and stopband edges scale with frequency. For input sample rates, Fs, other than 48 kHz,

the passband edge is 0.4535×Fs and the stopband edge is 0.5465×Fs.

4. Group Delay for Fs=48 kHz 25/48 kHz=520µs

5. Specified for a fully differential output ±((AOUT+)-(AOUT-)). See Figure 12.

L L

4- -k

- - 100 pf

Ω

SWITCHING CHARACTERISTICS

to 4.75 Volts; C

=20pF)

(TA= -10 to 70°C; Logic 0 = AGND = DGND; Logic 1 = VD = VA = 5.25

Parameter Symbol Min Typ Max Unit

Input Sample Rate Fs 1 - 50 kHz MCLK Pulse Width High MCLK / LRCK = 512 10 - - ns MCLK Pulse Width Low MCLK / LRCK = 512 10 - - ns MCLK Pulse Width High MCLK / LRCK = 384 21 - - ns MCLK Pulse Width Low MCLK / LRCK = 384 21 - - ns MCLK Pulse Width High MCLK / LRCK = 256 31 - - ns MCLK Pulse Width Low MCLK / LRCK = 256 32 - - ns

External SCLK Mode

SCLK Pulse Width Low t SCLK Pulse Width High t SCLK Period t

SCLK rising to LRCK edge delay t SCLK rising to LRCK edge setup time t SDATA valid to SCLK rising setup time t SCLK rising to SDATA hold time t

sclkl

sclkh

sclkw

slrd slrs

sdlrs

sdh

20 --ns 20 --ns

-------------------128 Fs()

--ns

20 --ns 20 --ns 20 --ns 20 --ns

Internal SCLK Mode

SCLK Period SCLK / LRCK = 64 t

SDATA valid to SCLK rising setup time t

SCLK rising to SDATA hold time MCLK / LRCK = 256 or 512 t

SCLK rising to SDATA hold time MCLK / LRCK = 384 t

sclkw

sdlrs

sdh

----------------64 Fs()

-------------------512 Fs()

-------------------384 Fs()

--ns

10+

15+

--ns

DS153F1 3

LRCK

SCLK

SDATA

slrs

slrd

sdlrs

External Serial Mode Input Timing

sclkl

sdh

sclkh

CS4329

LRCK

SDATA

*INTERNA L SCLK

* The SCLK pin must be terminated to ground. The SCLK pulses shown are internal to the CS4329.

sdlrstsdh

Internal Serial Mode Input Timing

sclkw

4 DS153F1

CS4329

DIGITAL CHARACTERISTICS (T

Parameter Symbol Min Typ Max Unit

High-Level Input Voltage V Low-Level Input Voltage V Input Leakage Current V Digital Input Capacitance - 10 - pF

= 25°C; VD = 5 V ±5%)

IH IL in

2.0 - - V

--0.8V

--±10.0

ABSOLUTE MAXIMUM RATINGS (AGND = 0 V, all voltages with respect to ground.)

Parameter Symbol Min Max Unit

DC Power Supply: Positive Analog

Positi ve D ig ital

|VA - VD| Input Current, Any Pin Except Supplies I Digital Input Voltage V Ambient Operating Temperature (power applied) T Storage Temperature T

WARNING: Operation at or beyond these limits may result in permanent damage to t he device.No rmal operat ion is not guaranteed at these extremes.

RECOMMENDED OPERATING CONDITIONS

VA VD

IND

stg

(DGND = 0V; all voltages with respect to ground)

-0.3

0.0

-±10mA

-0.3 (VD)+0.4 V

-55 125 °C

-65 150 °C

6.0

0.4

V V V

Parameter Symbol Min Typ Max Unit

DC Power Supply: Positive Digital

Positi ve Analog

|VA - VD|

4.75

5.0

5.25

0.4

V V V

DS153F1 5

CS4329

Ω

1 µF

0.1 µF

1 µF

0.1 µF

+5V

Analog

Mode

Select

Audio

Data

Processor

External Clock

DIF0

DIF1

DIF2

LRCK

SCLK*

SDATA

DEM0

DEM1

MUTE_R

MUTE_L

AUTO_MUTE

MCLK

DGND

CS4329

AGND

AOUTL-

AOUTL+

AOUTR-

AOUTR+

Analog

Conditioning

Analog

Conditioning

* SCLK mus t be connec ted to D GND for operation in Internal SCLK Mode

Figure 1. Typical Connection Diagram

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CS4329

GENERAL DESCRIPTION

The CS4329 is a com plete ste reo dig ital-t o-analo g

system including 128× digital interpolation, fourthorder delta-sigma digital-to-analog conversion, 128× oversampled one-bit delta-sigma modulator and analog filtering. This architecture provides a high insensitivity to clock jitter. The DAC converts digital data at a ny input sample rat e bet w een 1 and 50 kHz, including the standa rd audio rates of 48,

44.1 and 32 kHz. The primary purpose of using delta-sigma modula-

tion techni ques is to avo id the limi tations of lase r trimmed resistive DAC architectures by using an inherently linear 1-bit DAC. The advantages of a 1bit DAC include: ideal differential linearity, no distortion mechanisms due to resistor matching errors and no linearity drift over time and temperature due to variations in resist or va lues.

Digital Interpolation Filter

The digital interpolation filter increases the sample rate by a factor of 4 and is followed by a 32× digital sample-and hold to effectivel y achieve a 128× interpolation filter. This filter eliminates images of the baseband audio s ignal w hich exi st at m ultiple s of the input sample rate, Fs. This allows for the selection of a less complex analog filter based on outof-band noise atte nuat ion requi reme nts rath er t han anti-image filtering. Following the interpolation filter, the resulting frequ ency spectrum ha s i ma g e s

of the input signa l at multiples of 128× the in put sample rate. These images are removed by the external analog filter.

Delta-Sigma Modulator

The interpola tion filter is fol lowed by a fo urth-order delta-sigm a modula tor whic h convert s the 24bit interpolation filter output into 1-bit data at 128× Fs.

Switched-Capacitor Filter

The delta-sigma modulator is followed by a digitalto-analog co nverter whi ch transl ates the 1-bi t data into a se ries of char ge packets. T he magnitud e of the charge in each packet is determined by sampling of a voltage reference onto a switched capacitor, where the polarity of each packet is controlled by the 1-b it signa l. Thi s techn ique greatl y reduce s the sensitivity to clock jitter and is a major improvement over earlier generations of 1-bit digitalto-analog converters where the magnitude of charge in the D-to-A process is determined by switching a curr ent reference for a period of time defined by the mast er c loc k.

The CS4329 incorporates a differential output to maximize the output level to minimize the amount of gain required in the output analog stage. The differential outp ut also allows for the can cellation of common mode errors in the di fferential to si ngledended conve rter.

Interpolator

DS153F1 7

Delta-Sigma

Modulator

DAC

Figure 2. Block Diagram

Analog

Low-Pass

Filter

AOUTL+

AOUTL-

CS4329

SYSTEM DESIGN Master Clock

The Maste r Clock, MCLK, is us ed to operate the digital interpolation filter and the delta-sigma mod-

ulator. MCLK must be either 256×, 384 × or 512× the desired Input Sample Rate, Fs. Fs is the frequency at which digital audio samples for each channel a re input to th e DAC and is e qual to the LRCK frequ ency. The MCL K to LRCK freq uency ratio is dete ct ed au toma tic ally dur ing the init ia lization seque nce by counting the number of MCLK transitions during a single LR CK period. Internal dividers are th en set to generate the proper clocks for the digital filter, delta-sigma modulator and switched-capa citor filter. LRCK must be synchronous with MCLK. Once the MCLK to LRCK frequency ratio has been detected, the phase and frequency relationship between the two clocks must remain fix ed. If during any LRCK th is relationship is changed, the CS4329 will reset. Table 1 illustrate s the stand ard audio sam ple rates and the required MCLK frequencies.

(kHz)

32 8.1920 12.2880 16.3840

44.1 11.2896 16.9344 22.5792 48 12.2880 18.4320 24.5760

Table 1. Common Clock Frequencies

256x 384x 512x

MCLK (MHz)

in 2's-complement format with the MSB-first in all seven formats .

Formats 0, 1 and 2 are shown in Figure 3. The audio data is right-justified, LSB aligned with the trailing edge of LRCK, and latched into the serial input data buffer on the rising edge of SCLK. Formats 0, 1 and 2 are 16, 18 and 20-b it versions and differ only in the number of data bits required.

Formats 3 and 4 are 20-bit left justified, MSB aligned with the leading edge of LRCK, and are identical with the exception of the SCLK edge used to latch data . Data is latc hed on t he fa lli ng edge of SCLK in Format 3 a nd the rising edge of SCLK in Format 4. Both form ats will suppo rt 16 an d 18-bit inputs if the data is followed by four or two zeros to simulate a 20-bit input as shown in Figures 4 and 5. A very small of fset will result if th e 18 or 16-bit data is follow ed by stat ic non-zero data.

Formats 5 and 6 are compatible with the I

S serial data protocol and are shown in Figures 6 and 7. Notice that the MSB is delayed 1 period of SCLK following the leading edge of LRCK and LRCK is inverted compared to the pre vious formats. Data is latched on the rising edge of SCLK. Format 5 is 16-

S while Format 6 is 20-bit I2S. 18-bit I2S can

bit I be implemented in Format 6 if the data is followed by two zeros to simulate a 20-bit inpu t as shown in Figure 7. A very small offset will result if the 18-bit data is follow ed by stat ic non-zero data.

Serial Data Interface

The Seri al Data interfac e is accomplis hed via the serial data input, SDATA, serial data clock, SCLK, and the left/r ight clock, LRCK . The CS4329 supports seven seri al data formats wh ich are select ed via the digital input format pins DIF0, DIF1 and DIF2. The different formats control the relationship of LRCK to the serial data and the edge of

DIF2 DIF1 DIF0 Format Figure

00003 00113 01023 01134 10045 10156 11067 111Calibrate-

SCLK used t o latch t he data into th e input b uffer. Table 2 lists the seven formats, along with the associated fi gu re numb er. The s er ial dat a is re pres en ted

8 DS153F1

Table 2. Digital Input Formats

DS153F1 9

LRCK

SCLK

SDATA

Format 0

SDATA

Format 1

SDATA

Format 2

LRCK

SCLK

Left Channel

19 18

15 14 13 12 11 10

17 16

15 14 13 12 11 1017 16

6543210987

54321098 7

1819

15 14 13 12 11 10

17 16

15 14 131211 10

Right Channel

6543210987

NOTE: Format 1 is not compatible with CS4390

Figure 3. Digital Input Format 0, 1 and 2.

Left Channel

Right Channel

SDATA

16-Bit

SDATA

18-Bit

SDATA

20-Bit

15 14 15 14

15 14 13 12 11 10 654321098715 14 13 12 11 10

19 18

4321076513 12 11 10 9 8 654321098713 12 11 10

543210987

654321098715 14 13 12 11 1017 16

17 16

19 18

Figure 4. Digital Input Format 3.

654321098715 14 13 12 11 1017 16

CS4329

10 DS153F1

LRCK

SCLK

Left Channel

Right Channel

SDATA

16-Bit

SDATA

18-Bit

SDATA

20-Bit

LRCK

SCLK

SDATA 16-Bit

15 14 15 14

15 14 13 12 11 10 654321098715 14 13 12 11 10

14 13 12 11 10

19 18

4321076513 12 11 10 9 8 654321098713 12 11 10

543210987

6543210987

17 16

19 18

Figure 5. Digital Input Format 4.

Left Channel Right Ch an ne l

15 14 13 12 11 10

654321

Figure 6. Digital Input Format 5.

6543210

8715 141312 11 10

4321098715 14 13 12 11 1017 16

LRCK

SCLK

SDATA

18-Bit

SDATA

20-Bit

15 14 13 12 11 10

17 16

19 18

Left Channel Right Channel

6543210987

654321098715 14 13 12 11 1017 16

17 16

19 18

14 13 12 11 10

Figure 7. Digital Input Format 6.

654321098715 14 13 12 11 10

CS4329

6543210987

CS4329

Serial Clock

The serial clo ck controls the shi fting of data into the input dat a buffers. The CS4329 su pports both external and internal serial clock generation modes.

External Serial Clock

The CS4329 will enter the external serial clock mode if 15 or more high\low transitions are detected on the SCLK pin during any phase of the LRCK period. When this mode is enabled, internal serial clock mode can not be accessed without ret urning to the power down mode.

Internal Serial Clock

In the Internal Serial Cl ock Mode, the seria l clock is internally derived and synchronous with MCLK. The interna l SCLK / LRCK ratio is al ways 64 and operation in this mode is identical to operation with an external serial clock synchron ized with L RCK. The SCLK pin must be connected to DGND for proper operation.

De-Emphasis

Implementation of digital de-emphasis requires reconfigu ration of th e digital f ilter to main tain the fi lter response sh own in Figure 8 at m ultipl e samp le rates. The CS4 329 is capa ble of di gital de-e mphasis for 32, 44.1 or 48kHz sample rates. Table 3 shows the de-emphasis con trol inputs for DEM 0 and DEM 1.

DEM 1 DEM 0 De-emphasis

0032kHz

0144.1kHz 1048kHz 11OFF

Table 3. De-Emphasis Filter Selection

Gain

0dB

T1=50

The inte rnal serial clock mode is advant ageous in that there are situations where improper serial clock routin g on the printe d circuit board can degrade system pe rforma nce. The use of th e intern al serial clock mode simplifies the routing of the printed circ uit board by allowing the serial clock trace to be deleted and avoids possible interference effects.

Mute Functions

The CS4329 includes an auto-mute function which will initiate a mute if 8192 consecutive 0’s or 1’s are input on both the Left and Right channels. The mute will be released when non-st at ic input data is applied to the DAC. The auto-mute function is useful for applicat ions, such as com pact disk playe rs, where the idle channel noise must be minimized. This feature is active only if the AUTO_MUTE is low and is independent of the status of MUTE_L and MUTE_R. Either channel can also be muted instantaneou sly with the MUTE_L or MUT E _R.

T2 = 15µs

Frequency

-10dB

3.183 kHz

Figure 8. De-emphasis Filter Response

10.61 kHz

Initialization, Calibration and Power-Down

Upon initia l power -up, the DA C en te rs the po wer down mode. The interpolation filters and delta-sigma modulat ors are reset, and the in ternal voltage reference, one-bit D/A converters and switched-capacitor low-pass filters are powered down. The device will remain in the power-down mode until MCLK and LR CK are pres en te d. Once MCLK and LRCK are detected, MCLK occurrences are counted over one LRCK period to determine the MCLK/LRCK fre qu ency rati o. The ph ase and fre quency rela tionship between the two clocks m ust remain fixed. If during any LRCK this relationship

DS153F1 11

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