Datasheet CS42L50-KN, CDB42L50 Datasheet (Cirrus Logic)

CS42L50

Low Voltage, Stereo CODEC with Headphone Amp

Features

l 28-Pin CASON package l 1.8 to 3.3 Volt supply l 24-Bit conversion / 96 kHz sample rate l 96 dB ADC/DAC dynamic range at 3 V supply l -88/-85 dB ADC/DAC THD+N l 19 mW playback power consumption @ 1.8 V l Microphone or Line input amplifier with up to

32dB of gain

l 2:1 stereo mux l Digital volume control on inputs and outputs

– 96 dB attenuation, 1 dB step size

l Digital bass and treble boost on outputs

– Selectable corner frequencies

l Dynamic range compression and limiting l De-emphasis for 32 kHz, 44.1 kHz, and 48 kHz l Headphone amplifier

– 26 mW power output into 16 W load @ 3.0V

supply – -80 dB THD+N – 34 dB analog attenuation and mute

l ATAPI mixing functions

I I

SCL SDA

Description

The CS42L50 is a highly integrated, 24-bit, 96 kHz audio codec.

This device is based on delta-sigma modulation allowing infinite adjustment of the sample rate between 8 kHz and 100 kHz simply by changing the master clock frequency.

The CS42L50 contains a 2:1 stereo mux, programmable analog gain control, and digital attenuation on the analog inputs. The output D/A converters include digital bass and treble boost, dynamic range compression, limiting, mixing, volume control and de-emphasis.

The CS42L50 operates from a +1.8 V to +3.3 V supply. These features are ideal for portable MP3 and MD recorders, CD and DVD recorders, digital camcorders, and other portable systems that require extremely low power consumption in a minimal amount of space.

ORDERING INFORMATION

CS42L50-KN 28-pin CASON, -10 to 70 °C CDB42L50 Evaluation Board

RST

LRCK

SCLK

SDIN

SDOUT

Control Port

Serial Port

Attenuator

Compression

De-emphasis

0-96 dB

Digital Volume Control

Bass/Treble

Boost

Limiting

Preliminary Product Information

P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com

Analog

Digital

Filters

MCLK

Volume Control

Analog

MUX

Volume Control

i a

Compensation

MUTEC

Gain

12 dB

Gain

12 dB

∆Σ

DAC

∆Σ

Digit al Filters

DAC

Analog

Filter

Analog

Filter

ADC

Headphone

Line

Amplifier

HP_A

HP_B

AOUT_A

AOUT_B

AIN_L1

AIN_L2

AIN_R1

AIN_R2

This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.

AUG ‘01

DS544PP1

TABLE OF CONTENTS

1. CHARACTERISTICS/SPECIFICATIONS ................................................................................. 5

ANALOG INPUT CHARACTERISTICS .................................................................................... 5

ANALOG OUTPUT CHARACTERISTICS ................................................................................ 7

POWER AND THERMAL CHARACTERISTICS..................................................................... 10

DIGITAL CHARACTERISTICS ............................................................................................... 11

ABSOLUTE MAXIMUM RATINGS ......................................................................................... 11

RECOMMENDED OPERATING CONDITIONS ..................................................................... 11

SWITCHING CHARACTERISTICS ........................................................................................ 12

SWITCHING CHARACTERISTICS - CONTROL PORT......................................................... 14

2. TYPICAL CONNECTION DIAGRAM ....................................................................................... 15

3. REGISTER QUICK REFERENCE ........................................................................................... 16

4. REGISTER DESCRIPTION ..................................................................................................... 18

4.1 ADC (address 0010000) .................................................................................................. 18

4.1.1 I/O and Power Control (address 01h) .......................................................................... 18

4.1.2 20DB Gain Boost (BOOST) .......................................................................................... 18

4.1.3 Analog Input Multiplexer (AINMUX) ............................................................................... 18

4.1.4 Power Down (PDN)........................................................................................................ 18

4.1.5 Control Port Enable (CP_EN) ........................................................................................ 18

4.1.6 Interface Control (address 02h) .................................................................................... 19

4.1.7 Master Clock Divide (MCLKDIV)................................................................................... 19

4.1.8 Master Clock Ratio (RATIO) ......................................................................................... 19

4.1.9 Master Mode (MASTER)............................................................................................... 19

4.1.10 Digital Interface Format (DIF) ..................................................................................... 19

4.1.11 Analog I/O Control (address 03h) ............................................................................... 20

4.1.12 Left/Right Channel Mute (MUTE)............................................................................... 20

4.1.13 Soft Ramp and Zero Cross Enable (SOFT/ZC) ......................................................... 20

4.1.14 Independent Volume Control Enable (INDVC) .......................................................... 21

4.1.15 Left Channel Volume = Right Channel Volume (L=R) ............................................... 21

4.1.16 High-Pass Filter Freeze (HPFREEZE)....................................................................... 21

4.1.17 Volume Control: Left Channel (address 04h) & Right Channel (address 05h) ............ 22

4.1.18 Left/Right Analog Gain (address 06h) ........................................................................ 22

4.1.19 Clip Detection Status (address 07h) .......................................................................... 23

4.2 DAC (Address = 0010001) ............................................................................................... 23

4.2.1 Power and Muting Control (address 01h) .................................................................... 23

4.2.2 Auto-Mute (AMUTE) ..................................................................................................... 23

4.2.3 Soft Ramp and Zero Cross Control (SZC) ..................................................................... 23

4.2.4 Power Down Headphone Amplifier (PDNHP) ................................................................ 24

CS42L50

Contacting Cirrus Logic Support

For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:

http://www.cirrus.com/corporate/contacts/sales.cfm

Purchase of I2C components of Cirrus Logic, Inc., or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use those components in a standard I2C system. Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, including use of this information as the basis for manufacture or sale of any items, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and by furnishing this information, Cirrus Logic, Inc. grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights of Cirrus Logic, Inc. Cirrus Logic, Inc., copyright owner of the information contained herein, gives consent for copies to be made of the information only for use within your organization with respect to Cirrus Logic integrated circuits or other parts of Cirrus Logic, Inc. The same consent is given for similar information contained on any Cirrus Logic website or disk. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found

2 DS544PP1

at http://www.cirrus.com

CS42L50

4.2.5 Power Down Line Amplifier (PDNLN)............................................................................ 24

4.2.6 Power Down (PDN) ....................................................................................................... 24

4.2.7 Control Port Enable (CP_EN) ........................................................................................ 24

4.2.8 Channel A Analog Headphone Attenuation Control (address 02h) (HVOLA) .............. 25

4.2.9 Channel B Analog Headphone Attenuation Control (address 03h) (HVOLB) .............. 25

4.2.10 Channel A Digital Volume Control (address 04h) (DVOLA) ....................................... 25

4.2.11 Channel B Digital Volume Control (address 05h) (DVOLB) ....................................... 25

4.2.12 Tone Control (address 06h)........................................................................................ 26

4.2.13 Bass Boost Level (BB)................................................................................................. 26

4.2.14 Treble Boost Level (TB)............................................................................................... 26

4.2.15 Mode Control (address 07h) ....................................................................................... 27

4.2.16 Bass Boost Corner Frequency (BBCF) ....................................................................... 27

4.2.17 Treble Boost Corner Frequency (TBCF) ..................................................................... 27

4.2.18 Channel A Volume = Channel B Volume (A=B) .......................................................... 27

4.2.19 De-Emphasis Control (DEM) ....................................................................................... 28

4.2.20 Digital Volume Control Bypass (VCBYP) .................................................................... 28

4.2.21 Volume and Mixing Control (address 0Ah) ................................................................. 28

4.2.22 Tone Control Mode (TC).............................................................................................. 28

4.2.23 Tone Control Enable (TC_EN) .................................................................................... 28

4.2.24 ATAPI Channel Mixing and Muting (ATAPI)................................................................ 29

4.2.25 Mode Control 2 (address 0Bh) ................................................................................... 29

4.2.26 Master Clock Divide Enable (MCLKDIV) ..................................................................... 29

4.2.27 Line Amplifier Gain Compensation (LINE)................................................................... 29

4.2.28 Digital Interface Format (DIF) ...................................................................................... 30

5. PIN DESCRIPTIONS ............................................................................................................... 31

6. APPLICATIONS ...................................................................................................................... 33

6.1 Grounding and Power Supply Decoupling ....................................................................... 33

6.2 Clock Modes .................................................................................................................... 33

6.3 EP73xx Serial Port Interface ........................................................................................... 33

6.4 De-Emphasis ................................................................................................................... 33

6.5 Recommended Power-up Sequence ............................................................................... 33

6.6 Optional External Headphone Mute ................................................................................ 33

7. CONTROL PORT INTERFACE ............................................................................................... 33

7.1 Memory Address Pointer (MAP) ...................................................................................... 35

7.2 INCR (Auto Map Increment Enable) ................................................................................. 35

7.3 MAP0-3 (Memory Address Pointer).................................................................................. 35

8. PARAMETER DEFINITIONS ................................................................................................... 44

9. REFERENCES ......................................................................................................................... 44

10. PACKAGE DIMENSIONS ..................................................................................................... 45

LIST OF FIGURES

Figure 1. SCLK to LRCK and SDIN, Slave Mode .................................................... 13

Figure 2. SCLK to LRCK and SDIN, Master Mode .................................................. 13

Figure 3. Control Port Timing - I

Figure 4. CS42L50 Typical Connection Diagram .................................................... 15

Figure 5. Control Port Timing .................................................................................. 35

Figure 6. Decimation Filter Single Speed Stopband Rejection ............................... 36

Figure 7. Decimation Filter Single Speed Transition Band ...................................... 36

Figure 8. Decimation Filter Single Speed Transition Band (Detail) ......................... 36

Figure 9. Decimation Filter Single Speed Passband Ripple ................................... 36

Figure 10.Decimation Filter Double Speed Stopband Rejection .............................. 36

Figure 11.Decimation Filter Double Speed Transition Band .................................... 36

Figure 12.Decimation Filter Double Speed Transition Band (Detail) ........................ 37

DS544PP1 3

C‚ ......................................................................... 14

Figure 13.Decimation Filter Double Speed Passband Ripple .................................. 37

Figure 14.Interpolation Filter Single Speed Stopband Rejection .............................. 38

Figure 15.Interpolation Filter Single Speed Transition Band .................................... 38

Figure 16.Interpolation Filter Single Speed Transition Band (Detail) ....................... 38

Figure 17.Interpolation Filter Single Speed Passband Ripple .................................. 38

Figure 18.Interpolation Filter Double Speed Stopband Rejection ............................ 38

Figure 19.Interpolation Filter Double Speed Transition Band ................................... 38

Figure 20.Interpolation Filter Double Speed Transition Band (Detail) ...................... 39

Figure 21.Interpolation Filter Double Speed Passband Ripple ................................. 39

Figure 22.Line Input Test Circuit .............................................................................. 39

Figure 23.Line Output Test Load .............................................................................. 40

Figure 24.Headphone Output Test Load .................................................................. 40

Figure 25.Left Justified, up to 24-bit data ................................................................. 41

Figure 26.Right Justified, 16-bit data ........................................................................ 41

Figure 27.Right Justified, 24-bit data ........................................................................ 41

Figure 28.Right Justified, 18-bit data ........................................................................ 42

Figure 29.Right Justified, 20-bit data ........................................................................ 42

Figure 30.I2S, up to 24-bit data ................................................................................ 42

Figure 31.De-Emphasis Curve ................................................................................. 43

Figure 32.ATAPI Block Diagram ............................................................................... 43

Figure 33.Package Dimensions ................................................................................ 45

Figure 34.Package Top and Side Views .................................................................. 46

Figure 35.Package Bottom View .............................................................................. 47

CS42L50

LIST OF TABLES

Table 1. Example Analog Volume Settings ...................................................................................25

Table 2. Example Digital Volume Settings ....................................................................................26

Table 3. Example Bass Boost Settings .........................................................................................26

Table 4. Example Treble Boost Settings .......................................................................................27

Table 5. ATAPI Decode.................................................................................................................29

Table 6. Digital Interface Format ...................................................................................................30

4 DS544PP1

1. CHARACTERISTICS/SPECIFICATIONS

CS42L50

ANALOG INPUT CHARACTERISTICS (T

GND = 0 V; MCLK = 12.288 MHz; Fs for Single Speed Mode = 48 kHz, SCLK = 3.072 MHz, Fs for Double Speed Mode = 96 kHz, SCLK = 6.144 MHz; Measurement Bandwidth 10 Hz to 20 kHz, unless otherwise specified. Input is 997Hz sine wave.)

Parameter Symbol

Analog Input Characteristics for VA = 1.8 V

Dynamic Range A-weighted

unweighted

Total Harmonic Distortion + Noise (Note 1)

18 to 24-Bit -1 dB

-20 dB

-60 dB

16-Bit -1 dB

-20 dB

-60 dB

Dynamic Range (PGA on)*

0 dB Gain A-weighted

unweighted

12 dB Gain A-weighted

unweighted

Total Harmonic Distortion + Noise (PGA on)* (Note 1) 0 dB Gain, 18 to 24-Bit -1 dB

12 dB Gain, 18 to 24-Bit -1 dB

Analog Input Characteristics for VA = 3.0 V

Dynamic Range A-weighted

unweighted

Total Harmonic Distortion + Noise (Note 1)

18 to 24-Bit -1 dB

-20 dB

-60 dB

16-Bit -1 dB

-20 dB

-60 dB

Dynamic Range (PGA on)*

0 dB Gain A-weighted

unweighted

12 dB Gain A-weighted

unweighted

Total Harmonic Distortion + Noise (PGA on)* (Note 1) 0 dB Gain, 18 to 24-Bit -1 dB

12 dB Gain, 18 to 24-Bit -1 dB

*PGA : Programmable Gain Amplifier

THD+N

= 25° C; GND = 0 V Logic "1" = VL = 1.8 V; Logic "0" =

Single Speed Mode Double Speed Mode

UnitMin Typ Max Min Typ Max

TBD TBD9390

TBD TBD9693

-88

-70

-30

-86

-68

-28

90 87 85 82

85 83

-88

-73

-33

-86

-68

-28

93 90 88 85

78 73

TBD

TBD TBD9491

-88

-71

-31

-86

-68

-28

TBD TBD9895

89 86 86 83

84 82

-85

-75

-35

-83

-65

-28

92 89 89 86

77 76

TBD

dB dB

dB dB dB dB dB dB

dB dB dB dB

dB dB

dB dB dB dB dB dB

dB dB dB dB

dB dB

DS544PP1 5

CS42L50

Single Speed Mode Double Speed Mode

Parameter Symbol

Analog Input Characteristics for VA = 1.8 - 3.3V

Interchannel Isolation 1 kHz - 90 - - 90 - dB

Interchannel Gain Mismatch - 0.1 - - 0.1 - dB

Offset Error (with HPF Active) - - 0 - - 0 LSB

Full Scale Input Voltage TBD VA/3.6 TBD TBD VA/3.6 TBD Vrms

Gain Drift - 100 - - 100 - ppm/°C

Input Resistance 10 - - 10 - - kΩ

Input Capacitance - - 15 - - 15 pF

Programmable Gain Characteristics

Gain Step Size - 1.0 - - 1.0 - dB

Absolute Gain Step Error - - TBD - - TBD dB

A/D Decimation Filter Characteristics (Note 2)

Passband (Note 3) 0 - 23.5 0 - 47.5 kHz

Passband Ripple -0.08 - +0.17 -0.09 - 0 dB

Stopband (Note 3) 27.5 - - 64.1 - - kHz

Stopband Attenuation (Note 4) -60.3 - - -48.4 - - dB

Group Delay (Fs = Output Sample Rate)(Note 5) t

Group Delay Variation vs. Frequency ∆t

High Pass Filter Characteristics

Frequency Response -3 dB (Note 2)

-0.1 dB

Phase Deviation @ 20 Hz (Note 2) - 10 - - 10 - Degree

Passband Ripple (Note 2) - - 0.17 - - 0.09 dB

*PGA : Programmable Gain Amplifier

- 10/Fs - - 2.7/Fs - s

- - 0.03 - - 0.007 µs

3.7

24.2

3.7

24.2

UnitMin Typ Max Min Typ Max

6 DS544PP1

CS42L50

ANALOG OUTPUT CHARACTERISTICS (T

GND = 0 V; Full-Scale Output Sine Wave, 997 Hz; MCLK = 12.288 MHz; Measurement Bandwidth 10 Hz to 20 kHz, unless otherwise specified; Fs for Single Speed Mode = 48 kHz, SCLK = 3.072 MHz. Fs for Double Speed Mode = 96 kHz, SCLK = 6.144 MHz. Test load R C

= 10 pF (see Figure 24) for headphone out.

Parameter

Line Output Dynamic Performance for VA = 1.8 V

Dynamic Range (Note 6)

18 to 24-Bit unweighted

A-Weighted

16-Bit unweighted

A-Weighted

Total Harmonic Distortion + Noise (Note 6)

18 to 24-Bit 0 dB

-20 dB

-60 dB

16-Bit 0 dB

-20 dB

-60 dB

Interchannel Isolation (1 kHz) - 100 - - 100 - dB

Headphone Output Dynamic Performance for VA = VA_HP = 1.8 V

Dynamic Range (Note 6)

18 to 24-Bit unweighted

A-Weighted

16-Bit unweighted

A-Weighted

Total Harmonic Distortion + Noise (Note 6)

18 to 24-Bit 0 dB

-20 dB

-60 dB

16-Bit 0 dB

-20 dB

-60 dB

Interchannel Isolation (1 kHz) - 66 - - 66 - dB

=10kΩ, CL= 10 pF (see Figure 23) for line out, RL=16Ω,

Symbol Min Typ Max Min Typ Max Unit

THD+N

= 25° C; Logic "1" = VL = 1.8 V; Logic "0" =

Single Speed Mode Double Speed Mode

TBD TBD

91 94 89 92

-80

-71

-31

-78

-69

-29

88 91 86 89

-82

-68

-28

-80

-66

-26

TBD

TBD TBD

89 92 87 90

-80

-69

-29

-78

-67

-27

88 91 86 89

-85

-68

-28

-83

-66

-26

TBD

dB dB

Notes: 1. Referenced to typical full-scale input voltage.

2. Filter response is not tested but is guaranteed by design.

3. Filter characteristics scale with output sample rate. For output sample rates, Fs, other than 48 kHz, the

0.01 dB passband edge is 0.4535x Fs and the stopband edge is 0.625x Fs.

4. The analog modulator samples the input at 6.144 MHz for an Fs equal to 48 kHz. There is no rejection of input signals which are multiples of the sampling frequency ( n x 6.144 MHz ±21.8 kHz where n = 0,1,2,3...).

5. Group delay for Fs = 48 kHz, t

6. One-half LSB of triangular PDF dither is added to data.

DS544PP1 7

= 10/48 kHz = 208 µs.

CS42L50

ANALOG OUTPUT CHARACTERISTICS (Continued)

Single Speed Mode Double Speed Mode

Parameter

Line Output Dynamic Performance for VA = 3.0 V

Dynamic Range (Note 6) 18 to 24-Bit unweighted A-Weighted 16-Bit unweighted A-Weighted

Total Harmonic Distortion + Noise (Note 6) 18 to 24 Bit 0dB

-20dB

-60dB 16-Bit 0dB

-20dB

-60dB

Interchannel Isolation (1 kHz) - 100 - - 100 - dB

Headphone Output Dynamic Performance for VA = VA_HP = 3.0 V

Dynamic Range (Note 6) 18 to 24-Bit unweighted A-Weighted 16-Bit unweighted A-Weighted

Total Harmonic Distortion + Noise (Note 6) 18 to 24 Bit 0dB

-20dB

-60dB 16-Bit 0dB

-20dB

-60dB

Interchannel Isolation (1 kHz) - 66 - - 66 - dB

Symbol Min Typ Max Min Typ Max Unit

TBD

dB dB dB

dB dB dB dB dB dB

dB dB dB dB

dB dB dB dB dB dB

THD+N

TBD TBD

93 96 91 94

-85

-73

-33

-83

-71

-31

90 93 88 91

-76

-70

-30

-74

-68

-28

TBD

TBD TBD

93 96 91 94

-85

-73

-33

-83

-71

-31

90 93 88 91

-73

-70

-30

-71

-68

-28

8 DS544PP1

CS42L50

ANALOG OUTPUT CHARACTERISTICS (Continued)

Parameters Symbol Min Typ Max Units

Analog Output

Full Scale Line Output Voltage (Note 7) V Line Output Quiescent Voltage V Full Scale Headphone Output Voltage V Headphone Output Quiescent Voltage V

FS_LINE

Q_LINE

FS_HP

Q_HP

Interchannel Gain Mismatch - 0.1 - dB Gain Drift - 100 - ppm/°C Maximum Line Output AC-Current VA=1.8 V

LINE

VA= 3 . 0 V

Maximum Headphone Output VA=VA_HP=1.8 V

AC-Current VA=VA_HP=3.0 V

Single Speed Mode Double Speed Mode

Parameter

Combined Digital and On-chip Analog Filter Response (Note 8)

Passband (Note 9)

to -0.05 dB corner

to -0.1 dB corner

to -3 dB corner

Frequency Response 10 Hz to 20 kHz

(Note 10)

StopBand .5465 - - .577 - - Fs

StopBand Attenuation (Note 11) 50 - - 55 - - dB

Group Delay tgd - 9/Fs - - 4/Fs - s

Passband Group Delay Deviation 0 - 40 kHz

0 - 20 kHz

De-emphasis Error Fs = 32 kHz (Relative to 1 kHz) Fs = 44.1 kHz

Fs = 48 kHz

Symbol Min Typ Max Min Typ Max Unit

-.02 - +.08 0 - +0.11 dB

--±0.36/Fs

TBD G x VA TBD Vpp

- 0.5 x VA_LINE - VDC

TBD 0.55 x VA TBD Vpp

- 0.5 x VA_HP - VDC

.4535

.4998

+.2/-.1

+.05/-.14

+0/-.22

0.1

0.15 31

0 0

--±1.39/Fs

±0.23/Fs--

(Note 12)

.4426 .4984

mA mA

Fs Fs Fs

s s

dB dB dB

Notes: 7. See Section 4.2.7 for details.

8. Filter response is not tested but is guaranteed by design.

9. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 14 through 21) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.

10. Referenced to a 1 kHz, full-scale sine wave.

11. For Single Speed Mode, the measurement bandwidth is 0.5465 Fs to 3 Fs. For Double Speed Mode, the measurement bandwidth is 0.577 Fs to 1.4 Fs.

12. De-emphasis is not available in Double Speed Mode.

DS544PP1 9

CS42L50

POWER AND THERMAL CHARACTERISTICS (GND = 0 V; All voltages with respect to

ground. All measurements taken with all zeros input and open outputs, unless otherwise specified.)

Parameters Symbol Min Typ Max Units

Power Supplies

Power Supply Current- VA=1.8 V Normal Operation VA_HP=1.8 V

VL=1.8 V

Power Supply Current- VA=3.0 V Normal Operation VA_HP=3.0 V

VL=3.0 V

Power Supply Current- All Supplies=1.8 V Power Down Mode (Note 13) All Supplies =3.0V

Total Power Dissipation- All Supplies=1.8 V Normal Operation All Supplies=3.0 V

Maximum Headphone Power Dissipation (1 kHz full-scale sine wave VA=1.8 V into 16 ohm load) VA=3.0 V

Package Thermal Resistance θ Power Supply Rejection Ratio (Note 14) (1 kHz)

(60 Hz)

A_HP

D_L

A_HP

D_L

PSRR -

13.3

1.5

154

1.5

270 150

350

27 65

15 26

TBD TBD

mA mA

µA

mA mA

µA µA

µA

mW mW

-55-°C/Watt 60

dB dB

Notes: 13. Power Down Mode is defined as RST

14. Valid with the recommended capacitor values on FILT+_ADC, FILT+_DAC, VQ_DAC, and VQ_ADC as shown in Figure 4. Increasing the capacitance will also increase the PSRR. Note that care should be taken when selecting capacitor type, as any leakage current in excess of 1.0 µA will cause degradation in analog performance. A small ceramic capacitor in parallel with a larger electrolytic is recommended.

= LO with all clocks and data lines held static.

10 DS544PP1

CS42L50

DIGITAL CHARACTERISTICS (T

= 25° C; VL = 1.7 V - 3.3 V; GND = 0 V)

Parameters Symbol Min Typ Max Units

High-Level Input Voltage

Low-Level Input Voltage Input Leakage Current I High-Level Output Voltage V Low-Level Output Voltage V

0.7 x VL - - V

- - 0.3 x VL V

--±10µA

0.7 x VL - - V

- - 0.3 x VL V Input Capacitance - 8 - pF Maximum MUTEC Drive Capability VA=1.8 V

VA= 3 . 0 V

TBD

mA MUTEC High-Level Output Voltage - VA - V MUTEC Low-Level Output Voltage - 0 - V

ABSOLUTE MAXIMUM RATINGS (GND = 0V; all voltages with respect to ground.)

Parameters Symbol Min Max Units

DC Power Supplies: Analog&Headphone

Digital I/O Input Current, Any Pin Except Supplies I Digital Input Voltage V Ambient Operating Temperature (power applied) T Storage Temperature T

WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is

not guaranteed at these extremes.

VA&VA_HP

IND

stg

-0.3

4.0

V V

-±10mA

-0.3 VL+0.4 V

-55 125 °C

-65 150 °C

RECOMMENDED OPERATING CONDITIONS (GND = 0V; all voltages with respect to ground.)

Parameters Symbol Min Typ Max Units

Ambient Temperature T DC Power Supplies: Analog&Headphone (Note 15)

VA&VA_HPVL1.7

Digital I/O

Notes: 15. VA and VA_HP should be tied to the same supply as shown in Figure 4.

-10 - 70 °C

1.7

3.6

V V

DS544PP1 11

CS42L50

SWITCHING CHARACTERISTICS (T

Logic 1 = VL, C

= 20 pF)

= -10 to 70° C; VA = 1.7 V - 3.3 V; Inputs: Logic 0 = GND,

Parameters Symbol Min Typ Max Units

Input Sample Rate Single Speed Mode

Double Speed Mode

Fs Fs

100

kHz kHz

MCLK Pulse Width High MCLK/LRCK = 1024 8 - - ns

MCLK Pulse Width Low MCLK/LRCK = 1024 8 - - ns

MCLK Pulse Width High MCLK/LRCK = 768 10 - - ns

MCLK Pulse Width Low MCLK/LRCK = 768 10 - - ns

MCLK Pulse Width High MCLK/LRCK = 512 15 - - ns

MCLK Pulse Width Low MCLK/LRCK = 512 15 - - ns

MCLK Pulse Width High MCLK / LRCK = 384 or 192 25 - - ns

MCLK Pulse Width Low MCLK / LRCK = 384 or 192 25 - - ns

MCLK Pulse Width High MCLK / LRCK = 256 or 128 35 - - ns

MCLK Pulse Width Low MCLK / LRCK = 256 or 128 35 - - ns

Master Mode

SCLK Falling to LRCK Edge t

SCLK Falling to SDOUT Valid t

slrd

sdo

-20 - 20 ns

0 - 20 ns

SCLK Duty Cycle 40 50 60 %

Slave Mode

LRCK Duty Cycle 40 50 60 %

Rise Time of Both LRCK and SCLK t

Fall Time of Both LRCK and SCLK t

SCLK Period (Note 16) Single Speed Mode

Double Speed Mode

sclkw

SCLK Falling to LRCK Edge t

SCLK Falling to SDOUT Valid Single Speed Mode

Double Speed Mode

slrd

dss

- - 10 ns

------------ ---------128()Fs

------------ ------

64()Fs

-20 - 20 ns

(512)Fs

(256)Fs

16. There must be exactly 32, 48, 64, or 128 SCLK periods per LRCK transition.

12 DS544PP1

CS42L50

SCLK

LRCK

SDIN

sclkh

sclkl

slrd

dss

MSB

Figure 1. SCLK to LRCK and SDIN, Slave Mode

sclkw

SCLK

slrd

LRCK

sdo

SDIN

MSB MSB-1

Figure 2. SCLK to LRCK and SDIN, Master Mode

DS544PP1 13

SWITCHING CHARACTERISTICS - CONTROL PORT

(TA = 25° C; VL = 1.7 V - 3.3 V; Inputs: logic 0 = GND, logic 1 = VL, CL = 30 pF)

Parameter Symbol Min Max Unit

SCL Clock Frequency f

Rising Edge to Start t

RST

Bus Free Time Between Transmissions t

Start Condition Hold Time (prior to first clock pulse) t

Clock Low time t

Clock High Time t

Setup Time for Repeated Start Condition t

SDA Hold Time from SCL Falling (Note 17) t

SDA Setup time to SCL Rising t

Rise Time of SCL t

Fall Time of SCL t

Rise Time of SDA t

Fall Time of SDA t

Setup Time for Stop Condition t

scl

irs

buf

hdst

low

high

sust

hdd

sud

susp

CS42L50

-100KHz

500 - ns

4.7 - µs

4.0 - µs

4.7 - µs

4.0 - µs

4.7 - µs

0-µs

250 - ns

-25ns

-1µs

-300ns

4.7 - µs

Note: 17. Data must be held for sufficient time to bridge the transition time, t

RST

SDA

SCL

irs

Stop S ta rt

buf

hdd

high

sud

hdst

low

Figure 3. Control Port Timing - I2C

Repeated

Start

sust

hdst

, of SCL.

Stop

susp

14 DS544PP1

2. TYPICAL CONNECTION DIAGRAM

CS42L50

1.8 to 3.3 V Supply

1.0 µF 0.1 µF

150 Ω

0.47 µF

150 Ω

0.47 µF

150 Ω

0.47 µF

150 Ω

0.47 µF

Digital

Audio

Source

µc

Configuration

1.0 nF

0. 1 µ F

0. 1 µF

0. 1 µ F

0. 1 µF

1.0 nF

AIN_L1

AIN_R1

AIN_L2

AIN_R2

MCLK

SCLK

LRCK

SDOUT

SDIN

RST

SDA

SCL

AFLTL

AFLTR

0.1 µF 0.1 µF

13 21

VA_HPVA VL

CS42L50

VQ_DAC

FILT+_DAC

REF_GND

FILT+_ADC

VQ_ADC

GND

HP_A

HP_B

AOUTL

AOUTR

MUTEC

220 µF

3.3 µ F +

0.1 µF

C =

1.0 µF

RL + 560

4 π F

1 kΩ

10 kΩ

1.0 µF

(RL560)

4.7 µH

560 Ω

1.0 µF

0.1 µF

1.8 to 3.3 V Supply

Headphones

Mute

Circuit

1.0 µF

Ω

Figure 4. CS42L50 Typical Connection Diagram

DS544PP1 15

CS42L50

3. REGISTER QUICK REFERENCE

ADC (Address = 0010000)

Addr Function 7 6 5 4 3 2 1 0

0h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

default

1h I/O and Power

Control

default

2h Interface Control Reserved MCLKDIV RATIO1 RATIO0 MASTER DIF2 DIF1 DIF0

default

3h Analog I/O Control MUTEL MUTER SZC1 SZC0 Reserved INDVC L=R HPFREEZE

default

4h Left Channel Digital

Volume Control

default

5h Right Channel Digital

Volume Control

default

6h Analog Gain Control LVOL3 LVOL2 LVOL1 LVOL0 RVOL3 RVOL2 RVOL1 RVOL0

default

7h Clip Detection Status Reserved Reserved Reserved Reserved Reserved Reserved CLIP_L CLIP_R

default

000 0000 0

Reserved BOOST

000 0000 0

001 1000 0

VOL7 VOL6 VOL5 VOL4 VOL3 VOL2 VOL1 VOL0

000 0000 0

VOL7 VOL6 VOL5 VOL4 VOL3 VOL2 VOL1 VOL0

000 0000 0

AINMUX1

AINMUX0 Reserved Reserved PDN CP_EN

0001 0

DAC (Address = 0010001)

Addr Function 7 6 5 4 3 2 1 0

0h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

default

1h Power and Muting

Control

default

2h Channel A Analog

Headphone Attenuation Control

default

3h Channel B Analog

Headphone Attenuation Control

default

4h Channel A Digital

Volume Control

default

5h Channel B Digital

Volume Control

default

00000000

AMUTE SZC1

HVOLA7 HVOLA6 HVOLA5 HVOLA4 HVOLA3 HVOLA2 HVOLA1 HVOLA0

00000000

HVOLB7 HVOLB6 HVOLB5 HVOLB4 HVOLB3 HVOLB2 HVOLB1 HVOLB0

00000000

DVOLA7 DVOLA6 DVOLA5 DVOLA4 DVOLA3 DVOLA2 DVOLA1 DVOLA0

00000000

DVOLB7 DVOLB6 DVOLB5 DVOLB4 DVOLB3 DVOLB2 DVOLB1 DVOLB0

00000000

SZC0

Reserved PDNHP PDNLN PDN CP_EN

10010

16 DS544PP1

CS42L50

Addr Function 7 6 5 4 3 2 1 0

6h Tone Control BB3 BB2 BB1 BB0 TB3 TB2 TB1 TB0

default

7h Mode Control BBCF1 BBCF0 TBCF1 TBCF0 A=B DEM1 DEM0 VCBYP

default

8h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

default

9h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

default

Ah Volume and Mixing

Control

default

Bh Mode Control 2 MCLKDIV LINE1 LINE0 Reserved Reserved DIF2 DIF1 DIF0

default

00000000

00010000

00100000

TC1 TC0 TC_EN Reserved ATAPI3 ATAPI2 ATAPI1 ATAPI0

00001001

00000000

DS544PP1 17

CS42L50

4. REGISTER DESCRIPTION

4.1 ADC (Address = 0010000)

4.1.1 I/O and Power Control (address 01h)

76543210

RESERVED BOOST AINMUX1 AINMUX0 RESERVED RESERVED PDN CP_EN

00000010

4.1.2 20DB GAIN BOOST (BOOST)

Default = 0

0 - Disabled 1 - Enabled

Function:

Applies a 20dB digital gain to the input signal, regardless of the input path.

4.1.3 ANALOG INPUT MULTIPLEXER (AINMUX)

Default = 00

00 - Channel 1 direct to A/D 01 - Channel 2 direct to A/D 10 - Channel 2 through PGA to A/D 11 - Reserved

Function:

The analog input multiplexer selects the input channel as well as the input path associated with various gain stages.

4.1.4 POWER DOWN (PDN)

Default - 1

0 - Disabled 1 - Enabled

Function:

The entire ADC device will enter a low-power state whenever this function is activated. The power-down bit defaults to ‘enabled’ on power-up and must be disabled before normal operation will begin. The contents of the control registers are retained when this mode is enabled.

4.1.5 CONTROL PORT ENABLE (CP_EN)

Default = 0

0 - Disabled 1 - Enabled

Function:

The ADC will enter control port mode when this bit is enabled. This bit must be set prior to writing to the control port.

18 DS544PP1

CS42L50

4.1.6 Interface Control (address 02h)

76543210

RESERVED MCLKDIV RATIO1 RATIO0 MASTER DIF2 DIF1 DIF0

00000000

4.1.7 MASTER CLOCK DIVIDE (MCLKDIV)

Default = 0

0 - Disabled 1 - Enabled

Function:

Divides ADC MCLK by two prior to all other chip circuitry.

4.1.8 MASTER CLOCK RATIO (RATIO)

Default = 00

00 - 128x 01 - 192x 10 - 256x 11 - 384x

Function:

Sets the ratio of MCLK to LRCK for the ADC.

4.1.9 MASTER MODE (MASTER)

Default = 0

0 - Slave Mode 1 - Master Mode

Function:

Configures the CS42L50 for master or slave operation.

4.1.10 DIGITAL INTERFACE FORMAT (DIF)

Default = 000

000 - I 001 - Left Justified, up to 24-bit data, data valid on positive edge of SCLK 010 - Reserved 011 - Right Justified, 16-bit data, data valid on positive edge of SCLK 100 - Right Justifed, 24-bit data, data valid on positive edge of SCLK 101 - Right Justified, 18-bit data, data valid on positive edge of SCLK 110 - Right Justified, 20-bit data, data valid on positive edge of SCLK 111 - Reserved

Function:

The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and the options are detailed in Figures 25 through 30. It is recommended that the ADC and the DAC are configured for the same Digital Interface Format.

S, up to 24-bit data, data valid on positive edge of SCLK

DS544PP1 19

CS42L50

4.1.11 Analog I/O Control (address 03h)

76543210

MUTEL MUTER SZC1 SZC0 RESERVED INDVC L=R HPFREEZE

00110000

4.1.12 LEFT/RIGHT CHANNEL MUTE (MUTE)

Default = 0

0 - Disabled 1 - Enabled

Function:

Digital mute of the left and right ADC channels.

4.1.13 SOFT RAMP AND ZERO CROSS ENABLE (SOFT/ZC)

Default = 11 00 - Change volume immediately 01 - Change volume at next zero cross time 10 - Change volume in 1dB steps 11 - Change volume in 1dB steps at every zero cross time

Function:

Soft Ramp Enable : Soft Ramp allows level changes, both muting and attenuation, to be implemented via an incremental ramp. Digital volume control is ramped from the current level to the new level at a rate of 1/8 dB per left/right clock period. Analog volume control is ramped in 1 dB steps every 8 left/right clock periods in Single Speed mode, and 1dB every 16 left/right clock periods in Double Speed mode.

Zero Cross Enable : Zero Cross enable dictates that signal level changes, either by attenuation changes or muting, will occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a timeout period of 512 sample periods in Single Speed mode or 1024 sample periods in Double Speed mode (approximately 10.7ms at 48kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel.

Soft Ramp and Zero Cross Enable : Soft Ramp and Zero Cross enable dictates that signal level changes, either by attenuation changes or muting, will occur in 1 dB steps and be implemented on a signal zero crossing. The level change will occur after a timeout period of 512 sample periods in Single Speed mode or 1024 sample periods in Double Speed mode (approximately 10.7 ms at 48kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel.

20 DS544PP1

4.1.14 INDEPENDENT VOLUME CONTROL ENABLE (INDVC)

Default = 0

0 - Disabled 1 - Enabled

Function:

When this function is disabled, the AIN_L and AIN_R volume levels are controlled by the Left and Right Volume Control registers and the Independent Analog Gain Control registers are ignored. When this function is enabled, the volume levels are determined by both the Volume Control registers and the Independent Analog Gain Control registers.

4.1.15 LEFT CHANNEL VOLUME = RIGHT CHANNEL VOLUME (L=R)

Default = 0

0 - Disabled 1 - Enabled

Function:

When this function is disabled, the left channel volume is determined by the left channel volume control register and right channel volume is determined by the right channel volume control register.

CS42L50

When enabled, the left and right channel volumes are determined by the left channel volume control register and the right channel volume control register is ignored.

4.1.16 HIGH-PASS FILTER FREEZE (HPFREEZE)

Default = 0

0 - Frozen 1 - Enabled

Function:

The high-pass filter works by continuously subtracting a measure of the dc offset from the output of the decimation filter. If the HPFREEZE bit is taken low during normal operation, the current value of the dc offset is frozen and this dc offset will continue to be subtracted from the conversion result.

DS544PP1 21

CS42L50

4.1.17 Volume Control: Left Channel (address 04h) & Right Channel (address 05h)

76543210

VOL7 VOL6 VOL5 VOL4 VOL3 VOL2 VOL1 VOL0

00000000

Default = 0 (No attenuation)

Binary Code Decimal Value Volume Setting

00001010 12 +12 dB

00000111 7 +7 dB 00000000 0 0 dB 11000100 -60 -60 dB 10100110 -90 -90 dB

Function:

The volume control allows the user to alter the signal level in 1 dB increments from +12 to -96 dB, when the INDVC bit is disabled. When INDVC is enabled, the volume control can be altered in 1 dB increments from 0 to -96dB. Volume settings are decoded as shown above, using a 2’s complement code. The volume changes are implemented as dictated by the Soft and Zero Cross bits in the Analog I/O Control register. All volume settings less than -96dB are equivalent to muting the channel.

4.1.18 Left/Right Analog Gain (address 06h)

76543210

LVOL3 LVOL2 LVOL1 LVOL0 RVOL3 RVOL2 RVOL1 RVOL0

00000000

Default = 0 (No gain)

Binary Code Decimal Value Volume Setting

0000 0 0 dB 0010 2 +2 dB 1010 6 +6 dB 1001 9 +9 dB 1100 12 +12 dB

Function:

The level of the left and right analog channels can be adjusted in 1dB increments as dictated by the Soft Ramp and Zero Cross bits from 0 to +12dB when routed through the PGA via the AINMUX bits. Levels are decoded as shown above. Levels above +12dB are interpreted as +12dB.

22 DS544PP1

CS42L50

4.1.19 Clip Detection Status (address 07h)

76543210

RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED CLIP_L CLIP_R

00000000

Default = 0 (No clipping detected)

Function:

The Clip Flags indicate when there is an over-range condition anywhere in the CS42L50 internal signal path. These bits are “sticky”. They constantly monitor the ADC signal path and are set to 1 when an overrange condition occurs. They are reset to 0 when read.

4.2 DAC (Address = 0010001)

4.2.1 Power and Muting Control (address 01h)

76543210

AMUTE SZC1 SZC0 POR PDNHP PDNLN PDN CP_EN

11010010

4.2.2 AUTO-MUTE (AMUTE)

Default = 1

0 - Disabled 1 - Enabled

Function:

The Digital-to-Analog converter output will mute following the reception of 8192 consecutive audio samples of static 0 or -1. A single sample of non-static data will release the mute. Detection and muting is done independently for each channel. The quiescent voltage on the output will be retained and the Mute Control pin will go active during the mute period. The muting function is affected, similar to volume control changes, by the Soft and Zero Cross bits in the Power and Muting Control register.

4.2.3 SOFT RAMP AND ZERO CROSS CONTROL (SZC)

Default = 10

00 - Immediate Change 01 - Zero Cross Digital and Analog 10 - Ramped Digital and Analog 11 - Reserved

Function:

Immediate Change

When Immediate Change is selected all level changes will take effect immediately in one step.

Zero Cross Digital and Analog

Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a timeout period of 512 sample periods (10.7 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel.

DS544PP1 23

Ramped Digital and Analog

Soft Ramp allows digital level changes, both muting and attenuation, to be implemented by incrementally ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods. Analog level changes will occur in 1 dB steps on a signal zero crossing. The analog level change will occur after a timeout period of 512 sample periods (10.7 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel.

Note: Ramped Digital and Analog is not available in Double Speed Mode.

4.2.4 POWER DOWN HEADPHONE AMPLIFIER (PDNHP)

Default = 0

0 - Disabled 1 - Enabled

Function:

The headphone amplifier will independently enter a low-power state when this function is enabled.

4.2.5 POWER DOWN LINE AMPLIFIER (PDNLN)

CS42L50

Default = 0

0 - Disabled 1 - Enabled

Function:

The line output amplifier will independently enter a low-power state when this function is enabled.

4.2.6 POWER DOWN (PDN)

Default = 1

0 - Disabled 1 - Enabled

Function:

The entire DAC device will enter a low-power state when this function is enabled, and the contents of the control registers are retained in this mode. The power-down bit defaults to ‘enabled’ on power-up and must be disabled before normal operation will begin.

4.2.7 CONTROL PORT ENABLE (CP_EN)

Default = 0

0 - Disabled 1 - Enabled

Function:

The DAC will enter control port mode when this bit is enabled. This bit must be set prior to writing to the control port.

24 DS544PP1

CS42L50

4.2.8 Channel A Analog Headphone Attenuation Control (address 02h) (HVOLA)

4.2.9 Channel B Analog Headphone Attenuation Control (address 03h) (HVOLB)

76543210

HVOLx7 HVOLx6 HVOLx5 HVOLx4 HVOLx3 HVOLx2 HVOLx1 HVOLx0

00000000

Default = 0 dB (No attenuation)

Function:

The Analog Headphone Attenuation Control operates independently from the Digital Volume Control. The Analog Headphone Attenuation Control registers allow attenuation of the headphone output signal for each channel in 1 dB increments from 0 to -25 dB. Attenuation settings are decoded using a 2’s complement code, as shown in Table 1. The volume changes are implemented as dictated by the Soft and Zero Cross bits in the Power and Muting Control register. All volume settings greater than zero are interpreted as zero.

Note: The Analog Headphone Attenuation only affects the headphone outputs. When set for levels

greater than -10dB, the actual attenuation deviates from the register setting by more than 1 dB.

Binary Code Decimal Value Volume Setting

00000000 0 0 dB

11110110 -10 -10 dB

11110 0 01 -15 -1 5 dB

Table 1. Example Analog Volume Settings

4.2.10 Channel A Digital Volume Control (address 04h) (DVOLA)

4.2.11 Channel B Digital Volume Control (address 05h) (DVOLB)

76543210

DVOLx7 DVOLx6 DVOLx5 DVOLx4 DVOLx3 DVOLx2 DVOLx1 DVOLx0

00000000

Default = 0 dB (No attenuation)

Function:

The Digital Volume Control registers allow independent control of the signal levels in 1 dB increments from +18 to -96 dB. Volume settings are decoded using a 2’s complement code, as shown in Table 2. The volume changes are implemented as dictated by the Soft and Zero Cross bits in the Power and Muting Control register. All volume settings less than -96 dB are equivalent to muting the channel via the ATAPI bits (see Section 4.46).

Note: The digital volume control affects both the line outputs and the headphone outputs. Setting this

DS544PP1 25

CS42L50

Binary Code Decimal Value Volume Setting

00001010 12 +12 dB

00000111 7 +7 dB 00000000 0 0 dB 11000100 -60 -60 dB 10100110 -90 -90 dB

Table 2. Example Digital Volume Settings

4.2.12 Tone Control (address 06h)

76543210

BB3 BB2 BB1 BB0 TB3 TB2 TB1 TB0

00000000

4.2.13 BASS BOOST LEVEL (BB)

Default = 0 dB (No Bass Boost)

Function:

The level of the shelving bass boost filter is set by Bass Boost Level. The level can be adjusted in 1 dB increments from 0 to +12 dB of boost. Boost levels are decoded as shown in Table 3. Levels above +12 dB are interpreted as +12 dB.

Binary Code Decimal Value Boost Setting

0000 0 0 dB 0010 2 +2 dB 1010 6 +6 dB 1001 9 +9 dB 1100 12 +12 dB

Table 3. Example Bass Boost Settings

4.2.14 TREBLE BOOST LEVEL (TB)

Default = 0 dB (No Treble Boost)

Function:

The level of the shelving treble boost filter is set by Treble Boost Level. The level can be adjusted in 1 dB increments from 0 to +12 dB of boost. Boost levels are decoded as shown in Table 4. Levels above +12 dB are interpreted as +12 dB.

Note: Treble Boost is not available in Double Speed Mode.

26 DS544PP1

CS42L50

Binary Code Decimal Value Boost Setting

0000 0 0 dB 0010 2 +2 dB 1010 6 +6 dB 1001 9 +9 dB 1100 12 +12 dB

Table 4. Example Treble Boost Settings

4.2.15 Mode Control (address 07h)

76543210

BBCF1 BBCF0 TBCF1 TBCF0 A=B DEM1 DEM0 VCBYP

00000000

4.2.16 BASS BOOST CORNER FREQUENCY (BBCF)

Default = 00

00 - 50 Hz 01 - 100 Hz 10 - 200 Hz 11 - Reserved

Function:

The bass boost corner frequency is user selectable as shown above.

4.2.17 TREBLE BOOST CORNER FREQUENCY (TBCF)

Default = 00

00 - 2 kHz 01 - 4 kHz 10 - 7 kHz 11 - Reserved

Function:

The treble boost corner frequency is user selectable as shown above.

Note: Treble Boost is not available in Double Speed Mode.

4.2.18 CHANNEL A VOLUME = CHANNEL B VOLUME (A=B)

Default = 0

0 - Disabled 1 - Enabled

Function:

The AOUTA/HP_A and AOUTB/HP_B volume levels are independently controlled by the A and the B Channel Volume Control Bytes when this function is disabled. The volume on both AOUTA/HP_A and AOUTB/HP_B are determined by the A Channel Attenuation and Volume Control Bytes, and the B Channel Bytes are ignored when this function is enabled.

DS544PP1 27

4.2.19 DE-EMPHASIS CONTROL (DEM)

Default = 00

00 - Disabled 01 - 44.1 kHz 10 - 48 kHz 11 - 32 kHz

Function:

Selects the appropriate digital filter to maintain the standard 15 µs/50 µs digital de-emphasis filter response at 32, 44.1 or 48 kHz sample rates. (see Figure 31)

Note: De-emphasis is not available in Double Speed Mode.

4.2.20 DIGITAL VOLUME CONTROL BYPASS (VCBYP)

Default = 0

0 - Disabled 1 - Enabled

Function:

The digital volume control section is bypassed when this function is enabled. This disables the digital volume control, muting, bass boost, treble boost, limiting and ATAPI functions. The analog headphone attenuation control will remain functional.

CS42L50

4.2.21 Volume and Mixing Control (address 0Ah)

76543210

TC1 TC0 TC_EN LIM_EN ATAPI3 ATAPI2 ATAPI1 ATAPI0

00001001

4.2.22 TONE CONTROL MODE (TC)

Default = 00

00 - All settings are taken from user registers 01 - 12 dB of Bass Boost at 100 Hz and 6 dB of Treble Boost at 7 kHz 10 - 8 dB of Bass Boost at 100 Hz and 4 dB of Treble Boost at 7 kHz 11 - 4 dB of Bass Boost at 100 Hz and 2 dB of Treble Boost at 7 kHz

Function:

The Tone Control Mode bits determine how the Bass Boost and Treble Boost features are configured. The user defined settings from the Bass and Treble Boost Level and Corner Frequency registers are used when these bits are set to ‘00’. Alternately, one of three pre-defined settings may be used.

4.2.23 TONE CONTROL ENABLE (TC_EN)

Default = 0

0 - Disabled 1 - Enabled

Function:

The Bass Boost and Treble Boost features are active when this function is enabled.

28 DS544PP1

4.2.24 ATAPI CHANNEL MIXING AND MUTING (ATAPI)

Default = 1001 - AOUTA/HP_A = L, AOUTB/HP_B = R (Stereo)

Function:

The CS42L50 implements the channel mixing functions of the ATAPI CD-ROM specification. Refer to

Table 5 and Figure 32 for additional information.

Note: All mixing functions occur prior to the digital volume control.

ATAPI3 ATAPI2 ATAPI1 ATAPI0 AOUTA/HP_A AOUTB/HP_B

0000 MUTE MUTE 0001 MUTE R 0010 MUTE L 0011 MUTE [(L+R)/2] 0100 R MUTE 0101 R R 0110 R L 0111 R [(L+R)/2] 1000 L MUTE 1001 L R 1010 L L 1011 L [(L+R)/2] 1100[(L+R)/2] MUTE 1101[(L+R)/2] R 1110[(L+R)/2] L 1111[(L+R)/2] [(L+R)/2]

Table 5. ATAPI Decode

CS42L50

4.2.25 Mode Control 2 (address 0Bh)

76543210

MCLKDIV LINE1 LINE0 RESERVED RESERVED DIF2 DIF1 DIF0

00000000

4.2.26 MASTER CLOCK DIVIDE ENABLE (MCLKDIV)

Default = 0

0 - Disabled 1 - Enabled

Function:

The MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2 prior to all other DAC circuitry.

4.2.27 LINE AMPLIFIER GAIN COMPENSATION (LINE)

Default = 00

00 - 0.785 x VA 01 - 0.943 x VA 10 - Reserved

DS544PP1 29

11 - Line Mute

Function:

The Line Amplifier Gain Compensation bits allow the user to scale the full-scale line output level according to the power supply voltage used. The full-scale line output level will be equal to {gain factor}xVA, where {gain factor} is selected from options above.

The Line Mute option is available to allow muting of the line output when the headphone output is still in use and the line amp is still powered up. To use this feature, first mute the outputs via the ATAPI bits. Next, set the LINE GAIN to Line Mute. Finally, un-mute the outputs with the ATAPI bits. Following these steps will ensure a click free mute.

4.2.28 DIGITAL INTERFACE FORMAT (DIF)

Default = 000 - Format 0 (I2S, up to 24-bit data)

Function:

The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and the options are detailed in Figures 25-30. It is recommended that the ADC and the DAC is configured for the same Digital Interface Format.

CS42L50

DIF2 DIF1 DIF0 DESCRIPTION Format FIGURE

000 001 010 011 100 101 110 111

I2S, up to 24-bit data Reserved Left Justified, up to 24-bit data, Right Justified, 24-bit data Right Justified, 20-bit data Right Justified, 16-bit data Right Justified, 18-bit data Identical to Format 0

030

-225 327 429 526 628 030

Table 6. Digital Interface Format

30 DS544PP1

CS42L50

5. PIN DESCRIPTIONS

Filter Capacitor AFLTR RST Reset Filter Capacitor AFLTL SCL Control Port Clock

Voltage Reference FILT+_ADC SDA Control Port Data

Analog Input 2 Right AIN_R2 LRCK Left/Right Clock

Analog Input 2 Left AIN_L2 SDOUT Serial Audio Data Output

Ground Reference REF_GND VA Analog Power

Analog Input 1 Right AIN_R1 GND Ground Reference

Analog Input 1 Left AIN_L1 VL Interface Power

Quiescent Voltage VQ_ADC SDIN Serial Audio Data Input

Voltage Reference FILT+_DAC MCLK Master Clock

Quiescent Voltage VQ_DAC SCLK Serial Clock

Headphone A Output HP_A MUTEC External Mute Control

Headphone Amp Power VA_HP AOUTL Analog Output Left

Headphone B Output HP_B AOUTR Analog Output Right

821

12 17

14 15

Pin Name # Pin Description

VA_ H P

VQ_ADC VQ_DAC

REF_GND

GND

23 Analog Power (Input) - Positive power supply for the analog section. Refer to the Recommended Oper-

ating Conditions for appropriate voltages.

Logic Power (Input) - Determines the required signal level for the digital input/output. Refer to the Rec-

ommended Operating Conditions for appropriate voltages.

13 Headphone Amp Power (Input) - Positive power supply for the headphone amplifier. Refer to the Rec-

ommended Operating Conditions for appropriate voltages.

9,11 Quiescent Voltage (Output) - Filter connection for internal quiescent voltage. VQ must be capacitively

coupled to analog ground, as shown in the Typical Connection Diagram. The nominal voltage level is specified in the Analog Characteristics and Specifications section. VQ presents an appreciable source impedance and any current drawn from this pin will alter device performance. However, VQ can be used

to bias the analog circuitry assuming there is no AC signal component and the DC current is less than 10uA.

Reference Ground (Input) - Ground reference for the internal sampling circuits and must be connected

to analog ground.

Ground (Input) - Ground reference. Should be connected to analog ground.

Serial Audio Interface

MCLK

SCLK

LRCK

SDIN

SDOUT

Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters.

Serial Clock (Input/Output) - Serial clock for the serial audio interface.

Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the

serial audio data line. The frequency of the left/right clock must be at the audio sample rate, Fs.

Serial Audio Data Input (Input) - Input for two’s complement serial audio data.

Serial Audio Data Output (Output) - Output for two’s complement serial audio data.

DS544PP1 31

Analog Input/Output

AIN_Rx AIN_Lx

AOUTL AOUTR

HP_A

HP_B

4, 5,

7,8

15,

12,

Control Port Interface

SCL

SDA

Control & Misc.

AFLTR AFLTL

FILT+_ADC

FILT+_DAC

MUTEC

RST

1,2

17 Mute Control (Output) - The Mute Control pin goes low during power-up initialization, reset, muting,

CS42L50

Analog Inputs (Input) - The full scale analog input level is specified in the Analog Input Characteristics

specification table.

Analog Outputs (Output) - The full scale analog line output level is specified in the Analog Output Char-

acteristics specifications table.

Headphone Outputs (Output) - The full scale analog headphone output level is specified in the Analog

Output Characteristics specifications table.

Serial Control Port Clock (Input) - Serial clock for the serial control port. Requires an external pull-up

resistor to the logic interface voltage as shown in the Typical Connection Diagram.

Serial Control Data (Input/Output) - SDA is a data I/O line and requires an external pull-up resistor to

the logic interface voltage, as shown in the Typical Connection Diagram.

Anti-Aliasing Capacitors (Output) - Anti-aliasing capacitors for the left and right channels. An external

capacitor is required from AFLTR and AFLTL to ground, as shown in the Typical Connections Diagram. AFLTR and AFLTL are not intended to supply external current, and any current drawn from these pins will alter device performance.

Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.

Requires the capacitive decoupling to AGND as shown in the Typical Connection Diagram.

Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.

Requires the capacitive decoupling to AGND as shown in the Typical Connection Diagram.

power-down or if the master clock to left/right clock frequency ratio is incorrect. This pin is intended to be used as a control for an external mute circuit to prevent the clicks and pops that can occur in any single supply system. The use of an external mute circuit is not mandatory but may be desired for designs requiring the absolute minimum in extraneous clicks and pops.

Reset (Input) - The device enters a low power mode and all internal registers are reset to their default

settings when low. When high, the control port becomes operational and the CP_EN bits must be set and the PDN bits must be cleared before normal operation will occur. The control port cannot be accessed when Reset is low.

32 DS544PP1

CS42L50

6. APPLICATIONS

6.1 Grounding and Power Supply Decoupling

As with any high resolution converter, the CS42L50 requires careful attention to power supply and grounding arrangements to optimize performance. Figure 4 shows the recommended power arrangement with VA, VA_HP, and VL connected to clean supplies. Decoupling capacitors should be located as close to the device package as possible. If desired, all supply pins may be connected to the same supply, but a decoupling capacitor should still be used on each supply pin.

6.2 Clock Modes

The CS42L50 operates in one of two clocking modes. Single Speed Mode supports input sample rates up to 50 kHz, and Double Speed Mode supports input sample rates up to 100 kHz. All clock modes use 64x oversampling.

6.3 EP73xx Serial Port Interface

Special considerations must be made when interfacing the CS42L50 with the EP73xx series of ARM processors. To receive stereo data from the ADC, connect the MCLK pin (pin 19) of the CS42L50 to the BUZ pin (pin 93) of the EP73xx, and run the serial port in 64Fs mode with MCLK generation enabled on the EP73xx. Any other configuration, either hardware or software modes, will result in mono data being produced from the ADC of the CS42L50.

6.4 De-Emphasis

The CS42L50 includes on-chip digital de-emphasis. Figure 31 shows the de-emphasis curve. The frequency response of the de-emphasis curve will scale proportionally with changes in sample rate, Fs.

The de-emphasis feature is included to accommodate older audio recordings that utilize pre-emphasis equalization as a means of noise reduction.

6.5 Recommended Power-up Sequence

1) Hold RST low until the power supply, master clock and left/right clock are stable. In this state, the control port is reset to its default settings and VQ_ADC and VQ_DAC will remain low.

2) Bring RST high. The device will remain in a low power state and VQ_ADC and VQ_DAC remain low. The control port will be accessible at this time and the desired register settings can be loaded after setting the CP_EN bits and while keeping the PDN bits set to 1.

3) Once the registers are configured as desired, set the PDN bits to 0, initiating the power-up sequence.

6.6 Optional External Headphone Mute

An external headphone mute circuit, as shown in the CDB42L50 datasheet schematic, is recommended to minimize the effects of output transients during power-up and power-down. This technique minimizes the audio transients commonly produced by single-ended, single-supply converters when it is implemented with external DC-blocking capacitors connected in series with the audio outputs.

Use of the Mute Control function on the line outputs is recommended for designs requiring the absolute minimum in extraneous clicks and pops. Also, use of the Mute Control function can enable the system designer to achieve idle channel noise/signal-to-noise ratios only limited by the external mute circuit. See the CDB42L50 datasheet for a suggested mute circuit.

7. CONTROL PORT INTERFACE

The control port is used to load all the internal settings. The operation of the control port may be completely asynchronous with the audio sample rate. However, to avoid potential interference problems, the control port pins should remain static if

DS544PP1 33

CS42L50

no operation is required. Please note that the internal registers are separated into two unique chip address blocks, one for the control of the ADC and one for the control of the DAC portion of the codec.

SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL, with the clock to data relationship as shown in Figure 5. The upper 6 bits of the 7 bit address field must be

001000. To communicate with the CS42L50, the chip address should match that of the ADC (0010000) or DAC (0010001) address. The eighth bit of the address byte is the R/W bit (high for a read, low for a write). If the operation is a write, the

next byte is the Memory Address Pointer, MAP, which selects the register to be read or written. The MAP is then followed by the data to be written. If the operation is a read, the contents of the register pointed to by the MAP will be output after the chip address.

The CS42L50 has MAP auto increment capability, enabled by the INCR bit in the MAP register. If INCR is 0, then the MAP will stay constant for successive writes. If INCR is set to 1, then MAP will auto increment after each byte is written, allowing block reads or writes of successive registers.

34 DS544PP1

7.1 Memory Address Pointer (MAP)

76543210

INCR Reserved Reserved Reserved MAP3 MAP2 MAP1 MAP0

00000000

7.2 INCR (AUTO MAP INCREMENT ENABLE)

Default = ‘0’ 0 - Disabled 1 - Enabled

7.3 MAP0-3 (MEMORY ADDRESS POINTER)

Default = ‘0000’

Note 1

SDA

001000

ADDR AD0

R/W

ACK

DATA 1-8

ACK

DATA 1-8

ACK

CS42L50

SCL

Start

Note: If o peration is a w rite , th is byte co ntains the M em ory A d dress P o in ter, M AP .

Figure 5. Control Port Timing

Stop

DS544PP1 35

CS42L50

-10

-20

-30

-40

-50

-60

Amplitude dB

-70

-80

-90

-100 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

Frequency (normaliz ed to Fs)

Figure 6. Decimation Filter Single Speed Stopband

Rejection

-1

-2

-3

-4

-5

-6

Amplitude dB

-7

-8

-9

-10

0. 45 0.46 0. 47 0.48 0. 49 0.5 0. 51 0.52 0. 53 0.54 0. 55

Freque ncy (normalized to Fs)

Figure 8. Decimation Filter Single Speed Transition

Band (Detail)

-10

-20

-30

-40

-50

-60

Amplitude dB

-70

-80

-90

-100

0. 4 0. 42 0.44 0. 46 0.48 0. 5 0. 52 0.54 0. 56 0.58 0. 6

Frequency (normal ized to Fs)

Figure 7. Decimation Filter Single Speed Transition

Band

0.3

0. 25

0.2

0. 15

0.1

0. 05 0

-0.05

-0.1

Amplitude dB

-0.15

-0.2

-0.25

-0.3

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

Freque ncy (normal ized to Fs)

Figure 9. Decimation Filter Single Speed Passband

Ripple

-10

-20

-30

-40

-50

-60

Amplitude dB

-70

-80

-90

-100

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

Frequency (normal iz e d to Fs)

Figure 10. Decimation Filter Double Speed Stopband

Rejection

-10

-20

-30

-40

-50

-60

Amplitude dB

-70

-80

-90

-100

0.4 0.43 0.46 0.49 0.52 0.55 0.58 0.61 0.64 0.67

Frequency (normaliz ed to Fs)

Figure 11. Decimation Filter Double Speed Transition

Band

36 DS544PP1

CS42L50

-1

-2

-3

-4

-5

-6

Amplitude dB

-7

-8

-9

-10

0. 45 0.46 0.47 0. 48 0. 49 0. 5 0. 51 0. 52 0.53 0. 54 0. 55

Freque ncy (normal ized to Fs)

Figure 12. Decimation Filter Double Speed Transition

Band (Detail)

0.3

0.25

0.2

0.15

0.1

0.05 0

-0.05

-0.1

Amplitude dB

-0.15

-0.2

-0.25

-0.3

0 0.05 0. 1 0. 15 0. 2 0. 25 0. 3 0.35 0. 4 0. 45 0. 5

Frequency (normalized to Fs)

Figure 13. Decimation Filter Double Speed Passband

Ripple

DS544PP1 37

CS42L50

Figure 14. Interpolation Filter Single Speed Stopband

Rejection

Figure 16. Interpolation Filter Single Speed Transition

Band (Detail)

-10

-20

-30

-40

-50

-60

Amplitude dB

-70

-80

-90

-100

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

Frequency (normalized to Fs)

Figure 18. Interpolation Filter Double Speed Stopband

Rejection

Figure 15. Interpolation Filter Single Speed Transition

Band

Figure 17. Interpolation Filter Single Speed Passband

Ripple

-10

-20

-30

-40

-50

-60

Amplitude dB

-70

-80

-90

-100

0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.6

Frequency ( normali zed to Fs)

Figure 19. Interpolation Filter Double Speed Transition

Band

38 DS544PP1

CS42L50

-1

-2

-3

-4

-5

-6

Amplitude dB

-7

-8

-9

-10

0.45 0.46 0.47 0.48 0.49 0.50 0.51 0.52 0.53 0.54 0.5

Frequency (normalized to Fs)

Figure 20. Interpolation Filter Double Speed Transition

Band (Detail)

Ω

150

0.47 µF

0.30

0.25

0.20

0.15

0.10

0.05

0.00

-0.05

Amplit ude d B

-0.10

-0.15

-0.20

-0.25

-0.30

0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.5

Frequency (normalized to Fs)

Figure 21. Interpolation Filter Double Speed Passband

Ripple

AIN_xx

0.01 µF

Figure 22. Line Input Test Circuit

GND

DS544PP1 39

AOUTx

3.3 µF

CS42L50

out

AGND

Figure 23. Line Output Test Load

220 µF

HP_x

AGND

out

Figure 24. Headphone Output Test Load

40 DS544PP1

CS42L50

LRCK

SCLK

SDATA +3 +2 +1

MSB

-1 -2 -3 -4 -5

Left Channel

+5 +4

Left Justified, up to 24-Bit Data. Data Valid on Rising Edge of SCLK.

Figure 25. Left Justified, up to 24-bit data

LRCK

SCLK

SDATA

Left Channel

15 14 13 12 11 10

Right Justified, 16-Bit Data. Data Valid on Rising Edge of

32 clocks

SCLK. SCLK Must Have at Least 32 Cycles per LRCK Period.

Figure 26. Right Justified, 16-bit data

LSB

Right Channel

+3 +2 +1

MSB

-1 -2 -3 -4

6543210987

15 14 13 12 11 10

+5 +4

Right Channel

LSB

6543210987

LRCK

SCLK

SDATA

Left Channel

23 22 21 20 19 18

32 clocks

Right Justified, 24-Bit Data. Data Valid on Rising Edge of

65432107

23 22 21 20 19 18

Right Channel

65432107

SCLK. SCLK Must Have at Least 48 Cycles per LRCK Period.

Figure 27. Right Justified, 24-bit data

DS544PP1 41

CS42L50

LRCK

SCLK

SDATA

LRCK

SCLK

SDATA

Right C hannel

Left Channel

17 16 17 16

15 14 13 12 11 10

32 clocks

6543210987

15 14 13 12 11 10

Right Justified, 18-Bit Data. Data Valid on Rising Edge of SCLK. SCLK Must Have at Least 36 Cycles per LRCK Period.

Figure 28. Right Justified, 18-bit data

Left Channel

10 6543210987

17 16 17 16

19 18 19 18

15 14 13 12 11 10

32 clocks

6543210987

15 14 13 12 11 10

Right Channel

Right Justified, 20-Bit Data. Data Valid on Rising Edge of SCLK. SCLK Must Have at Least 40 Cycles per LRCK Period.

6543210987

Figure 29. Right Justified, 20-bit data

LRCK

SCLK

SDATA +3 +2 +1

MSB

-1 -2 -3 -4 -5

Left Channel

+5 +4

I2S, up to 24-Bit Data. Data Valid on Rising Edge of SCLK

LSB

MSB

-1 -2 -3 -4

Figure 30. I2S, up to 24-bit data

Right Channel

+3 +2 +1

+5 +4

LSB

42 DS544PP1

CS42L50

Gain

T1=50 µs

0dB

T2 = 15 µs

-10dB

Left Channel

Audio Data

F1 F2

3.183 kHz 10.61 kHz

Figure 31. De-Emphasis Curve

A Channel

Digital

Volume

Control

Frequency

MUTE

AoutA/HP_A

B Channel

Right Channel

Audio Data

Digital

Volume

Control

MUTE

AoutB/HP_B

Figure 32. ATAPI Block Diagram

DS544PP1 43

8. PARAMETER DEFINITIONS

Total Harmonic Distortion + Noise (THD+N)

The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels.

Dynamic Range

The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full scale. This technique ensures that the distortion components are below the noise level and do not affect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307.

Interchannel Isolation

A measure of crosstalk between the left and right channels. Measured for each channel at the converter's output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in decibels.

Interchannel Gain Mismatch

The gain difference between left and right channels. Units in decibels.

CS42L50

Gain Error

The deviation from the nominal full scale analog output for a full scale digital input.

Gain Drift

The change in gain value with temperature. Units in ppm/°C.

9. REFERENCES

1) "How to Achieve Optimum Performance from Delta-Sigma A/D & D/A Converters" by Steven Harris. Paper presented at the 93rd Convention of the Audio Engineering Society, October 1992.

1) "The I2C-Bus Specification: Version 2.1" Philips Semiconductors, January 2000. http://semiconductors.philips.com

44 DS544PP1

10. PACKAGE DIMENSIONS

CS42L50

Figure 33. Package Dimensions

DS544PP1 45

CS42L50

Figure 34. Package Top and Side Views

46 DS544PP1

CS42L50

Figure 35. Package Bottom View

DS544PP1 47

Datasheet CS42L50-KN, CDB42L50 Datasheet (Cirrus Logic)

Specifications and Main Features

Frequently Asked Questions

User Manual

Features

Description

Figure 1. SCLK to LRCK and SDIN, Slave Mode

Figure 2. SCLK to LRCK and SDIN, Master Mode

2. TYPICAL CONNECTION DIAGRAM

Figure 4. CS42L50 Typical Connection Diagram

3. REGISTER QUICK REFERENCE

4. REGISTER DESCRIPTION

4.1 ADC (Address = 0010000)

4.1.2 20DB GAIN BOOST (BOOST)

4.1.3 ANALOG INPUT MULTIPLEXER (AINMUX)

4.1.4 POWER DOWN (PDN)

4.1.5 CONTROL PORT ENABLE (CP_EN)

4.1.7 MASTER CLOCK DIVIDE (MCLKDIV)

4.1.8 MASTER CLOCK RATIO (RATIO)

4.1.9 MASTER MODE (MASTER)

4.1.10 DIGITAL INTERFACE FORMAT (DIF)

4.1.12 LEFT/RIGHT CHANNEL MUTE (MUTE)

4.1.13 SOFT RAMP AND ZERO CROSS ENABLE (SOFT/ZC)

4.1.14 INDEPENDENT VOLUME CONTROL ENABLE (INDVC)

4.1.15 LEFT CHANNEL VOLUME = RIGHT CHANNEL VOLUME (L=R)

4.1.16 HIGH-PASS FILTER FREEZE (HPFREEZE)

4.2 DAC (Address = 0010001)

4.2.2 AUTO-MUTE (AMUTE)

4.2.3 SOFT RAMP AND ZERO CROSS CONTROL (SZC)

4.2.4 POWER DOWN HEADPHONE AMPLIFIER (PDNHP)

4.2.5 POWER DOWN LINE AMPLIFIER (PDNLN)

4.2.6 POWER DOWN (PDN)

4.2.7 CONTROL PORT ENABLE (CP_EN)

4.2.13 BASS BOOST LEVEL (BB)

4.2.14 TREBLE BOOST LEVEL (TB)

4.2.16 BASS BOOST CORNER FREQUENCY (BBCF)

4.2.17 TREBLE BOOST CORNER FREQUENCY (TBCF)

4.2.18 CHANNEL A VOLUME = CHANNEL B VOLUME (A=B)

4.2.19 DE-EMPHASIS CONTROL (DEM)

4.2.20 DIGITAL VOLUME CONTROL BYPASS (VCBYP)

4.2.22 TONE CONTROL MODE (TC)

4.2.23 TONE CONTROL ENABLE (TC_EN)

4.2.24 ATAPI CHANNEL MIXING AND MUTING (ATAPI)

4.2.26 MASTER CLOCK DIVIDE ENABLE (MCLKDIV)

4.2.27 LINE AMPLIFIER GAIN COMPENSATION (LINE)

4.2.28 DIGITAL INTERFACE FORMAT (DIF)

5. PIN DESCRIPTIONS

6. APPLICATIONS

6.1 Grounding and Power Supply Decoupling

6.2 Clock Modes

6.3 EP73xx Serial Port Interface

6.4 De-Emphasis

6.5 Recommended Power-up Sequence

6.6 Optional External Headphone Mute

7. CONTROL PORT INTERFACE

7.1 Memory Address Pointer (MAP)

7.2 INCR (AUTO MAP INCREMENT ENABLE)

7.3 MAP0-3 (MEMORY ADDRESS POINTER)

Figure 5. Control Port Timing

Figure 22. Line Input Test Circuit

Figure 23. Line Output Test Load

Figure 24. Headphone Output Test Load

Figure 25. Left Justified, up to 24-bit data

Figure 26. Right Justified, 16-bit data

Figure 27. Right Justified, 24-bit data

Figure 28. Right Justified, 18-bit data

Figure 29. Right Justified, 20-bit data

Figure 30. I2S, up to 24-bit data

Figure 31. De-Emphasis Curve

Figure 32. ATAPI Block Diagram

8. PARAMETER DEFINITIONS

9. REFERENCES

10. PACKAGE DIMENSIONS

Figure 33. Package Dimensions

Figure 34. Package Top and Side Views

Figure 35. Package Bottom View