Cirrus Logic CS4297-KQ, CS4297-JQ Datasheet

CS4297

Product Data Sheet

FEATURES

n AC’97 1.03 Co mpatible
n Industry Leading Mixed Signal Technology
n 18-bit stereo full-duplex Codec with fixed 48 kHz

sampling rate

n Four analog line-level stereo inputs for connec-

tion from LINE IN, CD, VIDEO and AUX

n T wo analog line-level mono inputs for speaker-

phone and internal PC Beeper

n Mono microphone input switchable from two

external sourc e s

n High quality differential CD input
n Dual Stereo line level outputs
n Extensive power management support

®

n Meets or ex ce e ds Mi cr o sof t’s

audio performance requirements.

ORDERING INFO

CS4297-KQ, 48-pin TQF P, 9x9x1 mm
CS4297-JQ, 48-pin TQFP, 9x9x1 mm

PC’97 and PC’98

CrystalClear™

SoundFusion™ Audio

Codec ’97

DESCRIPTION

The CS4297 is a AC’97 1.03 compatible stereo au­dio Codec designed for PC multimedia systems.
Using the industry leading CrystalClear delta-sig­ma and mixed signal technology, the CS4297
paves the way for PC’97-compliant de sktop, porta­ble, and entertainment PCs, where high-quality
audio is required.

The CS4297, when coupled with a DC’97 PCI au­dio accelerator such as the CS4610, implements a
cost-effective, superior quality, two-chip audio so­lution. The CS4297 Audio Codec ’97 and CS4610
PCI Audio Accelerator are the f irst members of the
SoundFusion family of advanced PCI audio prod­ucts for next generation multimedia PCs.

AC-LINK AND AC’97

REGISTERS

PWR

MGT

SYNC
BIT_CLK
SDATA_OUT
SDATA_IN
RESET#

DS242F5 JUN ‘99

AC-

LINK

AC’97

REGISTERS

Copyright  Cirrus Logic, Inc. 1999

PCM_DATA

GAIN / MUTE CONTROLS

MIXER / MUX SELECTS

PCM_DATA

(All Rights Reserved)

ANALOG INPUT MUX
AND OUTPUT MIXER

ADC

INPUT

18 bits

MUX

OUTPUT

MIXER

DAC
18 bits

Σ

LINE
CD
AUX
VIDEO

MIC1
MIC2

PHONE

PC_BEEP

LINE_OUT
ALT_LINE_OUT
MONO_OUT

TABLE OF CONTENTS

CHARACTERISTICS AND SPECIFICATIONS.....................................................4

Analog Characteristics .................................................................................4

Mixer Characteristics .. ...... ....... ............................................. ...... ..................5

Absolute Maximum Ratings .........................................................................5

Recommended Operating Conditions..........................................................5

Power Down States......................................................................................6

Digital Filter Characteristics .........................................................................6

Digital Characteristics ..................................................................................7

Serial Port Timing.........................................................................................7

Serial Port Timing.........................................................................................8

PARAMETER AND TERM DEFINITIONS ..........................................................10

GENERAL DESCRIPTION .................................................................................12

Overview ...................................................................................................12

Digital Section ...........................................................................................12

AC-Link ..................... ................................................................. .........12

AC’97 Register Interface .....................................................................12

Power Management ............................................................................12

Analog Section ..........................................................................................12

Output Mixer .......................................................................................12

Input Mux ............................................................................................12

Volume Control ...................................................................................12

AC’97 IMPLEMENTATION ................................................................................13

DIGITAL HARDWARE DESCRIPTION ..............................................................15

AC’97 AC-Link ...........................................................................................15

AC-Link Protocol .................................................................................15

AC-Link Serial Data Output Frame ...........................................................15

Slot 0: Serial Data Output Slot Tags ...................................................16

Slot 1: AC’97 Register Address ..........................................................16

Slot 2: AC’97 Register Write Data ......................................................17

Slot 3: Left Channel PCM Playback Data ...........................................17

Slot 4: Right Channel PCM Playback Data .........................................17

AC-Link Audio Input Frame .......................................................................18

Slot 0: Serial Data Input Slot Tag Bits ................................................18

Slot 1: Read-Back Address Port .........................................................19

Slot 2: Read-Back Data Port ...............................................................19

Slot 3: Left Channel PCM Capture Data .............................................19

Slot 4: Right Channel PCM Capture Data ..........................................20

AC-Link Reset Modes ...............................................................................21

Cold AC’97 Reset ...............................................................................21

Warm AC’97 Reset .............................................................................21

AC’97 Register Reset .........................................................................21

AC-Link Protocol Violation - Loss of SYNC ...............................................21

REGISTER INTERFACE.....................................................................................22

Reset Register (Index 00h) .................................................................23

Master Volume (Index 02h) ................................................................23

Alternate Volume (Index 04h) .............................................................23

Master Mono Volume (Index 06h) ......................................................23

PC_BEEP Volume (Index 0Ah) ..........................................................24

Phone_In Volume (Index 0Ch) ...........................................................24

Microphone Volume (Index 0Eh) ........................................................24

Stereo Analog Mixer Input Gain Registers (Index 10 - 18h) ...............25

CS4297

CrystalClear™ SoundFusion™ Audio Codec ’97

2 DS242F5

CS4297

CrystalClear™ SoundFusion™ Audio Codec ’97

Input Mux Select Register (Index 1Ah) ...............................................25

Record Gain Register (Index 1Ch) .....................................................26

Record Gain Mix (Index 1Eh) .............................................................26

General Purpose Register (Index 20h) ...............................................26

Powerdown Control/Status Register (Index 26h) ...............................27

Reserved Registers (Index 28h - 58h) ................................................27

Crystal Revision and Fab ID Register (Index 5Ah) .............................27

Vendor Reserved Registers (Index 5C - 7Ah) ....................................28

Vendor ID1 (Index 7Ch) .....................................................................28

POWER MANAGEMENT .. ...... ....... ...... ....... ...... ...... ....... ...... ....... ...... ....... ..........29

ANALOG HARDWARE DESCRIPTION ............................................................29

Line-Level Inputs .......................................................................................29

Microphone Level Inputs ...........................................................................30

Mono Inputs ..............................................................................................30

Line Level Outputs ....................................................................................31

Miscellaneous Analo g Signal s ................................................. ....... ...... ....32

Power Supplies .........................................................................................32

GROUNDING AND LAYOUT .............................................................................33

PERFORMANCE PLOTS ...................................................................................34

PIN DESCRIPTIONS...........................................................................................39

Digital I/O Pins ....................................................................................39

Analog I/O Pins ..................................................................................40

Filter and Reference Pins ...................................................................42

Power Supplies ..................................................................................43

REFERENCES ................................................................................................... 43

PACKAGE DIMENSIONS...................................................................................44

Contacting Cirrus Logic Support

For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:

http://www.cirrus.com/corporate/contacts/

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Intel is a registered trademark of Intel Corporation.
Preliminary product info rmation describes products which are i n p r od ucti on, b ut for which full characteriza ti on da t a i s not yet available. Advance product i nf or -

mation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information
contained in this document is accurate and reli able. However , the i nformati on is sub ject to change with out no tice and i s provi ded “AS IS” withou t warranty of

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DS242F5 3

CS4297

CrystalClear™ SoundFusion™ Audio Codec ’97

ANALOG CHARACTERISTICS (Standard test conditions unless otherwise noted: T

AVdd = 5.0 V ±5%, DVdd = 3.3 V ±5%; 1 kHz Input Sine wave; Sample Frequency, Fs = 48 kHz; Z
pF load C

= 18 pF load (Note 1); Measurement bandwidth is 20 Hz - 20 kHz, 18-bit linear coding; Mixer registers

DL

= 25° C,

ambient

=10 kΩ/680

AL

set for unity gain.

CS4297-KQ CS4297-JQ

Parameter

(Note 2)

Full Scale Input Voltage
Line Inputs
Mic Inputs (20 dB=0)
Mic Inputs (20 dB=1)

Symbol Path

(Note 3)

A-D
A-D
A-D

0.91

0.91

0.091

1.00

1.00

0.10

UnitMin Typ Max Min Typ Max

V

-

0.91

-

0.91

-

0.091

1.00

1.00

0.10

-

-

-

V
V

RMS
RMS
RMS

Full Scale Output Voltage
Line,Alternate Line, and Mono Outputs D-A 0.91 1.0 1.13 0.91 1.0 1.13

Frequency Response (Note 4)
Analog Ac = ± 0.5 dB
DAC Ac = ± 0.5 dB
ADC Ac = ± 0.5 dB

FR

A-A
D-A
A-D

20
20
20

-

-

-

20,000
20,000
20,000

20
20
20

-

-

-

20,000
20,000
20,000

V

RMS

Hz
Hz
Hz

Dynamic Range

dB FS A

Stereo Analog inputs to LINE_OUT
Mono Analog inputs to LINE_OUT
DAC Dynamic Range
ADC Dynamic Range

DR A-A

A-A
D-A
A-D

90
85
85
85

95
90
90
90

90

-

-

-

-

­85

­87

­85

-

-

-

-

-

dB FS A
dB FS A
dB FS A

DAC SNR (-20 dB FS input w/
CCIR-RMS filter on output) SNR D-A - 63 - - - - dB

Total Harmonic Distortion + Noise
(-3 dB FS input signal):
Line/Alternate Line Output
DAC
ADC (all inputs except phone/mic)
ADC (phone/mic)

THD+N A-A

D-A
A-D
A-D

-94

-

-86

-

-87

-

-87

-

-80

-80

-80

-74

-

-

-

-

­dB FS A

-74

­dB FS A

-74

­dB FS A

-74

-

dB FS A

-74

Power Supply Rejection Ratio
(1 kHz, 0.5 V

w/ 5 V DC offset)(Note 4)

RMS

40 60 - - 40 - dB
Interchannel Isolation 70 87 - - 87 - dB
Spurious Tone (Note 4) - -100 - - -100 - dB FS
Input Impedance (Note 4) 10 - - 10 - - k
External Load Impedance 10 - - 10 - - k
Output Impedance (Note 4) - 730 - - 730 -

Ω
Ω

Ω

Input Capacitance (Note 4) - 5 - - 5 - pF
Vrefout 2.0 2.3 2.5 2.0 2.3 2.5 V

Notes: 1. Z

2. Parameter definitions are given in the

3. Path refers to the signal path used to generate this data. These paths are defined in the

refers to the analog output pin loading and CDL refers to the digital output pin loading.

AL

Term Definitions

Parameter and Term Definitions

section.

section.

Parameter and

4. This specification is guaranteed by silicon characterization, it is not production tested.

4 DS242F5

CS4297

CrystalClear™ SoundFusion™ Audio Codec ’97

MIXER CHARACTERISTICS (for CS4297-KQ only)

Parameter Min Typ Max Unit

Mixer Gain Range Span

Line In, Aux, CD, Video, Mic1 Mic2, Phone, PC Beep

Line Out, Alternate Line Out, Mono Out

Step Size

All volume controls except PC Beep

PC Beep

-

-

-

-

46.5

94.5

1.5

3.0

-

-

-

-

dB
dB

dB
dB

ABSOLUTE MAXIMUM RATINGS (AVss1 = AVss2 = DVss1 = DVss2 = 0 V)

Parameter Min Typ Max Unit

Power Supplies +3.3 V Digital

+5 V Digital

Analog
Total Power Dissipation (Supplies, Inputs, Outputs) - 210 450 mW
Input Current per Pin (Except Supply Pins) -10 - 10 mA
Output Current per Pin (Except Supply Pins) -15 - 15 mA
Analog Input voltage -0.3 - AVdd+

Digital Input voltage -0.3 - DVdd +

Ambient Temperature (Power Applied) -55 - 110 °C

Storage Temperature -65 - 150 °C

-0.3

-0.3

-0.3

-

-

-

6.0

6.0

6.0

0.3

0.3

V
V
V

V

V

RECOMMENDED OPERATING CONDITIONS (AVss1 = AVss2 = DVss1 = DVss2 = 0 V)

Parameter Symbol Min Typ Max Unit

Power Supplies +3.3 V Digital

+5 V Digital

Analog

Operating Ambient Temperature 0 - 70 °C

DVdd1, DVdd2
DVdd1, DVdd2

AVdd1, AVdd2

3.135

4.75

4.75

3.3
5
5

3.465

5.25

5.25

V
V
V

DS242F5 5

CrystalClear™ SoundFusion™ Audio Codec ’97

POWER DOWN STATES

Parameter Min Typ Max Unit

Full Power 3.3 V digital

5 V digital

5 V analog -

ADCs and Input Mux Powerdown (PR0) 3.3 V digital

5 V digital

5 V analog -

DACs Powerdown (PR1) 3.3 V digital

5 V digital

5 V analog -

Analog Mixer Powerdown, Vref on (PR2) 3.3 V digital

5 V digital

5 V analog -

Analog Mixer Powerdown, Vref off (PR3) 3.3 V digital

5 V digital

5 V analog -

AC-Link Powerdown (PR4) 3.3 V digital

5 V digital

5 V analog -

Internal Clock Disable (PR5) 3.3 V digital

5 V digital

5 V analog -

Alternate Line Output Buffer Powerdown (PR6) 3.3 V digital

5 V digital

5 V analog -

CS4297

12.7

21.4

35.0 - mA

5.32

9.80

23.1 - mA

9.25

16.0

30.0 - mA

9.20

16.0

10.7 - mA

5.30

9.80

~0.00 - mA

3.30

6.92

23.0 - mA

0.004

0.005

0.001 - mA

5.30

9.80

20.3 - mA

DIGITAL FILTER CHARACTERISTICS

CS4297-KQ CS4297-JQ

Parameter

Transition Band

Stop Band

0.4 × F

0.6 × F

-

s

--

s

0.6 × F

0.4 × F

s

0.6 × F

0.6 × F

-

s

-- Hz

s

Stop Band Rejection (Note 4, 5) 74 - - 74 - - dB
Out-of-Band Energy (Note 6) - -82 - - -40 - dB
Group Delay (Note 4) - - 1 - - 1 ms

Notes: 5. Stop Band rejection determines filter requirements. Out-of-band rejection determines audible noise.

6. The integrated Out-of-Band generated by the DAC process, during normal PCM audio playback, over
a bandwidth 28.8 kHz to 100 kHz, with respect to a 1 V

DAC output.

RMS

UnitMin Typ Max Min Typ Max

Hz

s

6 DS242F5

CS4297

CrystalClear™ SoundFusion™ Audio Codec ’97

DIGITAL CHARACTERISTICS (AVss = DVss = 0 V (See

Grounding and Layout

section))

Parameter Symbol Min Typ Max Unit

Low level input voltage
High level input voltage
High level output voltage
Low level output voltage

V

il

V

ih

V

oh

V

ol

- -0.16 x DVddV

0.40 x DVdd - - V

0.70 x DVdd 0.99 x DVdd - V

- 0.03 0.10 x DVdd V

Input Leakage Current (AC-link inputs) -10 - 10 µA

Output Leakage Current (Tri-stated AC-link outputs) -10 - 10 µA
Output buffer drive current (Note 4) - 100 400 µA

SERIAL PORT TIMING

Parameter Symbol Min Typ Max Unit

RESET Timing

DVdd 90% maximum value to RESET# inactive pre-delay

(Note 4)
RESET# active low pulse width
RESET# inactive to BIT_CLK start-up delay
1st SYNC active to CODEC READY set

Clocks

BIT_CLK frequency - 12.288 - MHz
BIT_CLK period

BIT_CLK output jitter (depends on XTAL_IN source) - - 750 ps
BIT_CLK high pulse width
BIT_CLK low pulse width

SYNC frequency - 48 - kHz
SYNC period
SYNC high pulse width
SYNC low pulse width
SYNC active to RESET# inactive pre-delay

Data Setup and Hold

Output Propagation delay from rising edge of BIT_CLK
Output hold from falling edge of BIT_CLK
Input setup time from falling edge of BIT_CLK
Input hold time from falling edge of BIT_CLK
Input Signal rise time
Input Signal fall time
Output Signal rise time (Note 4)
Output Signal fall time (Note 4)

T

Vdd2rst#

T

rst_low

T

rst2clk

T

sync2crd

T

clk_period

T

clk_high

T

clk_low

T

sync_period

T

sync_high

T

sync_low

T

rst2snyc

T

prop

T

ohold

T

isetup

T

ihold

T

irise

T

ifall

T

ofall

T

ofall

1.5 - - ms

1.0 - -

µ

- 42.7 - ms

- 40.6 -

µ

- 81.4 - ns

- 40.7 - ns

- 40.7 - ns

- 20.8 -

µ

-1.3-µs

- 19.5 -

µ

- - 250 ms

-68ns

5--ns

10 - - ns

0--ns
2-6ns
2-6ns
246ns
246ns

s

s

s

s

DS242F5 7

SERIAL PORT TIMING (Continued)

Misc. Timing Parameters

End of Slot 2 to BIT_CLK, SDATA_IN low (PR4)
SYNC pulse width (PR4)
SYNC inactive (PR4) to BIT_CLK start-up delay
Setup to trailing edge of RESET# (test modes) (Note 4)
Rising edge of RESET# to Hi-Z delay (Note 4)

BIT_CLK

T

rst_low

RESET#

T

vdd2rst#

CS4297

CrystalClear™ SoundFusion™ Audio Codec ’97

T

s2_pdown

T

sync_pr4

T

sync2clk

T

setup2rst

T

off

- 16.24 16.36

1.0 - -

162.8 244 - ns
15 - - ns

- - 25 ns

T

rst2clk

µ

s

µ

s

Vdd

SYNC

BIT_CLK

SYNC

BIT_CLK

T

T

orise

irise

Power Up Timing

T

clk_highTclk_low

T

sync_high

T

T

ifall

sync_period

Clocks

T

clk_period

T

T

rst2sync

sync_low

T

ifall

SYNC

T

sync2crd

CODEC_READY

Codec Ready from Startup or Fault C on di t i on

8 DS242F5

CS4297

CrystalClear™ SoundFusion™ Audio Codec ’97

BIT_CLK

SDATA_IN

T

co

SDATA_OUT,
SYNC

Data Setup and Hold

BIT_CLK

T

setup

T

hold

SDATA_OUT

SDATA_IN

SYNC

Slot 1 Slot 2

Write to 0x20 Data PR4 Don’t Care

T

s2_pdown

T

PR4 Powerdown

RESET#

T

setup2rst

SDATA_OUT,
SYNC

T

off

sync_pr4

T

sync2clk

SDATA_IN,

Hi-Z

BIT_CLK

Test Mode

DS242F5 9

PARAMETER AND TERM DEFINITIONS

AC’97 Specification

Refers to the Audio Codec ‘97 Component Specification Ver 1.03 published by Intel

Corporation [1].

AC’97 Controller

Refers to the control chip which interfaces to the CS4297’s AC-Link. This has been also called
“DC’97” [1].

‘set’

Refers to a digital value of Vcc, “1”, or “high”.

‘clear’ or ‘cleared’

Refers to a digital value of GND, “0” or “low”.

AC’97 Registers

CS4297

CrystalClear™ SoundFusion™ Audio Codec ’97

®

Refers to the 64-field register map defined in the AC’97 Specification.

ADC

Refers to a single Analog-to-Digital converter in the CS4297. “A DCs” refers to the stereo pair
of Analog-to-Digital converters.

DAC

A single Digital-to-Analog converter in the CS4297. “DACs” refers to the stereo pair of
Digital-to-Analog converters.

Codec

Refers to the set of ADCs, DACs, and Analog mixer portions of the CS4297.

FFT

Fast Fourier Transform.

Resolution

The number of bits in the output words to the DACs, and in the input words to the ADCs.

Differential Nonlinearity

The worst case deviation from the ideal code width. Units in LSB.

dB FS A

dB FS is defined as dB relative to full-scale. The “A” indicates an A weighting filter was used.

10 DS242F5

CS4297

CrystalClear™ SoundFusion™ Audio Codec ’97

Frequency Response (FR)

FR is the deviation in signal level verses frequency. The 0 dB reference point is 1 kHz. The
amplitude corner, Ac, lists the maximum deviation in amplitude above and below the 1 kHz
reference point. The listed minimum and maximum frequencies are guaranteed to be within the
Ac from minimum frequency to maximum frequency inclusive.

Dynamic Range (DR)

DR is the ratio of the RMS full-scale signal level divided by the RMS sum of the noise floor,
in the presence of a signal, available at any instant in time (no change in gain settings between
measurements). Measured over a 20 Hz to 20 kHz bandwidth with units in dB FS A.

Total Harmonic Distortion plus Noise (THD+N)

THD+N is the ratio of the RMS sum of a ll non-fundamental frequency components, divided by
the RMS full-scale signal level. It is tested using a -3 dB FS input signal and is measured over
a 20 Hz to 20 kHz bandwidth with units in dB FS A.

Signal to Noise Ratio (SNR)

SNR, similar to DR, is the ratio of an arbitrary sinusoidal input signal to the RMS sum of the
noise floor, in the presence of a signal. It is measured over a 20 Hz to 20 kHz bandwidth with
units in dB.

Interchannel Isolation

The amount of 1 kHz signal present on the output of the grounded AC-coupled line input
channel with 1 kHz 0 dB signal present on the other line input channel. Units in dB.

Interchannel Gain Mismatch

For the ADCs, the difference in input voltage to get and equal code on both channels. For the
DACs, the difference in output voltages for each channel when both channels are fed the same
code. Units in dB.

PAT HS : [4 ]

A-D: Analog in, through the ADC, onto the serial link.

D-A: Serial interface inputs through the DAC to the analog output

A-A: Analog in to Analog out (analog mixer)

DS242F5 11

CS4297

CrystalClear™ SoundFusion™ Audio Codec ’97

GENERAL DESCRIPTION
Overview

The CS4297 is a mixed-signal serial Codec based
on the AC’97 Specification. It is designed to be
paired with a digital controller, typically located on

the PCI bus. The AC’97 Controller is responsible
for all communications between the CS4297 and
the rest of the system. The CS4297 functions as an
analog mixer, a stereo ADC, a stereo DAC, and a
control and digital audio stream interface to the
AC’97 Controller.

The CS4297 contains two distinct functional sec­tions: Digital and Analog. The Digital section in­cludes the AC-Link registers, power management
support, SYNC detection circuitry, and AC-Link
serial port interface logic. The Analog section in­cludes the analog input multiplexor (mux), stereo
output mixer, mono output mixer, stereo ADCs,
stereo DACs, and analog volume controls.

Digital Section

AC-Link

The AC-Link is the 5-wire digital interface to the
AC’97 Controller chip. The CS4297 generates the
BIT_CLK and the SDATA_IN signals. The AC’97
Controller must drive the SYNC, SDATA_OUT
and RESET# signals. Please refer to the AC-Link
timing section for the timing characteristics of the
interface. The interface uses the SYNC signal,
which is synchronous with BIT_CLK, to align the
data within the frame. The AC-Link signals may be
referenced to either 5 Volts or 3.3 Volts. The
CS4297 should use the same digital supply voltage
as the AC’97 Controller chip.

AC’97 Register Interface

The CS4297 implements the AC’97 Registers in
accordance with the AC’97 Specification. See the
Register Interface section for details on the
CS4297’s register set.

Power Management

The CS4297 supports a number of different power
down modes. They are accessed through register
0x26h of the CS4297 register interface. Please refer
to the Power Management section of the data sheet.

Analog Section

Please refer to Figure 1, Mixer diagram, for a high
level graphical representation of the CS4297 ana­log mixer structure.

Output Mixer

There are two output mixers on the CS4297. The
stereo output mixer sums together the analog inputs
to the CS4297 according to the settings in the vol­ume control registers. The mono output mixer gen­erates a monophonic sum of the left and right
channels from the stereo output mixer. However,
the mono output mixer does not include the
PC_BEEP and PHONE signals which are included
in the stereo output mix. The stereo output mix is
sent to the LINE_OUT and ALT_LINE_OUT out­put pins of the CS4297. The mono output mix is
sent to the MONO_OUT output pin on the CS4297.

Input Mux

The input multiplexor controls which analog input
is sent to the ADCs. The output of the input mux is
converted to stereo 18-bit digital PCM data and
sent to the AC’97 Controller chip in Slots 3 and 4
of the AC-Link SDATA_IN signal.

Volume Control

The volume control registers of the AC’97 Register
interface control analog input level to the input
mixer, the master volume level, and the alternate

12 DS242F5

CS4297

CrystalClear™ SoundFusion™ Audio Codec ’97

volume level. All analog volume controls, except
PC_BEEP, implement controlled volume steps at
nominally 1.5 dB per step. PC_BEEP uses 3 dB
steps. The analog inputs allow a mixing range of
+12 dB of signal gain to -34.5 dB of signal a ttenu­ation. The analog output volume controls allow
from 0 dB to -94.5 dB of attenuation. The
PC_BEEP input volume control allows from 0 dB
to -45 dB of attenuation.

AC’97 IMPLEMENTATION

The CS4297 implements an AC’97 compliant de­sign as defined in the Intel Audio Codec 97 Speci­fication Version 1.03. Due to certain design trade­offs and implementation decisions, the CS4297 dif-

fers from the AC’97 Specification in a a few minor
ways. The following list captures the specification
deviations and the implementation decisions made
to resolve ambiguities.

1. The rising edge of RESET# must occur at least

1.5 ms after the digital power supply DVdd reaches
90% of maximum value.

2. The digital input voltage threshold levels are
specified as percentages of the Vdd digital power
supply and are TTL level compatible. Min Vih =

0.4 x Vdd, Max Vil = 0.16 x Vdd.

3. The delay between setting the PR4 bit to power­ing down the AC-Link interface is implemented as

16.24 µs.

Figure 1. Mixer Diagram

DS242F5 13

CS4297

CrystalClear™ SoundFusion™ Audio Codec ’97

4. The digital outputs are specified with a 18 pF ca­pacitive load.

5. The nominal Vrefout level is 2.2 V.

6. All analog mixer input and output paths are de­signed to achieve greater than 90 dBFSA Dynamic
Range.

7. All stereo-to-mono mixer stages contain a scale
factor of -6 dB to prevent output clipping of the
summed mono signal.

8. When the analog mixer is powered down, the
control registers for Record Select and Record
Gain are frozen. The analog mixer stage must be
powered up to gain access to these registers.

9. The Headphone Output pins have been imple­mented as an Alternate Line Output. These pins
must drive loads greater than 10 kΩ, just as the
Line Outputs.

10. Reserved bits in the AC’97 serial data input
stream may return a ‘set’ or a ‘cleared’ value.

11. The Vref pin defined in the AC’97 Specifica­tion has been renamed to REFFLT. This pin is used
for internal filtering and should not be used as an
external circuit bias voltage. The Vrefout pin is
used to supply biasing voltages to external analog
circuitry. This pin is not capable of supplying 5 mA
of bias current as the specification indicates.

14 DS242F5