l Sample rates up to 100 kHz
l Pop-free Digital Output Volume Controls
- 90.5 dB range, 0.5 dB resolution (182 levels)
- Variable smooth ramp rate, 0.125 dB steps
l Mute Control pin for off-chip muting circuits
l On-chip Anti-alias and Output Filters
l De-emphasis filters for 32, 44.1 and 48 kHz
I
SCL/CCLKSDA/CDINVD
Description
The CS4228A codec provides two analog- to-digital and
six digital-to-analog delta- sigma converters, along with
volume controls, in a compact 28-pin SSOP device.
Combined with an IEC958 (SPDIF) receiver (like the
CS8414) and surround so und decoder (such as one of
the CS492x or CS 493xx families), it is ide al for use in
DVD player, A/V recei ver and car audio s ystems supporting multiple s tandards such as Dolby Digital AC-3,
AAC, DTS, Dolby ProLogic, THX, and MPEG.
A flexible serial audio interface al lows operation in Left
Justified, Right Justified, I
ORDERING INFORMATION
CS4228A-KS -10° to +70° C 28-pin SSOP
CDB4228AEvaluation Board
5.3 Chip Control .....................................................................................................................22
5.4 ADC Control .....................................................................................................................22
5.5 DAC Mute1 Control ..........................................................................................................23
5.6 DAC Mute2 Control ..........................................................................................................23
CS4228A
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts/
Dolby, Pro Logic, and AC-3 are trademarks of Dolby Laboratories Licensing Corporation.
Preliminary product inf o rmation describes products whi ch are in production, but for which full character izat i on da t a is not yet available. Advance product infor -
mation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best effort s to ensure that the information
contained in this document i s accurat e and reli able. However , t he infor mation is subje ct to chang e without noti ce and is provi d ed “AS IS” without warrant y of
any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other ri g ht s
of third parties. This document is the pro perty of Cirrus Logi c, Inc. and i mplie s no licen se under patents, copyrights, tr ademarks, or trade secre ts. No part of
this publication may be copied, reproduced , stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or
otherwise) without the pr i or writ ten consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or di sk may be pri nt ed for use by the user. However, no
part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical,
photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Furthermore, no part of this publication may be used as a basis for manufacture
or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing
in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.
2DS511PP1
5.7 DAC De-emphasis Control .............................................................................................. 24
5.8 Digital Volume Control .....................................................................................................24
5.9 Serial Port Mode .............................................................................................................. 25
5.10 Chip Status .................................................................................................................... 25
Figure 6. Optional Line Input Buffer ............................................................................................12
Figure 7. Passive Output Filter with Mute ................................................................................... 13
Figure 8. Butterworth Output Filter with Mute ............................................................................. 13
Figure 9. I
Figure 10.Left Justified Serial Audio Formats .............................................................................. 16
Figure 11.Right Justified Serial Audio Formats ............................................................................ 16
Figure 12.One Line Data Serial Audio Format ............................................................................. 16
Figure 13.Control Port Timing, SPI Slave Mode Write ................................................................. 17
Figure 14.Control Port Timing, Two Wire Slave Mode Write ....................................................... 18
Figure 15.Control Port Timing, Two Wire Slave Mode Read ....................................................... 18
2
S Serial Audio Formats ............................................................................................. 15
CS4228A
LIST OF TABLES
Table 1. Serial Audio Port Input Channel Allocations ................................................................... 15
Table 2. Common Master Clock Frequencies.............................................................................. 27
DS511PP13
1. CHARACTERISTICS AND SPECIFICATIONS
CS4228A
ANALOG CHARACTERISTICS (Unless otherwise specified T
Scale Input Sine wave, 984.375 Hz; Fs = 48 kHz BRM, 96 kHz HRM; Measurement Bandwidth is 20 Hz to 20 kHz;
Local components as shown in Figure 5; SPI control mode, Left Justified serial format, MCLK = 256 x Fs for BRM,
128 x Fs for HRM, SCLK = 64 x Fs)
Base Rate ModeHigh Rate Mode
ParameterSymbolMinTypMaxMinTypMaxUnits
Analog Input Characteristics
Dynamic Range, -60 dBFS input(A weighted)
Total Harmonic Distortion + Noise (Note 1)
Interchannel Isolation
Interchannel Gain Mismatch
Offset Error (with high pass filter)
Full Scale Input Voltage (Differential):
Gain Drift
Input Resistance
Input Capacitance
A/D Decimation Filter Characteristics
Passband (Note 3)
Passband Ripple
Stopband(Note 3)
Stopband Attenuation(Note 4)
Group Delay
Group Delay Variation vs. Frequency
Notes: 1. Referenced to typical full-scale differential input voltage (2 Vrms), Tested with -1 dBFS input.
2. Filter response is not tested but is guaranteed by design.
3. Filter characteristics scale with output sample rate.
4. The analog modulator samples the input at 128 times Fs. For example, input the sample rate is
6.144 MHz for an output sample rate of 48 kHz. There is no rejection of input signals which are multiples
of the sampling frequency (n × 6.144 MHz ±20.0 kHz where n = 0,1,2,3...).
5. High Pass Filter characteristics are specified for Fs=44.1 KHz.
Specifications are subject to change without notice
4DS511PP1
ANALOG CHARACTERISTICS (Continued)
ParameterSymbolMinTypMaxMinTypMaxUnits
Analog Output Characteristics
Dynamic Range, -60 dBFS input(A weighted)
Total Harmonic Distortion + Noise
Interchannel Isolation
Interchannel Gain Mismatch
Offset Voltage
Full Scale Output Voltage
Gain Drift
Analog Output Load
Minimum Load Resistance:
Maximum Load Capacitance:
Combined Digital and Analog Filter Characteristics
Frequency Response10 Hz to 20 kHz
Deviation from Linear Phase
Passband: to 0.01 dB corner(Notes 6, 7)
Passband Ripple(Note 7)
Stopband(Notes 6, 7)
Stopband Attenuation(Notes 5, 8)
Group Delay (Fs = Input Word Rate)
Analog Loopback Performance
Signal-to-noise Ratio
(CCIR-2K weighted, -20 dB FS input)
Notes: 6. The passband and stopband edges scale with frequency. For input word rates, Fs, other than 44.1 kHz,
the 0.01 dB passband edge is 0.4535×Fs and the stopband edge is 0.5465×Fs.
7. Digital filter characteristics.
8. Measurement bandwidth is 10 Hz to 3 Fs.
Specifications are subject to change without notice
DS511PP15
ANALOG CHARACTERISTICS (Continued)
Power Supply
Power Supply Current Operating
VA = VD = VL = 5 VVA
Power Down: RST
low, Clocks running
Power Supply Rejection(1 kHz, 10 mV
SymbolMinTypMaxMinTypMaxUnits
VL
VD
VA
VL
VD
)
rms
CS4228A
Base Rate ModeHigh Rate Mode
-
37
-
0.5
-
85
-
0.5
-
0.2
-
0.5
-50-50dB
42
2
99
1
0.5
1
-
37
-
0.5
-
85
-
0.5
-
0.2
-
0.5
42
2
99
1
0.5
1
mA
mA
mA
mA
mA
mA
DIGITAL CHARACTERISTICS Unless otherwise specified (T
5.25V)
ParameterSymbolMinMaxUnits
High-level Input Voltage
Low-level Input Voltage
High-level Output Voltage at VL = 5 V
= -2.0 mA
I
0
= -100 uA
I
0
VL = 2.5 V
= -2.0 mA
I
0
Low-level Output Voltage at VL = 5 V
= 2.0 mA
I
0
= 100 uA
I
0
VL = 2.5 V
= -2.0 mA
I
0
Input Leakage Current (Digital Inputs)
Output Leakage Current (High-Impe danc e Digi tal Outputs)
SWITCHING CHARACTERISTICS (T
= 25°C; VA = VD + 5V,VL = 2.375 to 5.25V, CL 30 pF)
A
ParameterSymbolMinTypMaxUnits
Audio ADC's and DAC's Sample RateBRM
HRM
MCLK Frequency
MCLK Duty CycleBRM
MCLK =128, 384 Fs
MCLK = 256, 512 Fs
HRM
MCLK = 64, 192 Fs
MCLK = 128, 256 Fs
V
IH
V
IL
V
OH
V
OL
Fs30
= 25 °C; VA = VD + 5V,VL = 2.375 to
A
0.7xVL-V
0.3xVLV
VL - 1.0
VL - 0.7
0.9 X VL
-
-
-
-
-
-
0.4
0.2
0.4
V
V
V
V
V
V
-10µA
-10µA
60
-
-
50
100
kHz
kHz
3.84-25.6MHz
TBD
40
TBD
40
50
50
50
50
TBD
60
TBD
60
%
%
%
%
6DS511PP1
SWITCHING CHARACTERISTICS (Continued)
Figure 1. Serial Audio Port Master Mode Timing
ParameterSymbolMinTypMaxUnits
Low Time(Note 9)
RST
SCLK Falling Edge to SDOUT Output Valid(DSCK=0)
LRCK Edge to MSB Valid
SDIN Setup Time Before SCLK Rising Edge
SDIN Hold Time After SCLK Rising Edge
Master Mode
SCLK Falling to LRCK Edge
SCLK Duty Cycle
Slave Mode
SCLK Period
SCLK High Time
SCLK Low Time
SCLK rising to LRCK Edge(DSCK=0)
LRCK Edge to SCLK Rising(DSCK=0)
t
dpd
t
lrpd
t
t
t
mslr
t
sckw
t
sckh
t
sckl
t
lrckd
t
lrcks
ds
dh
CS4228A
1- -ms
-50ns
-20ns
-10ns
-30ns
+10-ns
50-%
--ns
50--ns
50--ns
25--ns
25--ns
Notes: 9. After powering up the CS4228A, RST
SCLK*
(output)
t
mslr
LRCK
(output)
SDOUT
should be held low until the power supplies and clocks are settled.
LRCK
(input)
SCLK*
(input)
SDIN1
SDIN2
SDIN3
SDOUT
*SCLK shown for DSCK = 0.
SCLK inverted for DSCK = 1.
t
lrckd
t
lrpd
t
lrcks
t
sckh
t
t
dh
ds
MSB
t
sckw
t
sckl
t
dpd
MSB-1
Figure 2. Serial Audio Port Slave Mode Timing
DS511PP17
CS4228A
SWITCHING CHARACTERISTICS - CONTROL PORT (TA = 25° C, VA = VD = +5 V,
VL =2.375 to 5.25 V; Inputs: logic 0 = DGND, logic 1 = VL, C
ParameterSymbolMinMaxUnits
SPI Mode
(SDOUT > 47 kΩ to GND)
CCLK Clock Frequency
CS
High Time Between Transmissions
CS
Falling to CCLK Edge
CCLK Low Time
CCLK High Time
CDIN to CCLK Rising Setup Time
CCLK Rising to DATA Hold Time (Note 10)
Rise Time of CCLK and CDIN (Note 11)
Fall Time of CCLK and CDIN (Note 11)
Notes: 10. Data must be held for sufficient time to bridge the transition time of CCLK.
11. For F
SCK
< 1 MHz
= 30 pF)
L
f
t
t
t
t
t
t
sck
csh
css
scl
sch
dsu
dh
t
r2
t
f2
-6MHz
1.0µs
20ns
66ns
66ns
40ns
15ns
100ns
100ns
CS
CCLK
CDIN
t
t
css
r2
t
t
scl
t
t
f2
dsu
sch
t
dh
Figure 3. SPI Control Port Timing
t
csh
8DS511PP1
CS4228A
SWITCHING CHARACTERISTICS - CONTROL PORT (T
VL=2.375 to 5.25 V; Inputs: logic 0 = DGND, logic 1 = VL, C
= 30 pF)
L
= 25° C; VA = VD = +5 V,
A
ParameterSymbolMinMaxUnits
Two Wire Mode
SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling (Note 12)
SDA Setup Time to SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
(SDOUT < 47 kΩ to ground)
f
t
t
hdst
t
low
t
high
t
sust
t
hdd
t
sud
t
susp
scl
buf
t
t
-100kHz
4.7µs
4.0µs
4.7µs
4.0µs
4.7µs
0µs
250ns
r
f
4.7µs
Notes: 12. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
1µs
300ns
SDA
SCL
StopStart
t
buf
t
hdst
t
t
high
low
t
hdd
t
sud
Figure 4. Two Wire Control Port Timing
Repeated
Start
t
sust
t
hdst
Stop
t
f
t
r
t
susp
DS511PP19
CS4228A
ABSOLUTE MAXIMUM RATINGS (AGND, DGND = 0 V, all voltages with respect to 0 V.)
ParameterSymbolMinTypMaxUnits
Power Supplies Digital
Analog
Interface
Input Current (Note 13)
Analog Input Voltage (Note 14)
Digital Input Voltage Input Pins
Bidirectional Pins
(Notes 14 and 15)
Ambient Temperature (Power Applied)
Storage Temperature
Notes: 13. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause
SCR latch-up.
14. The maximum over or under voltage is limited by the input current.
15. Bidirectional pins configured as inputs.
VD
VA
VL
-0.3
-0.3
-0.3
--±10mA
-0.7-VA + 0.7V
-0.7
-0.7
-55-+125°C
-65-+150°C
-
-
-
-
-
6.0
6.0
6.0
VL + 2.5
VL + 0.7
V
V
V
V
V
V
Warning:Operation at or beyond these limits may result in permanent damage to the device. Normal operation
is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS (AGND, DGND = 0 V, all voltages with respect
to 0 V.)
ParameterSymbolMinTypMaxUnits
Power Supplies Digital
Analog
Interface
Operating Ambient Temperature
VD
VA
VL
T
A
4.75
4.75
2.375
-102570°C
5.0
5.0
-
5.25
5.25
5.25
V
V
V
10DS511PP1
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