Cirrus Logic CS4225-YU, CS4225-KL, CS4225-BL, CDB4225 Datasheet

Digital Audio Conversion System

CS4225

Features

l

Stereo 16-bit A/D Converters

l

Quad 16-bit D/A Converters

l

Sample Rates From 4 kHz to 50 kHz

l

>100 dB DAC Signal-to-Noise Ratio

l

Variable Bandwidth Auxiliary 12-bit A/D

l

Programmable Input Gain & Output
Attenuation

l

+5V Power Supply

l

On-chip Anti-aliasing and Output Smoothing
Filters

l

Error Correction and De-Emphasis

I

AD2/CDIN/CKF1

Serial Audio Data Interface

MUX

SDA/CDOUT/CKF0

Control Port

Digital Filters

with De-Emphasi s

Digital

Filters

Clock Osc/

Divider

DAC#1

DAC#2

DAC#3

DAC#4

Left

ADC

Right

ADC

PLL

DEM

RST-PDN

LRCK

SCLK
SDIN1
SDIN2

SDOUT1
SDOUT2

DIF/HOLD

AINAUX

SCL/CCLK/IF0

12-Bit

ADC

Description

The CS4225 is a single-chip, stereo analog-to-digital
and quad digital-to-analog converter using delta-sigma
conversion techniques. Applications include CD-quality
music, FM radio quality music, telephone-quality
speech. Four D/A converter s make the CS42 25 ideal for
surround sound and automotive appl ications.

The CS4225 is supplied in a 44-pin plastic package with
J-leads (PLCC) or as a die.

ORDERING INFORMATION

CS4225-KL 0° to 70° C 44-pin PLCC
CS4225-BL -40° to 85° C 44-pin PLCC
CS4225-YU -40° to 85° C die
CDB4225 Evaluation Board

AD3/CS/IF1

Reference

Volume

Control

Volume

Control

Volume

Control

Volume

Control

Input

Gain

Auxiliary Digital Input

CMOUTVREF

Voltage

Output Stage

Analog Low Pass and

VD+

VA+

H/S

AOUT1
AOUT2

AOUT3
AOUT4

2

IS0/AD0,
IS1/AD1

AIN1L
AIN1R

MUX

Input

AIN2L
AIN2R

AIN3L
AIN3R

AGND2

OVL

CLKOUT XTI XTO

Preliminary Product Information

Cirrus Logic, Inc.
Crystal Semiconductor Products Division

P.O. Box 17847, Austin, Texas 78760
[phone] FAX: [phone]
http://www.crystal.com

FILT

This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.

CL CR DAT AUX

Copyright  Cirrus Logic, I nc. 1997

(All Rights Reserv ed)

SCLKAUX AGND1 DGND

LRCKAUX

NOV ‘93

DS86PP8

1

CS4225

ANALOG CHARACTERISTICS( T

Word Clock = 48 kHz (PLL in use); Measurement Bandwidth is 20 Hz to 20 kHz; Local components as shown
in "Recommended Connection Diagram"; SPI mode, Format 0, unless otherwise specified.)

Parameter * Symbol Min Typ Max Units

Analog Input Characteristics

ADC Resolution Audio channels 16 - - Bits

ADC Differential Nonlinearity - - ±0.9 LSB
Dynamic Range Audio channels(A weighted): 82 85 - dB
Total Harmonic Distortion + Noise (A weighted) THD+N - -85 -82 dB
Interchannel Isolation - 85 - dB
Interchannel Gain Mismatch - - .1 dB
Frequency Response Audio channels(0 to 0.454 Fs): -3.0 - +0.2 dB
Programmable Input Gain -0.2 - 46.7 dB
Gain Step 1.3 1.5 1.7 dB
Offset Error - 10 - LSB
Full Scale Input Voltage (Auxiliary and Audio channels): 2.66 2.8 2.94 V
Gain Drift - 100 - ppm/°C

- Minimum gain setting (0 dB); unless otherwise specified.

= 25°C; VA+, VD+ = +5V; Full Scale Input Sine wave, 1 kHz;

A

Auxiliary channel 12 Bits

pp

Input Resistance (Note 1) 10 - - kΩ
Input Capacitance - - 15 pF
CMOUT Output Voltage 1.9 2.1 2.3 V

Notes: 1. Input resistance is for the input selected. Non-s elected inputs have a very high (>1MΩ) input

resistance. The input resistance will vary with gain value selected, but will always be greater
than the min. value specified.

Parameter definitions are given at the end of this data sheet.

*

Specifications are subject to change without notice.

2 DS86PP8

ANALOG CHARACTERISTICS (Continued)

Parameter * Symbol Min Typ Max Units

CS4225

Analog Output Characteristics

DAC Resolution 16 - - Bits
DAC Differential Nonlinearity - - ±0.9 LSB
Total Dynamic Range (DAC muted,A weighted) 100 - - dB
Total Harmonic Distortion (Note 2) THD - - 0.01 %
Instantaneous Dynamic Range 85 88 - dB

(DAC not muted, Note 2, A weighted)
Interchannel Isolation (Note 2) - 85 - dB
Interchannel Gain Mismatch - - 0.2 dB
Frequency Response (0 to 0.476 Fs) -3.0 - +0.2 dB
Programmable Attenuation (All Outputs) 0.2 - -117 dB
Attenuation Step 0.88 1.0 1.12 dB
Offset Voltage - 10 - mV
Full Scale Output Voltage (Note 2) 2.66 2.8 2.94 V
Gain Drift - 100 - ppm/°C
Deviation from Linear Phase - - 5 Degrees
Out of Band Energy (Fs/2 to 2Fs) - -60 - dB

- Minimum Attenuation; Unless Otherwise Specified.

pp

Analog Output Load Resistance: 8 - - kΩ

Capacitance: - - 100 pF

Power Supply

Power Supply Current Operating - 120 TBD mA

Power Down - 1 TBD mA

Power Supply Rejection (1 kHz) - 40 - dB

Notes: 2. 10 k Ω, 100 pF load.

DS86PP8 3

CS4225

16-Bit Audio A/D Decimation Filter Characteristics (See graphs towards the

end of this data sheet)

Parameter Symbol Min Typ Max Units

Passband ( to -3 dB cor ner) (Fs is conversion freq.) 0 - 0.454Fs Hz
Passband Ripple - - ±0.1 dB
Transition Band 0.40Fs - 0.60Fs Hz
Stop Band ≥ 0.60Fs - - Hz
Stop Band Rejection 75 - - dB
Group Delay - 10/Fs - s
Group Delay Variation vs. Frequency - - 0.0 µs

D/A Interpolation Filter Characteristics (See graphs toward the end of this data sheet)

Parameter Symbol Min Typ Max Units

Passband (to -3 dB corner) (Fs is conversion freq.) 0 - 0.476Fs Hz
Passband Ripple - - ±0.1 dB
Transition Band 0.442Fs - 0.567Fs Hz
Stop Band ≥0.567Fs - - Hz
Stop Band Rejection 50 - - dB
Stop Band Rejection 57 - - dB

with Ext. 2Fs RC filter
Group Delay - 12/Fs - s
Group Delay Variation vs. Frequency - - TBD µs

4 DS86PP8

CS4225

SWITCHING CHARACTERISTICS (T

= 25°C; VA+, VD+ = +5V, outputs loaded with 30pF)

A

Parameter Symbol Min Typ Max Units

SCLK period t
SCLK high time t
SCLK low time t

sckw

sckh

sckl

80 - - ns
25 - - ns

25 - - ns
Input Transition Time 10% to 90% points - - 10 ns
Input Clock Frequency Crystals 32 - 26000 kHz

XTI 32 - 26000 kHz
Input Clock (XTI) low time 30 - - ns
Input Clock (XTI) high time 30 - - ns
Input clock jitter tolerance - 500 - ps
PLL clock recovery frequency LRCK, LRCKAUX 32 - 50 kHz

SCLK, SCLKAUX 2.048 - 3.200 MHz
CLKOUT duty cycle 45 50 55 %
Audio ADC’s & DAC’s sample rate Fs 4 - 50 kHz
RST-PDN low time (Note 5) 500 - - ns
MSB output from LRCK edge (Format 1 and 3) t
SDOUT output from SCLK edge t
SDIN setup time before SCLK edge t
SDIN hold time after SCLK edge t
LRCK to SCLK delay (slave mode) t
LRCK to SCLK setup (slave mode) t
LRCK to SCLK alignment (master mode) t

Note: 5. After Powering up the CS4225,

RST-PDN should be held low for 50 ms to allow the voltage

lrpd
dpd

ds

dh
lrckd
lrcks

mslr

- - 50 ns

- - 50 ns

- - 35 ns

- - 35 ns
35 - - ns
35 - - ns

-20 - 20 ns

reference to settle.

LRCK

LRCKAUX

SCLK*

SCLKAUX*

(output)

t

mslr

LRCK

LRCKAUX

(output)

Audio Ports Master Mode Timing

(input)

SCLK*

SCLKAUX*

(input)

SDIN1
SDIN2

DATAUX

SDOUT1
SDOUT2

*Active edge of SCLK, SCLKAUX depends on selected format.

t

lrckd

t

lrpd

t

lrcks

t

t

sckh

t

t

ds

dh

MSB MSB-1

t

sckw

sckl

t

dpd

Audio Ports Slave Mode and Data I/O timing

DS86PP8 5

SWITCHING CHARACTERISTICS - CONTROL PORT

(TA = 25oC VD+, VA+ = 5V±10%; Inputs: logic 0 = DGND, logic 1 = V D+, CL = 30pF)

Parameter Symbol Min Max Units

(H/

SPI Mode

CCLK Clock Frequency f
CS High Time Between Transmissions t
CS Falling to SCK Edge t
CCLK Low Time t
CCLK High Time t
CDIN to CCLK Rising Setup Time t
CCLK Rising to DATA Hold Time CDIN (Note 9) t
CCLK Falling to CDOUT stable t
Rise Time of CDOUT t
Fall Time of CDOUT t
Rise Time of CCLK and CDIN t
Fall Time of CCLK and CDIN t

Notes: 9. Data mus t be held for sufficient time to bridge the transition time of CCLK.

S=0)

sck
csh
css

scl

sch

dsu

dh

01MHz

1.0 µs
20 ns

500 ns
500 ns
250 ns

50 ns

pd

r1
f1
r2 100 ns
f2

CS4225

250 ns

25 ns
25 ns

100 ns

CS

CCLK

CDIN

CDOUT

t

css

t

r2

t

t

sch

scl

t

t

f2

dsu

t

t

dh

pd

t

csh

6 DS86PP8

SWITCHING CHARACTERISTICS - CONTROL PORT

(TA = 25oC; VD+, VA+ = 5V±10%;Inputs: logic 0 = DG ND, logic 1 = VD+, CL = 20pF)

Parameter Symbol Min Max Units

(H/

I2C® Mode

S = floating) Note 10

CS4225

SCL Clock Frequency f
Bus Free Time Between Transmissions t
Start Condition Hold Time (prior to first clock pulse) t
Clock Low Time t
Clock High Time t
Setup Time for Repeated Start Condition t
SDA Hold Time from SCL Falling Note 11 t
SDA Setup Time to SCL Rising t
Rise Time of Both SDA and SCL Lines t
Fall Time of Both SDA and SCL Lines t
Setup Time for Stop Condition t

2C®

Notes: 10. Use of the I

2C®

is a registered trademark of Philips Semiconductors.

I

bus interface requires a license from Philips.

11. Data mus t be held for sufficient time to bridge the 300ns transition time of SCL.

scl

buf

hdst

low
high
sust

hdd
sud

r
f

susp

0 100 kHz

4.7 µs

4.0 µs

4.7 µs

4.0 µs

4.7 µs
0 µs

250 ns

1 µs

300 ns

4.7 µs

Repeated

Start

t

sust

t

hdst

Stop

t

f

t

r

t

susp

SDA

SCL

Stop Start

t

buf

t

hdst

t

low

t

hdd

t

high

t

sud

DS86PP8 7

CS4225

ABSOLUTE MAXIMUM RATINGS (AGND, DGND = 0V, all voltages with respect to 0V.)

Parameter Symbol Min Typ Max Units

Power Supplies: Digital VD -0.3 - 6.0 V

Analog VA -0.3 - 6.0 V
Input Current (Except Supply Pins) - - ±10.0 mA
Analog Input Voltage -0.3 - (VA+)+0.3 V
Digital Input Voltage -0.3 - (VD+)+0.3 V
Ambient Temperature (Power Applied) -55 - +125 °C
Storage Temperature -65 - +150 °C

Warning: Operation at or beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes.

RECOMMENDED OPERATING CONDITIONS (AGND, DGND = 0V, all voltages with

respect to 0V.)

Parameter Symbol Min Typ Max Units

Power Supplies: Digital VD 4.6 5.0 5.4 V

Analog VA 4.6 5.0 5.4 V
Operating Ambient Temperature CS4225-KL 0 25 70 °C

CS4225-BL T

CS4225-YU -40 25 +85 °C

DIGITAL CHARACTERISTICS (T

Parameter Symbol Min Typ Max Units

High-level Input Voltage V
Low-level Input Voltage V
High-level Output Voltage at I0 = -2.0 mA V
Low-level Output Voltage at I0 = 2.0 mA V
Input Leakage Current (Digital Inputs) - - 10 µA
Output Leakage Current (High-Z Digital Outputs) - - 10 µA

= 25°C; VA+, VD+ = 5V)

A

A

IH

IL
OH
OL

-40 25 +85 °C

(VD+)-1.0 - (VD+)+0.3 V

-0.3 - 1.0 V

(VD+)-0.3 - - V

--0.1V

8 DS86PP8

CS4225

+5V

Supply

To Optional
Inp u t Bu ffe rs

0.01 µF

NPO

0.47 µF

Fe rrite B e a d

150

0.01

µ

NPO

Digital

Audio

Source

Mode
Setting

and
Hardware

Controls

1 µF

+

0.47 µF

1.0 µF

1.0 µF

1.0 µF

1.0 µF

1.0 µF

1.0 µF

0.01 µF

NPO

F

38

33

39

37

13
12

2.0

0.1 µF

1 µF

+

3

23

CMOUT

19

AIN1L

18

AIN1R

16

AIN2L

17

AIN2R

15

AIN3L

CS4225

14

AIN3R

21

CR

22

20

4
5

6

CL

AINAUX

DATAUX
LRCKAUX

SCLKAU X

SCL/CCLK/IF0

SDA/CDOUT/CKF0

AD3/CS/IF1

AD2/CDIN/CKF1

DIF/HOLD

RST-PDN

H/S

DEM

IS0/ADO

IS1/AD1

AGND1,2

DGND

FILT

25 31 2 32 35 34

0.2 µF

F

0.1

µ

26

VAVD

AOUT1

AOUT2

AOUT3

AOUT4

VREF

SDIN1

SDIN2
SDOUT1
SDOUT2

LRCK

SCLK

CLKOUT

OVL

XTO XTI

C2C1

+5V Analog (optional)

If a separate +5V an alog supply
is available, attach here and
remove the 2.0 resistor

600

27

µ

0.0022

28

0.0022

29

0.0022

NPO

600

NPO

600

F

F

µ

F

µ

NPO
600

30

µ

0.0022

24

F

NPO

0.1 µF

7

9

10

8

43

42

1

44

41

40

36
11

External

Clock

Input

+

> 1.8 µF

>

+

> 1.8 µF>

+

>

> 1.8

+

> 1.8 µF

>

+

Micro­Controller

Audio

DSP

10

47 k

47k

47 k

F

µ

47 k

F

µ

All unused inputs

should be tied to 0V.
All NC pins should

b e left flo ating .

Figure 1 - Recommended Connection Diagram

DS86PP8 9