Cirrus Logic CS4218-KQ, CS4218-KL Datasheet
16-Bit Stereo Audio Codec
CS4218
Complete CMOS Stereo Audio Input
and Output System featuring:
Delta-Sigma A/D and D/A Converters using
•
64x Oversampling.
Input Anti-Aliasing and Output Smoothing
•
Filters.
Programmable Input Gain (0 dB to 22. 5 dB).
•
Programmable Output Attenuation (0 dB to
•
46.5 dB).
Sample frequencies from 4 kHz to 50 kHz.
•
Low Distortion, THD < 0.02% for DAC.
•
THD < 0.02% for ADC.
Low Power Dissipation: 80 mA typical.
•
Power-Down Mode : 1 mA typical.
•
Pin Compatible with CS4216 when used in
•
Serial Modes 3 and 4 (See Appendix A).
I2S(TM) Compatible Serial Mode (SM5).
•
Operates from 5V or 3.3V Digital Power
•
Supply. Requires 5V Analog Power Supply.
General Description
The CS4218 Stereo Audio Codec is a monolithic
CMOS device for computer multimedia, automotive,
and portable audio applications. It performs A/D and
D/A conversion, filtering, and level setting, creating 4
audio inputs and 2 audio outputs for a digital computer
system. The digital interfaces of left and right channels
are multiplexed into a single serial data bus with word
rates up to 50 kHz per channel.
ADCs and the DACs use delta-sigma modulation with
64X oversampling. The ADCs and DACs include digital decimation filters and output smoothing filters
on-chip which eliminate the need for external anti-aliasing filters.
The CS4218 is pin and function compatible with the
CS4216 when used in Serial modes 3 and 4. See the
Appendix A at the end of this data sheet for details.
2
I
S is a trademark of Ph ilips.
Ordering Information:
CS4218-KL 0
CS4218-KQ 0
° to 70°C 44-pin PLCC
° to 70°C 44-pin TQFP
RESET
PDN
SMODE3
SMODE2
SMODE1
SDIN
SDOUT
SCLK
SSYNC
MF7:SFS1/F2
MF8:SFS2/F3
FILT
CLKIN
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.crystal.com
D/A
POWER
CONTROL
SERIAL INTERFACE CONTROL
VD VA
DIGITAL
FILTERS
D/A
VOLTAGE REFERENCE
A/D
DIGITAL
FILTERS
A/D
DGND AGND
Copyright Crystal Semiconductor Corporation 1996
OUTPUT
MUTE
OUTPUT
ATTENUATION
INPUT
GAIN
INPUT
MUX
(All Rights Reserved)
LOUT
ROUT
DO1
MF5:DO2/INT
MF2:F2/CDIN
MF1:F1/CDOUT
DI1
MF6:DI2/F1
MF3:DI3/F3/CCLK
MF4:MA/CCS
REFGND
REFBYP
REFBUF
LIN1
LIN2
RIN1
RIN2
SEP ’96
DS135F1
1
Contents
Description
Cover . . . . . . . . . . . . . . . . . . . . 1
Contents . . . . . . . . . . . . . . . . . . . 2
Recommended Operating Conditions . . . . . . . . . . . . 3
Analog Input Characteristics . . . . . . . . . . . . . . 3
Analog Output Characteristics . . . . . . . . . . . . . 4
Switching Characteristics . . . . . . . . . . . . . . . 5
Digital Characteristics . . . . . . . . . . . . . . . . 7
A/D Decimation Filter Characteristics . . . . . . . . . . . . 8
D/A Interpolation Characteristics . . . . . . . . . . . . . 8
Absolute Maximum Ratings . . . . . . . . . . . . . . 8
Filter Response Plots . . . . . . . . . . . . . . . . 9
Typical Connection Diagram . . . . . . . . . . . . . . 11
Overview . . . . . . . . . . . . . . . . . . . 12
Functional Description . . . . . . . . . . . . . . . 12
Serial Interface Modes . . . . . . . . . . . . . . . 15
Power Supply and Grounding . . . . . . . . . . . . . . 26
Pin Diagrams and Descriptions . . . . . . . . . . . . . 29
Package Information . . . . . . . . . . . . . . . . 35
Parameter Definitions . . . . . . . . . . . . . . . . 36
Appendix A: CS4218 Compatibility with the CS4216 . . . . . . . . 38
Appendix B: Applications of Serial Mode 4 (SM4) . . . . . . . . 40
Appendix C: Setting CLKIN/SCLK Ratio for Desired Sample Rate . . . . 43
CS4218
- Analog Inputs and Outputs . . . . . . . . . . . . . 12
- Offset Calibration . . . . . . . . . . . . . . . 13
- Input Gain and Output Level Setting . . . . . . . . . . 13
- Muting and the ADC Valid Counter . . . . . . . . . . . 13
- Parallel Digital I/O Pins . . . . . . . . . . . . . . 13
- Reset and Power Down Modes . . . . . . . . . . . . 13
- Audio Serial Interface . . . . . . . . . . . . . . 14
- Serial Mode 3 . . . . . . . . . . . . . . . . 15
- Serial Mode 4 . . . . . . . . . . . . . . . . 22
- Serial Mode 5 . . . . . . . . . . . . . . . . 25
2 DS135F1
CS4218
RECOMMENDED OPERATING CONDITIONS (AGND, DGND = 0V, all voltages with respect
to 0V.)
Parameter Symbol Min Typ Max Units
Power Supplies: Digital VD 4.75 5.0 5.25 V
Digital (Low Voltage) VD 3.0 3.3 3.6 V
Analog VA 4.75 5.0 5.25 V
Operating Ambient Temperature T
ANALOG CHARACTERISTICS( T
Logic 1 = VD; 1kHz Input Sine Wave; CLKIN = 12.288 MHz; SM3 Slave sub-mode, 256 BPF; 0dB gain/attenuation;Conversion Rate = 48 kHz; SCLK = 12.288 MHz; Measurement Bandwidth is 10 Hz to 20 kHz ; Unless otherwise specified.)
Parameter * Symbol Min Typ Max Units
Analog Input Characteristics - Minimum gain s etting (0 dB); unless otherwise specified.
ADC Resolution 16 - - Bits
ADC Differential Nonlinearity (Note 1) - - ±0.9 LSB
Instantaneous Dynamic Range (Note 3) IDR 80 84 - dB
Total Harmonic Distortion THD - - 0.02 %
Interchannel Isolation - 80 - dB
Interchannel Gain Mismatch - - ±0.5 dB
Frequency Response (Note 1) -0.5 - +0.2 dB
= 25°C; VA, VD = +5V; Input Levels: Logic 0 = 0V,
A
A
02570°C
Programmable Input Gain - 22.5 - dB
Gain Step Size - 1.5 - dB
Absolute Gain Step Error - - 0.75 dB
Gain Drift (Note 1) - 100 - ppm/°C
Offset Error 0dB Gain - - ±50 LSB
22.5dB Gain Full Scale Input Voltage 2.5 2.8 3.1 V
Input Resistance (Notes 1,2) 20 - - kΩ
Input Capacitance (Note 1) - - 15 pF
Notes: 1. This specification is guar anteed by characterization, not production testing.
2. Input resistance is for the input selec ted. Non-selected inputs have a very high (>1M
3. Operation in Slave sub-modes may yield results lower than the 80 dB minimum.
* Parameter definitions are given at the end of this data sheet.
Specifications are subject to change without notice.
DS135F1 3
−±500 LSB
pp
Ω) input resistance.
CS4218
ANALOG CHARACTERISTICS (Continued)
Parameter * Symbol Min Typ Max Units
Analog Output Characteristics - Minimum A ttenuation; Unless Otherwise Spec ified.
DAC Resolution 16 - - Bits
DAC Differential Nonlinearity (Note 1) - - ±0.9 LSB
Total Dynamic Range TDR - 93 - dB
Instantaneous Dynamic Range IDR 80 83 - dB
Total Harmonic Distortion (Note 4) THD - - 0.02 %
Interchannel Isolation (Note 4) - 80 - dB
Interchannel Gain Mismatch - - ±0.5 dB
Frequency Response (Note 1) -0.5 - +0.2 dB
Programmable Attenuation (Note 5) - -46.5 - dB
Attenuation Step Size (Note 5) - 1.5 - dB
Absolute Attenuation Step Error (Note 5) - - 0.75 dB
Gain Drift (Note 1) - 100 - ppm/°C
REFBUF Output Voltage (Note 6) 1.9 2.1 2.3 V
Maximum output current= 400
Offset Voltage (Note 7) - 10 - mV
Full Scale Output Voltage (Note 4) 2.4 2.7 3.1 V
External Load Impedance 10k - - Ω
Internal Resistor Value for LOUT and ROUT 400 600 800 Ω
Deviation from Linear Phase (Note 1) - - 1 Degree
Out of Band Energy (22 kHz to 100 kHz) - -60 - dB
Power Supply
Power Supply Current (Note 8) Operating (VD = 5.0V) - 80 100 mA
Operating (VD = 3.3V) - 65 85 mA
Power Down - - 1 mA
Power Supply Rejection (1 kHz) - 40 - dB
Notes: 4. 10 k
5. Tested in SM3, Slave sub-mode, 256 BPF.
6. REFBUF load current must be DC. To drive dynamic loads, REFBUF must be buffered.
7. No DC load.
8. Typical current: VA = 30mA, VD = 50mA with VD = 5.0V. VA = 30mA, V D = 35mA with VD = 3.3V.
Ω, 100 pF load.
AC variations in REFBUF current may degrade ADC and DAC performance.
Power supply current does not include output loading.
µA
pp
* Parameter definitions are given at the end of this data sheet.
4 DS135F1
CS4218
SWITCHING CHARACTERISTICS (T
Levels: Logic 0 = 0V, Logic 1 = VD)
Parameter Symbol Min Typ Max Units
Input clock (CLKIN) frequency SM3 Multiplier Mode CLKIN 64 768 800 KHz
SM3 Master and Slave Modes, SM4, SM5 CLKIN 1.024 12.288 12.8 MHz
CLKIN low time t
CLKIN high time t
Sample Rate (Note 1) Fs 4 - 50 kHz
DI pins setup time to SCLK edge (Note 1) t
DI pins hold time from SCLK edge (Note 1) t
DO pins delay from SCLK edge t
SCLK and SSYNC output
delay from CLKIN rising
SCLK period All master Modes (Notes 1,7) t
SCLK high time Slave Mode t
SCLK low time Slave Mode t
SDIN, SSYNC setup time to SCLK edge Slave Mode t
SDIN, SSYNC hold time from SCLK edge Slave Mode t
SDOUT delay from SCLK edge t
Output to Hi-Z state bit 64 (Note 1) t
Output to non-Hi-Z bit 1 (Note 1) t
RESET pulse width low 500 - - ns
All master Modes (Note 1) t
= 25°C; VA, VD = +5V, outputs loaded with 30 pF; Input
A
ckl
ckh
s2
h2
pd2
pd3
sckw - 1/(Fs*bpf) - s
Slave Mode
sckh
sckl
s1
h1
pd1
hz
nz
15 - - ns
15 - - ns
10 - - ns
8--ns
- - 30 ns
- - 50 ns
75 - - ns
30 - - ns
30 - - ns
15 - - ns
10 - - ns
- - 28 ns
- - 12 ns
15 - - ns
CCS low to CCLK rising SM4 (Note 1) t
CDIN setup to CCLK falling SM4 (Note 1) t
CCLK low to CDIN invalid (hold time) SM4 (Note 1) t
CCLK high time SM4 (Note 1) t
CCLK low time SM4 (Note 1) t
CCLK Period SM4 (Note 1) t
CCLK rising to CDOUT data valid SM4 (Note 1) t
CCLK rising to CDOUT Hi-Z SM4 (Note 1) t
CCLK falling to CCS high SM4 (Note 1) t
RESET low time prior to PDN rising trph 100 - - ns
RESET low hold time after PDN rising trhold 50 - - ms
Notes: 7. When the CS4218 is in master modes (SSYNC and SCLK outputs), the SCLK duty cycle is 50%.
The equation is based on the selected sample frequency (Fs) and the number of bits per frame (bpf).
DS135F1 5
cslcc
discc
ccdih
cclhh
cclhl
cclkw
ccdov
ccdot
cccsh
25 - - ns
15 - - ns
10 - - ns
25 - - ns
25 - - ns
75 - - ns
- - 30 ns
- - 30 ns
0--ns
SCLK
[SM3,SM4\
SSYNC
[SM3,SM4\
SDIN
SDOUT
t
sckhtsckl
t
s1
[SM3]
(SM4)
[SM3]
(SM4)
t
sckw
CS4218
t
h1
t
t
h1
s1
Bit 1 Bit 2
t
pd1
Bit 1
t
nz
Bit 32
(Bit 32)
t
pd1
Bit 2
Bit 32
(Bit 32)
Serial Audio Port Timing
Bit 33
(Bit 1)
Bit 33
(Bit 1)
Bit 63
(Bit 31)
Bit 63
(Bit 31)
Bit 64
(Bit 32)
Bit 64
(Bit 32)
t
hz
MF4:CCS
MF1:CDOUT
MF3:CCLK
MF2:CDIN
MF4:CCS
MF1:CDOUT
MF3:CCLK
MF2:CDIN
t
discc
ADV
t
cslcc
t
ccdih
0MSK
t
cclkh
DO1
LAtt4
t
cclkl
t
cclkw
LAtt3
LAtt2
LAtt1
LAtt0
RAtt4
t
RAtt3
123 5 89467 10
0
DI1
ADV
0
t
ccdot
0000
0
RGain2
RGain1
0
RGain0
1
Err1
Err0
LCL RCL
0
24 28 29 3231302726252322
Serial Mode 4. Control Data Serial Port Timing
ccdov
RAtt2
t
cccsh
LCL
11
0
6 DS135F1
SCLK
CS4218
t
t
s2
h2
t
ckl
t
ckh
DIx
DOx
PDN
RESET
DI/DO Timing
CLKIN
t
pd2
SCLK
SSYNC
(Master Mode)
Power Down Mode Timing
t
pd3
SCLK & SSYNC Output Timing
(Master Mode)
t
rhold
t
rph
DIGITAL CHARACTERISTICS (T
= 25°C; VA = 5V, VD = 5V or 3.3V)
A
Parameter Symbol Min Typ Max Units
High-level Input Voltage V
Low-level Input Voltage V
High-level Output Voltage at I0 = -2.0 mA V
Low-level Output Voltage at I0 = +2.0 mA V
IH
IL
OH
OL
2.0 - VD+0 .3 V
-0.3 - 0.8 V
VD-0.3 - - V
--0.2V
Input Leakage Current (Digital Inputs) - - 10 µA
Output Leakage Current (High-Z Digital Outputs) - - 10 µA
Output Capacitance (Note 1) C
Input Capacitance (Note 1) C
OUT
IN
- - 15 pF
- - 15 pF
DS135F1 7
CS4218
A/D Decimation Filter Characteristics
Parameter Symbol Min Typ Max Units
Passband 0 - 0.40Fs Hz
Frequency Response -0.5 - +0.2 dB
Passband Ripple (0-0.4Fs) - - ±0.1 dB
Transition Band 0.40Fs - 0.60Fs Hz
Stop Band 0.60Fs - - Hz
Stop Band Rejection 74 - - dB
Group Delay - 8/Fs s
Group Delay Variation vs. Frequency - 0.0 µs
D/A Interpolation Filter Characteristics
Parameter Symbol Min Typ Max Units
Passband 0 - 0.40Fs Hz
Frequency Response -0.5 - +0.2 dB
Passband Ripple (0-0.4Fs) - - ±0.1 dB
Transition Band 0.40Fs - 0.60Fs Hz
Stop Band 0.60Fs - - Hz
Stop Band Rejection 74 - - dB
Group Delay - - 8/Fs s
Group Delay Variation vs. Frequency - - 0.1/Fs µs
ABSOLUTE MAXIMUM RATINGS (AGND, DGND = 0V, all voltages with respect to 0V.)
Parameter Symbol Min Typ Max Units
Power Supplies: Digital VD -0.3 - 6.0 V
Analog VA -0.3 - 6.0 V
Input Current (Except Supply Pins) - - ±10.0 mA
Analog Input Voltage -0.3 - VA+0.3 V
Digital Input Voltage -0.3 - VD+0.3 V
Ambient Temperature (Power Applied) -55 - +125 °C
Storage Temperature -65 - +150 °C
Warning: Operation beyond thes e limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
8 DS135F1
CS4218
10
0
-10
-20
-30
-40
-50
Magnitude (dB)
-60
-70
-80
-90
-100
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Input Frequency (×Fs)
Figure 1. CS4218 ADC Frequency Response
0
-10
-20
-30
-40
-50
-60
Magnitude (dB)
-70
-80
-90
-100
0.40 0.43 0.46 0.49 0.52 0.55 0.58 0.61 0.64 0.67 0.70
Input Frequency (×Fs)
0.2
0.1
-0.0
-0.1
-0.2
-0.3
-0.4
Magnitude (dB)
-0.5
-0.6
-0.7
-0.8
0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
Input Frequency (
Fs)
×
Figure 2. CS4218 ADC Passband Ripple
10
0
-10
-20
-30
-40
-50
-60
Magnitude (dB)
-70
-80
-90
-100
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
Input Frequency (
×
0.8
Fs)
0.9 1.0
Figure 3. CS4218 ADC Transition Band
0.2
0.1
-0.0
-0.1
-0.2
-0.3
-0.4
Magnitude (dB)
-0.5
-0.6
-0.7
-0.8
0.00 0.05 0.10 0.15 0.20 0.2 5 0.30 0.35 0.40 0.45 0.50
Input Frequency (×Fs)
Figure 5. CS4218 DAC Passband Ripple
Figure 4. CS4218 DAC Frequency Response
0
-10
-20
-30
-40
-50
-60
Magnitude (dB)
-70
-80
-90
-100
0.40
0.43
0.46
0.49 0.52
0.55 0.58 0.61
Input Frequency (×Fs)
Figure 6. CS4218 DAC Transition Band
0.64
0.67 0.70
DS135F1 9
2.5
2.0
1.5
1.0
0.5
0.0
-0.5
Phase (degrees)
-1.0
-1.5
-2.0
-2.5
0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
Input Frequency (
Fs)
×
Figure 7. CS4218 DAC Deviation from Linear Phase
CS4218
10 DS135F1
CS4218
+5V
Supply
Line In 2
Right
See
for suggested input ciruits.
Line In 2
Left
Line In 1
Right
To Optional
Input Buffers
Line In 1
Left
Analog Inputs
Ferrit e Bead
1 µF
+
section
0.47µF
Parallel Bits
or
Sub-Mode
Settings
or
Control Port
Note: AGND and DGND pins MUST be on the same ground plane
0.1 µF
26
RIN2
28
LIN2
25
RIN1
20
REFBUF
27
LIN1
40
MF1:F1/CDOUT
39
MF2:F2/CDIN
35
MF3:DI3/F3/CCLK
36
MF4:MA/CCS
38
MF5:DO2/INT
34
MF6:DI2/F1
2.0
1 µF
+
4
CS4218
AGND DGND
23 5
0.1 µF
24
VAVD
ROUT
LOUT
REFBYP
REFGND
CLKIN
RESET
PDN
SDOUT
SDIN
SCLK
SSYNC
SMODE3
SMODE2
SMODE1
MF7:SFS1
MF8:SFS2
FILT
Figure 8. Typical Connection Diagram
+5V
Analog
If a separate +5V
Analog supply is used, remove
the 2.0 ohm resistor
15
16
21
22
3
2
13
43
42
44
1
33
37
41
32
29
31
30
6
0.1 µF
Controller
DI1
DO1
Mode
Setting
C
FILT
0.47µF
Refer to the
section for terminating
All other unused inputs
should be tied to GND. All NC
pins should be left floating.
> 1.0 µF
+
40 k
0.0022µF
NPO
> 1.0 µF
+
40 k
0.0022µF
NPO
+
µ
F
10
Required only for SM3
Multiplier Sub-Mode
Analog Inputs
unused line inputs.
Right
Audio
Output
Left
Audio
Output
DS135F1 11
OVERVIEW
CS4218
The CS4218 contains two analog-to-digital converters, two digital-to-analog converters,
adjustable input gain, and adjustable output level
control. Since the converters contain all the required filters in digital or sampled analog form,
the filters’ frequency responses track the sample
rate of the CS4218. Only a single-pole RC filter
is required for the analog inputs and outputs.
Communication with the CS4218 is via a serial
port, with separate pins for data input and output. The filters and converters operate over a
sample rate range of 4 kHz to 50 kHz.
FUNCTIONAL DESCRIPTION
Analog Inputs and Outputs
Figure 8 illustrates the suggested connection diagram for the CS4218. The line level inputs,
LIN1 or LIN2 and RIN1 or RIN2, are selected
by an internal input multiplexer. This multiplexer
is a source selector and is not designed for realtime switching between inputs at the sample rate.
When using the CS4218 as a drop-in replacement for the CS4216, existing recommended
circuits (shown in the CS4216 data sheet) may
be used as is without any noticeable degradation
in performance. Performance may vary with
user-specific input circuits and should be
checked when contemplating the use of CS4218
in existing CS4216 designs.
Unused analog inputs that are not selected have
a very high input impedance, so they may be
tied to AGND directly. Unused analog inputs
that are selected should be tied to AGND
through a 0.1 µF capacitor. This prevents any
DC current flow.
The analog inputs are single-ended and internally biased to the REFBUF voltage (nominally
0.33 uF
300 pF
NPO
NPO
300 pF
0.33 uF
RIN1
or
RIN2
LIN1
or
LIN2
Line In
Right
Line In
Left
5.6K
5.6K
5.6K
5.6K
Figure 9. Line Inputs.
2.1 V). The REFBUF output should be buffered
if it is to be used for microphone phantom
power.
The use of a single-pole RC filter is recommended for use as an external anti-alias filter for
the CS4218. The maximum cutoff frequency
(lowpass) should not exceed 200 kHz. A lower
value for cuttoff frequency may be used, and is
dependent upon the application’s input bandwidth.
The CS4218 inputs will accept a 1Vrms signal,
so a divide by two resistor network will serve as
a front-end interface to 2 Vrms line level systems. Figure 9 shows a simple input circuit that
includes a gain of 0.5 and the required RC filter.
The gain of 0.5 yields a full scale input sensitivity of 2 V
with the CS4218 programmable
rms
gain set to 0.
The analog outputs are also single-ended and
centered around the REFBUF voltage. AC cou-
pling capacitors of >1 µF are recommended.
Refer to Figure 8 for the recommended analog
output circuit.
12 DS135F1
CS4218
When using the CS4218 as a drop-in replacement for the CS4216, the external 600 ohm
series resistors on LOUT and ROUT are not required, since they are part of the CS4218
internal circuitry.
In applications where both CS4218 and CS4216
are to be used, a board stuff option should be
included in the bill of materials which will allow
either a 600-ohm or a 0-ohm resistor to be used
externally on both LOUT and ROUT.
Offset Calibration
Both input and output offset voltages are minimized by internal calibration. Offset calibration
occurs after exiting a reset or power down condition. During calibration, which takes 194 frames,
output data from the ADCs will be all zeros, and
will be flagged as invalid. Also, the DAC outputs will be muted. After power down mode or
power up, RESET should be held low for a
minimum of 50 ms to allow the voltage reference to settle. Changing sample rates in master
and slave modes automaticall y initiates a calibration.
Input Gain and Output Level Settin g
Input gain is adjustable from 0 dB to +22.5 dB
in 1.5 dB steps. Output level attenuation is adjustable from 0 dB to -46.5 dB in 1.5 dB steps.
Both input and output gain adjustments are internally made on zero-crossings of the analog
signal, to minimize "zipper" noise. The gain
change automatically takes effect if a zero crossing does not occur within 512 frames.
Muting and the ADC Valid Counter
The mute function allows the the user to tu rn off
the output channels ( LOUT and ROUT ). Prior
to muting, the attenuation should be gradually
ramped to maximum ( 46.5 dB ), taking 1.5dB
steps. This significantly reduces any audible artifacts that may be heard once muting is enabled.
It is the users responsibility to program the serial
host to perform the ramping.
The serial data stream contains a "Valid Data"
indicator, the ADV bit, for the A/D converters
which is low until enough clocks have passed
since reset, or low-power (power down mode)
operation to have valid A/D data from the filters
(i.e., until calibration time plus the full latency
of the digital filters has passed.)
Parallel Dig ital Input/ Output Pin s
Parallel digital inputs are general purpose pins
whose values are reflected in the serial dat a output stream to the processor. Parallel digital
outputs provide a way to control external devices
using bits in the serial data input stream. All parallel digital pins, with the exception of DI1 and
DO1, are multifunction and are defined by the
serial mode selected. In Serial Mode 3 master
modes and Serial Mode 5, two digital inputs and
two digital outputs are available. In Serial Mode
3 slave modes, three digital inputs and two digital outputs are available. In Serial Mode 4 only
one digital input and digital output exists. Figure 10 shows when the DI pins are latched, and
when the DO pins are updated.
Reset and Power Down Modes
SSYNC
Reset places the CS4218 into a known state and
SCLK
(SM3)
Start of
Frame
Figure 10. Digital Input/Output Timing
DS135F1 13
DO pins
update
DI pins
latched
must be held low for at least 50 ms after powerup or a hard power down. In reset, the digital
outputs are driven low. Reset sets all control data
register bits to zero. Changing sample rates in
CS4218
master and slave modes automatically initiates a
calibration.
An RC filter with a time constant greater than
50 ms may be used on the RESET pin. The
CS4218 RESET pin has hysterisis to ensure
proper resets when using an RC filter.
Hard power down mode may be initiated by
bringing the PDN pin low. All analog outputs
will be driven to the REFBUF voltage which
will then decay to zero. All digital outputs will
be driven low and then will go to a high impedance state. Minimum power consumption will
occur if CLKIN is held low. After leaving the
power down state, RESET should be held low
for 50 ms to allow the analog voltage reference
to settle before calibration is started.
Alternatively, soft power down may be initiated
in slave modes by reducing the SCLK frequency
below the minimum values shown in Table 1. In
soft power down the analog outputs are muted
and the serial data from the codec will indicate
invalid data and the appropriate error code. The
parallel bit I/O is still functional in soft power
down mode. This is, in effect, a low power mode
with only the parallel bit I/O unit functioning.
Audio Serial Interface
In Serial Mode 3 (SM3), the audio serial port
uses 4 pins: SDOUT, SDIN, SCLK and SSYNC.
SDIN carries the D/A converters’ input data and
control bits. Input data is ignored for frames not
allocated to the selected CS4218. SDOUT carries the A/D converters’ output data and status
bits. SDOUT goes to a high-impedance state
during frames not allocated to the selected
CS4218. SCLK clocks data in to and out of the
CS4218. SSYNC indicates the start of a frame
and/or sub-frame. SCLK and SSYNC must be
synchronous to the master clock.
Serial Mode 4 (SM4 ) is similar to SM3 with the
exception of the control information. In Serial
Mode 4, the control information is entered
through a separate asynchronous control port.
Therefore, the audio serial port only contains
audio data, which reduces the number of bits on
the audio port from 64 to 32 per codec. This is
useful for lower bit rate serial hosts.
Serial Mode 5 (SM5) is compatible with the
I2STM serial data protocol. SM5 is a Master
mode only. As in SM3, 4 pins are used:
SDOUT, SDIN, SCLK, and SSYNC.
The serial port protocol is based on frames consisting of 1, 2, or 4 sub-frames. The frame rate is
the system sample rate. Each sub-frame is used
Bits Per Frame Minimum SCLK
Frequency
For All Modes Except SM3 Multiplier Sub Mode
32 CLKIN / 96
64 CLKIN / 48
128 CLKIN / 24
256 CLKIN / 12
SM3 Multiplier Sub Mode
64 (16 * CLKIN) / 48
128 (16 * CLKIN) / 24
256 (16 * CLKIN) / 12
by one CS4218 device. Up to 4 CS4218s may be
attached to the same serial control lines. SFS1
and SFS2 are tied low or high t o indicate to each
CS4218 which sub-frame is allocated for it to
use.
Serial Data Format
In SM3 and SM5, a sub-frame is 64 bits in
length and consists of two 16-bit audio values
and two 16-bit control fields. In SM4 a sub-
Table 1. Soft Power Down Conditions
(Slave Modes only)
frame is 32 bits in length and only contains the
two 16-bit audio fields; the control data is loaded
through a separate port. The audio data is MSB
14 DS135F1
Loading...