Cirrus Logic CS4215-KQ, CS4215-KL, CS4215 Datasheet
Semiconductor Corporation
16-Bit Multimedia Audio Codec
CS4215
Features
•
Sample Frequencies from 4 kHz to 50 kHz
•
16-bit Linear, 8-bi t Linear, µ-Law, or A-Law
Audio Data Coding
•
Programmable Gain for A nalog Inputs
•
Programmable Attenu ation for Analog
Outputs
•
On-chip Oscillators
•
+5V Power Supply
•
Microphone and Line Level Analog Inputs
•
Headphone, Sp eaker, and Line Outputs
•
On-chip Anti-Aliasing/Smoothing Filters
•
Serial Digital Interface
General Description
The CS4215 is an Mwave
audio codec.
The CS4215 is a single-chip, stereo, CMOS multimedia codec that supports CD-quality music,
FM radio-quality music, telephone-quality speech, and
modems. The analog-to-digital and digital-to-analog
converters are 64×oversampled delta-sigma converters
with on-chip filters which adapt to the sample frequency selected.
The +5V only power requirement makes the CS4215
ideal for use in workstations and personal computers.
Integration of microphone and line level inputs, input
and output gain setting, along with headphone and
monitor speaker driver, results in a v ery small footprint.
Ordering Information:
CS4215-KL 0°C to 70°C 44-pin PLCC
CS4215-KQ 0°C to 70°C 100-pin TQFP
CDB4215 Evaluation Board
TM
CMOUT
LINL
LINR
MINL
MINR
SDIN
CLKIN
CLKOUT
XTL1IN
XTL1OUT
XTL2IN
XTL2OUT
PIO0
PIO1
D/C
RESET
PDN
8
unsigned
decode
A/D
A/D
-law
µ
A-law
Serial Input/Output
Monitor
Attenuator
+
+
M
Gain
U
X
Clock
Generator
Control
Interface and
Registers
VA1 VA2 VD1 VD2 AGND1 AGND2 DGND1 DGND2
unsigned
-law
µ
A-law
encode
Voltage
Reference
D/A
D/A
Output
Attenuator
Mute
SDOUT
SCLK
FSYNC
TSIN
TSOUT
VREF
MOUT1
MOUT2
LOUTR
LOUTL
HEADC
HEADR
HEADL
This data sheet was written for Revision E CS4215 codecs and later. For differences between Revision E and
previous versions, see
Appendix A
.
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445-7222 FAX: (512) 445-7581
Copyright Crystal Semiconductor Corporation 1993
(All Rights Reserved)
SEPT ’93
DS76F2
1
CS4215
ANALOG CHARACTERISTICS( T
Input Levels: Logic 0 = 0V, Logic 1 = VD1, VD2; Full Scale Input Sine wave, No Gain, No Attenuation 1 kHz;
Conversion Rate = 48 kHz; No Gain, No Attenuation, SCLK = 3.072 MHz; Measurement Bandwidth is 10 Hz to
20 kHz; Slave mode; Unless otherwise specified.)
Parameter * Symbol Min Typ Max Units
Analog Input Characteristics
ADC Resolution 16 - - Bits
ADC Differential Nonlinearity - - ±0.9 LSB
Instantaneous Dynamic Range Line Inputs IDR 80 84 - dB
Total Harmonic Distortion Line Inputs THD - - 0.012 %
Interchannel Isolation Line to Line Inputs - 80 - dB
Interchannel Gain Mismatch Line Inputs - - 0.5 dB
Frequency Response (Note 1) (0 to 0.45 Fs) -0.5 - +0.2 dB
Programmable Input Gain Line Inputs -0.2 - 23.5 dB
- Minimum gain setting (0 dB); unless other wise specified.
= 25°C; VA1, VA2, VD1, VD2 = +5V;
A
Mic Inputs 72 78 - dB
Mic Inputs - - 0.032 %
Line to Mic Inputs - 60 - dB
Mic Inputs - - 0.5 dB
Mic Inputs 19.8 - 44 dB
Gain Step Size - 1.5 - dB
Absolute Gain Step Error - - 0.75 dB
Offset Error Line Inputs (AC Coupled) - ±150 ±400
with HPF = 0 Line Inputs (DC Coupled) - ±10 ±150 LSB
(No Gain) Mic Inputs - ±400 -
Offset Error Line Inputs (AC Coupled) - 0 ±5
with HPF = 1 (Notes 1,2) Line Inputs (DC Coupled) - 0 ±5LSB
(No Gain) Mic Inputs - 0 ±5
Full Scale Input Voltage: (MLB=0) Mic Inputs 0.250 0.28 0.310 Vpp
(MLB=1) Mic Inputs 2.50 2.8 3.10 V
Line Inputs 2.50 2.8 3.10 V
Gain Drift - 100 - ppm/°C
Input Resistance (Note 3) 20 - - kΩ
Input Capacitance - - 15 pF
CMOUT Output Voltage (Note 4) 1.9 2.1 2.3 V
(Maximum output current = 400 µA)
Notes: 1. This specification is guaranteed by characterization, not production tes ting.
2. Very low frequency signals will be slightly distorted when using the HPF.
3. Input resistance is for the input selec ted. Non-selected inputs have a very high (>1M Ω) input
resistance.
4. DC current only. If dynamic loading exists, then CMOUT must be buffered or the performance of
ADC’s and DAC’s may be degraded.
Parameter definitions are given at the end of this data sheet.
*
Mwave is a trademark of the IBM Corporation.
pp
pp
2 DS76F2
Specifications are subject to change without notice.
ANALOG CHARACTERISTICS (Continued)
Parameter * Symbol Min Typ Max Units
CS4215
Analog Output Characteristics
- Minimum Attenuation; Unless Otherwise Specified.
DAC Resolution 16 - - Bits
DAC Differential Nonlinearity - - ±0.9 LSB
Total Dynamic Range TDR - 95 - dB
Instantaneous Dynamic Range (OLB = 1) (All Outputs) IDR 80 85 - dB
Total Harmonic Distortion Line Out (Note 5) - - 0.025 %
(OLB = 1) Headphone Out (Note 6) THD - - 0.2 %
Speaker Out (Note 6) - - 0.32 %
Interchannel Isolation Line Out (Note 5) - 80 - dB
Headphone Out (Note 6) - 40 - dB
Interchannel Gain Mismatch Line Out - - 0.5 dB
Headphone - - 0.5 dB
Frequency Response (Note 1) (0 to 0.45 Fs) -0.5 - +0.2 dB
Programmable Attenuation (All Outputs) 0.2 - -94.7 dB
Attenuation Step Size - 1.5 - dB
Absolute Attenuation Step Error - - 0.75 dB
Offset Voltage Line Out - 10 - mV
Full Scale Output Voltage Line Output (Note 5) 2.55 2.8 3.08 V
with OLB = 0 Headphone Output (Note 6) 3.6 4.0 4.4 V
Speaker Output-Differential (Note 6) 7.3 8.0 8.8 V
Full Scale Output Voltage Line Output (Note 5) 1.8 2.0 2.2 V
with OLB = 1 Headphone Output (Note 6) 1.8 2.0 2.2 V
Speaker Output-Differential (Note 6) 3.6 4.0 4.4 V
pp
pp
pp
pp
pp
pp
Gain Drift - 100 - ppm/°C
Deviation from Linear Phase - - 1 Degree
Out of Band Energy (22 kHz to 100 kHz) Line Out - -60 - dB
Power Supply
Power Supply Current (Note 7) Operating - 110 140 mA
Power Down - 0.5 2 mA
Power Supply Rejection (1 kHz) - 40 - dB
Notes: 5. 10 kΩ, 100 pF load. Headphone and Speaker outputs disabled.
6. 48 Ω, 100 pF load. For the headphone outputs, THD with 10kΩ, 100pF load is 0.02%.
7. Typically, 50% of the power supply current is supplied to the analog power pins (VA1, VA2)
and 50% is supplied to the digital power pins (VD1, VD2). Values given are for unloaded outputs.
DS76F2 3
CS4215
A/D Decimation Filter Characteristics
Parameter Symbol Min Typ Max Units
Passband (Fs is conversion freq.) 0 - 0.45Fs Hz
Frequency Response -0.5 - +0.2 dB
Passband Ripple - - ±0.1 dB
Transition Band 0.45Fs - 0.55Fs Hz
Stop Band ≥ 0.55Fs - - Hz
Stop Band Rejection 74 - - dB
Group Delay - 16/Fs - s
Group Delay Variation vs. Frequency - - 0.0 µs
D/A Interpolation Filter Characteristics
Parameter Symbol Min Typ Max Units
Passband (Fs is conversion freq.) 0 - 0.45Fs Hz
Frequency Response -0.5 - +0.2 dB
Passband Ripple - - ±0.1 dB
Transition Band 0.45Fs - 0.55Fs Hz
Stop Band ≥ 0.55Fs - - Hz
Stop Band Rejection 74 - - dB
Group Delay - 16/Fs - s
Group Delay Variation vs. Frequency - - 0.1/Fs s
DIGITAL CHARACTERISTICS (T
Parameter Symbol Min Max Units
High-level Input Voltage V
Low-level Input Voltage V
High-level Output Voltage at I0 = -2.0 mA V
Low-level Output Voltage at I0 = 2.0 mA V
Input Leakage Current (Digital Inputs) - 10 µA
= 25°C; VA1, VA2, VD1, VD2 = 5V)
A
(VD1,VD2)-1.0 (VD1,VD2)+0.3 V
IH
IL
OH
OL
-0.3 1.0 V
(VD1,VD2)-0.2 - V
-0.1V
Output Leakage Current (High-Z Digital Outputs) - 10 µA
4 DS76F2
CS4215
SWITCHING CHARACTERISTICS
(TA = 25°C; VA1, VA2, VD1, VD2 = +5V,
outputs loaded with 30 pF; Input Levels: Logic 0 = 0V, Logic 1 = VD1, VD2)
Parameter Symbol Min Typ Max Units
SCLK period Master Mode, XCLK = 1 (Note 8) t
sckw
-1/(Fs
bpf) - s
*
Slave Mode (XCLK = 0) tsckw 80 - - ns
SCLK high time Slave Mode, XCLK = 0 (Note 9) tsckh 25 - - ns
SCLK low time Slave Mode, XCLK = 0 (Note 9) tsckl 25 - - ns
Input Setup Time t
Input Hold Time t
s1
h1
15 - - ns
10 - - ns
Input Transition Time 10% to 90% points - - 10 ns
Output delay tpd1 - - 28 ns
SCLK to TSOUT tpd2 - - 30 ns
Output to Hi-Z state Timeslot 8, bit 0 t
Output to non-Hi-Z Timeslot 1, bit 7 t
hz
nz
- - 12 ns
15 - - ns
Input Clock Frequency Crystals - - 27 MHz
CLKIN (Note 10) 1.024 - 13.5 MHz
Input Clock (CLKIN) low time 30 - - ns
Input Clock (CLKIN) high time 30 - - ns
Sample rate Fs 4 - 50 kHz
RESET low time (Note 11) 500 - - ns
Notes: 8. In Master mode with BSEL1,0 set to 64 or 128 bits per frame (bpf), the SCLK duty cycle is 50%.
When BSEL1,0 is set to 256 bpf, SCLK will have the same duty cycle as CLKOUT.
See Internal Clock Generation section.
9. In Slave mode, FSYNC and SCLK must be derived fr om the master clock running the codec
(CLKIN, XTAL1, XTAL2).
10. Sample rate specifications must not be exceeded.
11. After powering up the CS 4215, RESET should be held low for 50 ms to allow the v oltage
reference to settle.
FSYNC
TSIN
TSOUT
FSYNC
SCLK
SDIN
SDOUT
t
in
out
s1
t
t
t
pd1
sckh
h1
t
s1
t
sckw
t
t
h1
t
nz
pd1
t
pd1
t
sckl
t
s1
t
h1
TS 1, Bit 7
TS 1, Bit 7 TS 1, Bit 6
t pd1
t
pd2
TS 8, Bit 0TS 1, Bit 6
TS 8, Bit 0
t
t
pd2
hz
DS76F2 5
CS4215
ABSOLUTE MAXIMUM RATINGS (AGND, DGND = 0V, all voltages with respect to 0V.)
Parameter Symbol Min Max Units
Power Supplies: Digital VD1,VD2 -0.3 6.0 V
Analog VA1,VA2 -0.3 6.0 V
Input Current (Except Supply Pins) - ±10.0 mA
Analog Input Voltage -0.3 (VA1, VA 2)+0.3 V
Digital Input Voltage -0.3 (VD1, VD2)+0.3 V
Ambient Temperature (Power Applied) -55 +125 °C
Storage Temperature -65 +150 °C
Warning: Operation bey ond these limits may result in per manent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS (AGND, DGND = 0V, all voltages with re-
spect to 0V.)
Parameter Symbol Min Typ Max Units
Power Supplies: Digital (Note 8) VD1,VD2 4.75 5.0 5.25 V
Analog (Note 8) VA1,VA2 4.75 5.0 5.25 V
Operating Ambient Temperature T
Note: 8. VD - VA must be less than 0.5 V olts (one diode drop).
A
02570°C
6 DS76F2
+5V Digital
Supply
Ferrite Bead
1 uF
CS4215
+5V Analog
+
0.1 uF
0.1 uF
+
1 uF
Supply
Microphone
Input Right
Microphone
Input Left
To O ptio nal
Input Buffers
0.47 uF
See Line Level
Inp uts S e ction
Refer to the
section for terminating
unused line and mic inputs.
All other unused inputs
should be tied to GND. All NC
pins should be left floating.
Analog Inputs
0.47 uF
0.01 uF
0.47 uF
0.01 uF
VD1
47k
150
NPO
150
NPO
15
17
19
16
18
36
37
MINR
MINL
CMOUT
LINR
LINL
PIO0
PIO1
38
CS4215
2324
VA1VA2VD1 VD2
MOUT1
MOUT2
HEADR
HEADL
HEADC
LOUTR
LOUTL
VREF
XTL2IN
XTL2O UT
XTL1IN
XTL1O UT
SDIN
CLKIN
CLKOUT
RESET
PDN
SDOUT
TSOUT
TSIN
D/C
SCLK
FSYNC
28
27
12
Ω
29
31
12
Ω
30
600
Ω
33
0.0022 uF
NPO
600
Ω
32
0.0022 uF
NPO
21
10
11
6
7
1
4
5
12
13
44
41
40
35
43
42
1/2W
1/2W
0.1 uF
40pF
40pF
40pF
40pF
32
>
Ω
Headphone
> 1.0 uF
>
16.9344 MHz
24.576 MHz
Controller
Jack
+
+
1.0 uF
+
10 uF
>48
Ω
40 k
40 k
+5v
20k
AGND1 AGND2 DGND1 DG ND2
22 2 5 2 9
20k 20k
Note: AGND and DGND pins must be on the same ground plane.
Figure 1. Recommended Connection Diagram
DS76F2 7
CS4215
FUNCTIONAL DESCRIPTION
Overview
The CS4215 has two channels of 16-bit analogto-digital conversion and two channels of 16-bit
digital-to-analog conversion. Both the ADCs and
the DACs are delta-sigma converters. The ADC
inputs have adjustable input gain, while the DAC
outputs have adjustable output attenuation. Special features include a separate microphone input
with a 20 dB programmable gain block, an op-
tional 8-bit µ-law or A-law encoder/decoder, pins
for two crystals to set alternative sample rates,
direct headphone drive and mono speaker drive.
Control for the functions available on the
CS4215, as well as the audio data, are communicated to the device over a serial interface.
Separate pins for input and output data are provided, allowing concurrent writing to and
reading from the device. Data must be continually written for proper operation. Multiple
CS4215 devices may be attached to the same
data lines.
Analog Inputs
Unused analog inputs that are not selected have
a very high input impedance, so they may be
tied to AGND directly. Unused analog inputs
that are selected should be tied to AGND
through a 0.1uF capacitor. This prevents any DC
current flow.
Line Level Inputs
LINL and LINR are the line level input pins.
These pins are internally biased to the CMOUT
voltage. Figure 2 shows a dual op-amp buffer
which combines level shifting with a gain of 0.5
to attenuate the standard line level of 2 V
56 pF
Line In
Right
Example
Op-Amps
are
LT1013
Line In
Left
0.47 uF
0.47 uF
20 k
0.47 uF
20 k
10 k
_
+
+
_
5 k
10 k
150
0.01 uF
NPO
150
(pin 16)
0.47 uF
0.01 uF
NPO
rms
LINR
CMOUT
(pin 19)
LINL
(pin 18)
to
Figure 1, the recommended connection diagram,
shows examples of the external analog circuitry
recommended around the CS4215. An internal
multiplexer selects between line level inputs and
microphone level inputs.
Op-amps are run
from VA1, VA2 and
AGND.
Figure 2. DC Coupled Input.
56 pF
Input filters using a 150 Ω resistor and a .01 µF
NPO capacitor to ground are required to isolate
the input op-amps from, and provide a charge re-
Line In
Right
serve for, the switched-capacitor input of the
codec. The RC values may be safely changed
by a factor of two.
The HPF bit in Control Time Slot 2 provides a
high pass filter that will reduce DC offset on the
Line In
Left
analog inputs. Using the high pass filter will
cause slight distortions at very low frequencies.
8 DS76F2
Figure 3. AC Coupled Input.
0.47 uF
0.47 uF
150
150
LINR
(pin 16)
0.01 uF
NPO
NPO
0.01 uF
LINL
(pin 18)
CS4215
MINR
MINL
(Mono)
10 uF
10 uF
R6
2.2 k
+
C6
1 uF
+
C5
C2
+
1 uF
2.2 k
R3
+
C3
R4
22.1 k
VA+
2
3
R5
50 k
R2
50 k
5
6
C1 560 pF
C4
560 pF
NPO
C8
8
0.1 uF
1
4
U2
MC33078 or
MC33178
C7
7
A =20 dB
NPO
22.1 k
R1
C48
0.47 uF
+
1 uF
0.47 uF
C45
R56
150
C47
R57
150
C46
Microphone
Input Right
(pin 15)
NPO
0.01 uF
CMOUT
Microphone
Input Left
(pin 17)
NPO
0.01 uF
Figure 4. Optional Microphone Input Buffer
1 V
. The CMOUT reference level is used to
rms
level shift the signal. This level shifting allows
the line inputs to be DC coupled into the
CS4215. Minimum ADC offset results when the
line inputs are DC coupled (see Analog Characteristics Table).
Figure 3 shows an AC coupled input circuit for
signals centered around 0 Volts. The anti-aliasing RC filter presents a low impedance at high
frequencies and should be driven by a low impedance source.
Microphone Level Inputs
Internal amplifiers with a programmable 20 dB
gain block are provided for the microphone level
inputs, MINR and MINL. Figure 4 shows a single-ended input microphone pre-amplifier stage
with a gain of 23 dB. AC coupling is mandatory
for these inputs since any DC offset on the input
will be amplified by the codec.
The 20 dB gain block may be disabled using the
MLB bit in Control Time Slot 1. When disabled, the inputs become line level with full
scale inputs of 1 Vrms.
Adjustable Input Gain
The signals from the microphone or the line inputs are routed to a programmable gain circuit
which provides up to 22.5 dB of gain in 1.5 dB
steps. Level changes only take effect on zero
crossings to minimize audible artifacts, often referred to as "zipper noise". The requested level
change is forced if no zero crossing is found after 511 frames (10.6 ms at a 48 kHz frame rate).
A separate zero crossing detector exists for each
channel.
Analog Outputs
The analog outputs of the DACs are routed via
an attenuator to a pair of line outputs, a pair of
DS76F2 9
CS4215
headphone outputs and a mono monitor speaker
output.
Output Level Attenuator
The DAC outputs are routed through an attenuator, which provides 0 dB to 94.5 dB of
attenuation, adjustable in 1.5 dB steps. Level
changes are implemented using both analog and
digital attenuation techniques. Level changes
only take effect on zero crossings to minimize
audible artifacts. The requested level change is
forced if an analog zero crossing does not occur
within 511 frames (10.6 ms at a 48 kHz frame
rate). A separate zero crossing detector exists for
each channel.
Line Outputs
LOUTR and LOUTL output an analog signal,
centered around the CMOUT voltage. The mini-
mum recommended load impedance is 8 kΩ.
Figure 1 shows the recommended 1.0 µF DC
blocking capacitor with a 40 kΩ resistor to
ground. When driving impedances greater than
10 kΩ, this provides a high pass corner of
20 Hz. These outputs may be muted.
Headphone Outputs
HEADR and HEADL output an analog signal,
centered around the HEADC voltage. The default headphone output level (OLB = 0) contains
an optional 3 dB gain over the line outputs
which provides reasonable listening levels, even
with small amplitude digital sources. These outputs have increased current drive capability and
can drive a load impedance as low as 48 Ω. External 12 Ω series resistors reduce output level
variations with different impedance headphones.
The common return line from driving headphones should be connected to HEADC, which
is biased to the CMOUT voltage. This removes
the need for AC coupling, and also controls
where the return currents flow. All three head-
phone output lines are short-circuit protected.
These outputs may be muted.
Speaker Output
MOUT1 and MOUT2 differentially drive a small
loudspeaker, whose impedance should be greater
than 32 Ω. The signal is a summed version of
the right and left line output, tapped off prior to
the mute function, but after the attenuator. The
speaker output may be independently muted.
With OLB = 0, the speaker output also contains
a 3 dB gain over the line outputs. When
OLB = 1, the speaker outputs are driven at the
same level as the line outputs.
Some small speakers distort heavily when presented with low frequency energy. A high-pass
filter helps eliminate the low frequency energy
and can be implemented by AC coupling both
speaker terminals with a resistor to ground, on
the speaker side of the DC blocking capacitors.
The values selected would depend on the speaker
chosen, but typical values would be 22 µF for
the capacitors, with the positive side connected
to the codec, and 50 kΩ resistors. T his circuit is
contained on the CDB4215 evaluation board as
shown in the end of this data sheet.
Input Monitor Function
To allow monitoring of the input audio signal,
the output of the ADCs can be routed through a
monitor path attenuator, then digitally mixed into
the input data for the DACs (see the front page
block diagram). Changes in the input gain or
output level settings directly affect the monitor
level. If full scale data from the ADCs is added
to full scale digital data from the serial in terface,
clipping will occur.
Calibration
Both output offset voltage and input offset error
are minimized by an internal calibration cycle.
At least one calibration cycle must be invoked
10 DS76F2
FSYNC
SCLK
CLKOUT
8.5 CLKOUT's
11 CLKOUT's
Data Mode -Read and Write
TSIN
SCLK
1 SCLK
Control Mode - Read Only
CS4215
PIO Read
PIO Write
PIO Read
Notes:
DATA MODE READ - The data is sent out via SDOUT on the next frame.
1.
2.
CONTROL MODE READ - The data is sent out, via SDOUT, the same frame.
3.
DATA MODE READ, WRITE - are tied to the rising edge of FSYNC and CLKOUT.
They are independent of SCLK.
4.
CONTROL MODE READ - The PIO pins are sampled by a rising edge of SCLK.
Figure 5. PIO Pin Timing
after power up. A calibration cycle will occur
immediately after leaving the reset state. A calibration cycle will also occur immediately after
going from control mode to data mode (D/C going high). When powering up the CS4215, or
exiting the power down state, a minimum of
50 ms must occur, to allow the voltage reference
to settle, before initiating a calibration cycle.
This is achieved by holding RESET low or staying in control mode for 50 ms after power up or
exiting power down mode. The input offset error
will be calibrated for whichever input channel is
selected (microphone or line, using the IS bit).
Therefore, the IS bit should remain steady while
the codec is calibrating, although the other bits
input to the codec are ignored. Calibration takes
194 FSYNC cycles and SDOUT data bits will be
zero during this period. The A/D Invalid bit, ADI
(bit 7 in data time slot 6), will be high during
calibration and will go low when calibration is
finished.
Parallel Input/Output
Two pins are provided for parallel input/output.
These pins are open drain outputs and require
external pull-up resistors. Writing a zero turns on
the output transistor, pulling the pin to ground;
writing a one turns off the output transistor,
which allows an external resistor to pull the pin
high. When used as an input, a one must be written to the pin, thereby allowing an external
device to pull it low or leave it high. These pins
can be read in control mode and their state is
recorded in Control Register 5. These pins can
be written to and read back in data mode using
Data Register 7. Figure 5 shows the Parallel Input/Output timing.
DS76F2 11
CS4215
Clock Generation
The master clock operating the CS4215 may be
generated using the on-chip crystal oscillators, or
by using an external clock source. In all data
modes SCLK and FSYNC must be synchronous
to the selected master clock.
If the master clock source stops, the digital filters will power down after 5 µs to prevent
overheating. If FSYNC stops, the digital filters
will power down after approximately 1 FSYNC
period. The CS4215 will not enter the total
power down state.
Internal Clock Generation
Two external crystals may be attached to the
XTL1IN, XTL1OUT, XTL2IN and XTL2OUT
pins. Use of an external crystal requires additional 40 pF loading capacitors to digital ground
(see Figure 1). XTAL1 oscillator is intended for
use at 24.576 MHz and XTAL2 oscillator is intended for use at 16.9344 MHz, although other
frequencies may be used. The gain of the internal inverter is slightly higher for XTAL1,
ensuring proper operation at >24 MHz frequencies. The crystals should be parallel resonant,
fundamental mode and designed for 20 pF loading (equivalent to a 40 pF capacitor on each leg).
If XTAL1 or XTAL2 is not selected as the master clock, that particular crystal oscillator is
powered down to minimize interference. If a
crystal is not needed, the XTL-IN pin should be
grounded. An example crystal supplier is CAL
Crystal, telephone number (714) 991-1580.
FSYNC and SCLK must be synchronous to the
master clock. When using the codec in slave
mode with one of the crystals as master clock,
the controller must derive FSYNC and SCLK
from the crystals, i.e. via CLKOUT. Note that
CLKOUT will stop in a low condition within
two periods after D/C goes low.
An internally generated clock which is 256 times
the sample rate (FSYNC rate) is output
(CLKOUT) for potential use with an external
AES/EBU transmitter, or another CS4215. No
glitch occurs on CLKOUT when selecting alternate clock sources. CLKOUT will stop in a low
condition within two periods after D/C goes low,
assuming one of the crystal oscillators is selected, or either CLKIN or SCLK is the master
clock source and is continuous. The duty cycle
of CLKOUT is 50% if the master clock is one of
the crystal oscillators and the DFR bits are 0, 1,
2, 6 or 7. If the DFR bits are 3 or 5, the duty
cycle is 33% (high time). If the DFR bits are 4
then CLKOUT has the timing shown in Figure 6.
If the master clock is SCLK or CLKIN, the duty
cycle of CLKOUT will be the same as the master clock source.
1213
1/(128 x FSYNC) 1/(128 x FSYNC)
Figure 6. CLKOUT duty cycle using the on-chi p
crystal oscillator when DFR = 4
( typically FSYNC = 37.8 kHz)
1213
External Clock
An external clock input pin (CLKIN) is provided
for potential use with an external AES/EBU receiver, or an already existing system clock.
When MCK2 = 0, the input clock must be exactly 256 times the sample rate, and FSYNC and
SCLK must be synchronous to CLKIN. When
MCK2 = 1 the DFR bits allow various divide
ratios off the CLKIN frequency.
Alternatively, an external high frequency clock
may be driven into XTL1IN or XTL2IN. The
correct clock source must be selected using the
MCK bits. Manipulating DFR bits will allow
various divide ratios from the clock to be se-
12 DS76F2
CS4215
lected. SCLK and FSYNC must be synchronous
to the external clock.
As a third alternative, SCLK may be programmed to be the master clock input. In this
case, it must be 256 times Fs.
Serial Interface
The serial interface of the CS4215 transfers digital audio data and control data into and out of
the device. Multiple CS4215 devices may share
the same data lines. DSP’s supported include the
Motorola 56001 in network mode and a subset
of the ‘CHI’ bus from AT&T/Intel.
Serial Interface Signals
Figure 7 shows an example of two CS4215 devices connected to a common controller. The
Serial Data Out (SDOUT) and Serial Data In
(SDIN) lines are time division multiplexed between the CS4215s.
The serial interface clock, SCLK, is used for
transmitting and receiving data. SCLK can be
generated by one of the CS4215s, or it can be
input from an external SCLK source. When generated by an external source, SCLK must be
synchronous to the master clock. Data is transmitted on the rising edge of SCLK and is
received on the falling edge of SCLK. The
SCLK frequency is always equal to the bit rate.
The Frame Synchronizing signal (FSYNC) is
used to indicate the start of a frame. It may be
output from one of the CS4215s, or it may be
generated from an external controller. If FSYNC
is generated externally, it must be high for at
least 1 SCLK period, and it must fall at least
2 SCLKs before the start of a new frame (see
Figure 8). It must also be synchronous to the
master clock. The frequency of FSYNC is equal
to the system sample rate (see Figure 8). Each
CS4215 requires 64 SCLKs to transfer all the
data. The SCLK frequency can be set to 64, 128,
or 256 bits per frame, thereby allowing for 1, 2
or 4 CS4215s connected to the same bus.
In a typical multi-part scenario, one CS4215 (the
master) would generate FSYNC and SCLK,
while the other CS4215s (the slaves) would receive FSYNC and SCLK. The CLKOUT of the
master would be connected to the CLKIN of
each slave device as shown in Figure 7. Then,
the master device would be programmed for the
desired sample frequency (assuming one of the
crystals is selected as the clock source), the number of bits per frame, and for SCLK and FSYNC
to be outputs. The slave devices would be programmed to use CLKIN as the clock source, the
same number of bits per frame, and for SCLK
and FSYNC to be inputs. Since CLKOUT is al-
SCLK
SDIN
SDOUT
FSYNC
TSIN
TSOUT
D/C
PDN
RESET
SCLK
SDIN
SDOUT
FSYNC
TSIN
TSOUT
D/C
PDN
RESET
CS4215
XTL1IN
XTL1OUT
A
XTL2IN
XTL2OUT
Master
CLKOUT
CS4215
CLKIN
B
Slave
Controller
SCLK
SDIN
SDOUT
FSYNC
D/C
Figure 7. Multiple CS4215’s
DS76F2 13
FSYNC
TSINA
CS4215
T1
TSn
TSOUTA
TSINB
TSOUTB
SCLK
FSYNC
TSIN
DATA
TSOUT
TS8
TS1 TS2 TS3 TS2 TS7 TS8
TS8 TS1
DEVICE BDEVICE A
T1 1/Frame Rate or 1/System Sample Rate
TSn Time slot numbers
Figure 8. Seria l Interface Timing for 2 CS42 15’s
1 2 8 9 16 17 18 64 65 66 67
70 70
TS1 TS2
10
7610 6576 1
6 1
0
TS3 TS8
TS1
68
Figure 9. Frame Sync and Bit Offset Timing
1 2 64 128 2 65 6665 66 1 64
SCLK
FSYNC,
TSIN A
TSOUT A,
TSIN B
TSOUT B
SDIN
SDOUT
D/C
3 4 67 68 3 4
Control to A Control to B
_
Control Mode
Control to A
Control from A Control from B
5
Figure 10. Control Mode Timing for 2 CS4215’s
14 DS76F2
CS4215
ways 256 times the sample frequency and scales
with the selected sample frequency on the master, the slave devices will automatically scale
with changes in the master codec’s sample frequency.
CS4215s are time division multiplexed onto the
bus using the Time Slot Out (TSOUT) and Time
Slot In (TSIN) signals. TSOUT is an output signal that is high for one SCLK bit time, and
indicates that the CS4215 is about to release the
bus. TSIN is an input signal that informs the
CS4215 that the next time slot is available for it
to use. The first device in the chain uses FSYNC
as its TSIN signal. All subsequent devices use
the TSOUT of the previous device as its TSIN
input. TSIN must be high for at least 1 SCLK
period and fall at least 2 SCLKs before start of a
new frame.
Serial Interface Operation
The serial interface format has a variable number
of time slots, depending on the number of
CS4215s attached to the bus. All time slots have
8 bits. Each CS4215 requires 8 time slots (64
bits) to communicate all data (see Figure 9).
CONTROL MODE
The Control Mode is used to set up the CS4215
for subsequent operation in Data Mode by loading the internal control registers. Control mode is
asserted by bringing D/C low. If D/C is low during power up, then the CS4215 will enter control
mode immediately. The SCLK and FSYNC pins
are tri-stated, and the CS4215 will receive SCLK
and FSYNC from an external source. If the
CS4215 is in master mode (SCLK and FSYNC
are outputs) and D/C is brought low, then SCLK
& FSYNC will continue to be driven for a minimum of 4 and a maximum of 12 SCLKs, if the
ITS bit = 0. If ITS is 1, SCLK and FSYNC will
three-state immediately after D/C goes low. If
D/C is brought low when the codec is programmed as master with ITS=0, the codec will
timeout and release FSYNC and SCLK within
100µs. The values in the control registers for
control of the serial ports are ignored in control
mode. The data received on SDIN is stored into
the control registers which have addresses
matching their time slots. The data in the registers is transmitted on SDOUT with the time slot
equal to the register number (see Figure 10).
The steps involved when going from data mode
to control mode and back are shown in the flow
chart in Figure 11.
Control Formats
The CS4215 control registers have the functions
and time slot assignments shown in Table 1. The
register address is the time slot number when
D/C is 0. Reserved bits should be written as 0
and could be read back as 0 or 1. When comparing data read back, reserved bits should be
masked. The SDOUT pin goes into a
high-impedance state prior to Time Slot 1 and
after Time Slot 8. The data listed below the register is its reset state.
The parallel port register is used to read and
write the two open-drain input/output pins. The
outputs are all set to 1 on RESET. PIO bits are
read only in control mode. Note that, since PIO
signals are open drain signals, an external device
Time slot Description
1 Status
2 Data Format
3 Serial Port Control
4Test
5 Parallel Port
6 RESERVED
7 Revision
8 RESERVED
Table 1. Co ntrol Registers
DS76F2 15
may drive them low even when they have been
programmed as highs. Therefore, the value read
back may differ from the value written. In the
data mode, (D/C=1), this register can be read
and written to through the serial port as part of
the Input Settings Registers. In control mode,
(D/C=0) these bits can only be read.
CS4215
16 DS76F2
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