CIRRUS LOGIC CS1500 Service Manual

NC

STBY

IAC

FB

NC
VDD
GD
GND

1
2
3
4

8
7
6
5

8-lead SOIC

D2

C1

D1

CS1500

C2

L

B

C3

Q1

6

2

8

5

7

3

1

R1a

R1b

R2a

R2b

R3

FB

GD

NC

STBY

GND

VDD

IAC

NC

R

AC

R

FB

BR1

AC

Mains

Regulated

DC Outp u t

4

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CONFIDENTIAL

Digital Power Factor Correction IC

CS1500

Features & Description

 Digital EMI Noise Shaping
 Excellent Efficiency Under All Load Conditions
 Minimal External Devices Required
 Optimized Digital Loop Compensation
 Comprehensive Safety Features

• Undervoltage Lockout (UVLO)

• Output Overvoltage Protection

• Input Current Limiting

• Output Overpower Protection

• Input Brownout Protection

• Open/short Loop Protection for IAC & FB Pins

• Thermal Shutdown

Description

The CS1500 is a high-performance power factor correction (PFC)
controller for universal AC input, which uses a proprietary digital
algorithm for discontinuous conduction mode (DCM) with variable
on-time and variable frequency control, ensuring unity power factor.

The CS1500 incorporates all the safety features necessary for
robust and compact PFC stages. In addition, it has burst mode
control to lower the light-load/standby losses to a minimum.
Protection features such as overvoltage, overcurrent, overpower,
open- and short-circuit protection, overtemperature, and brownout
help protect the device during abnormal transient conditions.

The digital controller optimizes the system stability and transient
performance, simplifies the PFC design, reduces the external
component count and BOM costs. The simple design and
minimum cost makes CS1500 the ideal choice for PFC up to 300
watts.

Pin Assignments

Advance Product Information

Cirrus Logic, Inc.

http://www.cirrus.com

This document contains information for a product under development.
Cirrus Logic reserves the right to modify this product without notice.

Copyright  Cirrus Logic, Inc. 2010

(All Rights Reserved)

MAY ‘10

DS849A6

May ?$shortyear>

CONFIDENTIAL

Table 1. Pin Descriptions

CS1500

Pin Name Pin # I/O

NC

STBY

1, 8 -

2IN

IAC

FB

GND

GD

3IN

4IN

5-

6OUT

VDD

7IN

Description

NC — No connections
Remote On/Off Control — A voltage below 0.8 V shuts down the IC (not latched) and

brings the device into low power consumption mode. The input has an internal 600 kΩ
pull-up resistor to the VDD pin and should be driven with an open-collector device.

Rectifier Voltage Sense — A current proportional to the rectified line voltage (V
fed into this pin. The current is measured with an A/D converter.

Link Voltage Sense — A current proportional to the output link voltage (V
PFC is fed into this pin. The current is measured with an A/D converter.

Ground — Current return for both the input signal portion of the IC and the gate driver.
Gate Driver Output — The totem pole stage is able to drive the power MOSFET with a

peak current of 0.5 A source and 1.0 A sink. The high-level voltage of this pin is
clamped at V

IC Supply Voltage — Supply voltage of both the input signal portion of the IC and the
gate driver.

to avoid excessive gate voltages.

Z

link

rect

) of the

) is

2 DS849A6

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CONFIDENTIAL

1. CHARACTERISTICS AND SPECIFICATIONS

1.1 Absolute Maximum Ratings

Pin Symbol Parameter Value Unit

7V

DD

1,2,3,4,8 - Analog Input Maximum Voltage -0.5 to V

3,4 - Analog Input Maximum Current 50 mA

6V

GD

6IGDGate Drive Output Current -1.0 / +0.5 A

-P

- θ
T

-T

-T

Stg

IC Supply Voltage V

Z

Gate Drive Output Voltage -0.3 to V

Total Power Dissipation @ TA=50° C 600 mW

D

Junction-to-Ambient Thermal Impedance 107 ºC / W

JA

A

Operating Ambient Temperature Range
Junction Temperature Operating Range -40 to +125 ºC

J

1

-40 to +125 ºC

Storage Temperature Range -65 to +150 ºC

CS1500

Z

Z

V
V

V

1.2 Electrical Characteristics

(TA = 25º C, VDD = 13V, -40º < TJ < +125º C, CL=1nF between pin GD and GND, all voltages are measured with respect to
GND; all current are positive when flowing into the IC; unless otherwise specified). Recommended V

Parameter Condition Symbol Min Typ Max Unit

VDD Supply Voltage

Turn-on Threshold Voltage V
Turn-off Threshold Voltage (UVLO) V

Increasing V

DD

Decreasing V

DD

UVLO Hysteresis V
Zener Voltage I

=20mA V

DD

DD(on)
DD(off)

Hys

Z

8.4 8.8 9.3 V

7.1 7.4 7.9 V

-1.3-V

17.0 17.9 18.5 V

VDD Supply Current

Start-up Supply Current V

DD=VDD(on)

Standby Supply Current STBY
Operating Supply Current C

=1nF, fsw=70kHz I

L

<0.8V I

I

ST
SB
DD

-6880μA

-80112μA

-1.71.9mA

PFC Gate Drive

Maximum Operating Frequency
Minimum Operating Frequency
Maximum Duty Cycle

6

6

6

Output Source Resistance I
Output Sink Resistance I
Rising Time C
Falling Time C
Output Voltage Low State I
Output Voltage High State I

VDD = 13V f
VDD = 13V f
VDD = 13V D

=100mA,VDD = 13V R

GD

= -200mA,VDD = 13V R

GD

=1nF,VDD = 13V t

L

=1nF,VDD = 13V t

L

= -200mA,VDD = 13V Vol - 0.9 1.3 V

GD

=100mA,VDD = 13V Voh 11.3 11.8 - V

GD

SW(max)

SW(min)

max

OH
OL

r
f

62 66 70 kHz
20 22 23 kHz
64 66 68 %

-9-Ω

-6-Ω

-3245ns

-1525ns

= 10 – 15 V.

DD

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CONFIDENTIAL

Parameter Condition Symbol Min Typ Max Unit

Feedback & Protection

Reference Current I
Output Voltage at Startup Mode 25º C, 115 VAC V
Output Voltage at Normal Mode V
Overvoltage Protection Threshold 25º C, 115 VAC V
Overvoltage Protection Hysteresis V

Overpower Protection Threshold
Overpower Protection Recovery

Input Brownout Protection Threshold 25º C, GDRV turns off V
Input Brownout Recovery Threshold 25º C, GDRV turns on V

Thermal Protection

Thermal Shutdown Threshold T
Thermal Shutdown Hysteresis T

STBY Input

5

Logic Threshold Low - - 0.8 V
Logic Threshold High Vdd-0.8 - - V

2,3

REF

O(startup)

O(nom)

OVP

OVP(Hy)

2,4

2,4

1

25º C, 115 VAC - 125 - %
25º C, 115 VAC - 100 - %

BP(th)

BR

SD

SD(Hy)

-129-μA

-360-V

-400-V

415 418 421 V

-4-V

62 65 68 Vrms
77 80 83 Vrms

130 143 155 ºC

-9-ºC

CS1500

NOTES:

1. Specifications guaranteed by design & characterization and correlation with statistical process controls.

2. Specification are based upon a PFC system configured for AC input of 90-265 VAC (Sine), 45/65 Hz, V
R

=3x1.0 MΩ, RFB=3x1.0 MΩ, C3 = 180 μF, LB= 360 μH, 90 W. For othe r V

AC

Application Example.

3. Detailed Calculation See Section 4 Application Example.

4. Overpower protection is scaled to rated power.

5. STBY

is designed to be driven by an open collector. The input is internally pulled up with a 600 kΩ resistor.

6. Normal operation mode, see Section 3.2.

voltages, refer to Section 4

link

=400V,

link

4 DS849A6

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0

0.5

1

1.5

2

2.5

3

3.5

0 1 2 3 4 5 6 7 8 9 10111213 141516

VDD (V)

I

DD

(mA)

CL = 1 nF

f

SW

= 70 kHz

T

A

= 25 °C

Falling

Rising

7

8

9

10

11

12

13

-50 0 50 100 150

TEMP (oC)

V

DD

(V)

Startup

UVLO

0

0.5

1

1.5

2

-50 0 50 100 150

TEMP (oC)

UVLO Hysteresis (V)

17

17.5

18

18.5

19

-50 0 50 100 150

TEMP (oC)

V

Z

(V)

IDD = 20 mA

Figure 1. Supply Current vs. Supply Voltage Figure 2. Start-up & UVLO vs. Temp

Figure 3. UVLO Hysteresis vs. Temp Figure 4. VDD Zener Voltage vs. Temp

CONFIDENTIAL

2. TYPICAL ELECTRICAL PERFORMANCE

CS1500

DS849A6 5

May ?$shortyear>

385

390

395

400

405

410

415

420

425

-50 0 50 100 150

Temperature (°C)

V

link

(V)

OVP

Normal

Frequency (kHz)

Min Freq

Max Freq

TEMP (oC)

0

10

20

30

40

50

60

70

80

90

100

-60 -40 -20 0 20 40 60 80 100 120 140

0

2

4

6

8

10

12

14

-60 -40 -20 0 40 100 120 140

Gate Resistor (ROH, ROL) Temp (oC)

Z

out

(Ohm)

Source

Sink

VDD = 13 V

I

source

= 100 mA

I

sink

= 200 mA

20 60 80

-50 0 50 100 150

TEM P (oC)

Supply Current (mA)

Start-up

Standby

0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8
Operating

VDD = 13 V

C

L

= 1 nF

f

SW

= 70 kHz

Start-up

Standby

Figure 5. Supply Current (ISB, IST, IDD) vs. Temp Figure 6. Min/Max Operating Frequency vs. Temp

Figu r e 7 . Gate Resistance (R

OH

, ROL) vs. Temp Figure 8. OVP vs. Temp

CONFIDENTIAL

CS1500

6 DS849A6

IAC

FB

STBY

3

4

2

CS1500

GD

6

VDD

7

NC

8

GND

5

Processor

Logic

NC

1

PWM

Driver

Oscillator

Protection

ADC

T

on

0.001126
V

rect

------------------------ -

≤

May ?$shortyear>

CONFIDENTIAL

3. INTRODUCTION

Figure 9. CS1500 Block Diagram

The CS1500 digital power factor controller operates in variable
on-time, variable frequency, discontinuous conduction mode
(DCM). The CS1500 uses a proprietary digital algorithm to
maximize the efficiency and reduce the conductive EMI.

The analog-to-digital converter (ADC) shown in the CS1500
block diagram in Figure 9 is used to sense the PFC output
voltage ( V

) and the rectified AC line voltage ( V

link

rect

) by
measuring currents through their respective resistors. The
magnitudes of these currents are measured as a proportion of a
reference current (I

) that functions as the reference for the

REF

ADCs. The digital signal is then processed in a control algorithm
which determines the behavior of the CS1500 during start-up,
normal operation, and under fault conditions, such as brownout,
overvoltage, overcurrent, overpower, and over-temperature
conditions.

• DCM with Variable On-Time, Variable Switching Fre­quency

The CS1500 PFC switching frequency varies with the

on a cycle-by-cycle basis, and its digital algorithm

V

rect

calculates the on-time accordingly for unity power factor.
Unlike traditional Critical Conduction Mode (CRM) PFC
controller, CS1500 operates at its low switching frequen­cy near the zero-crossing point of the AC input voltage,
even no switching at all, and it operates at its high switch­ing frequency at the peak of its AC input voltage (this is
the opposite of the switching frequency profile for a CRM
PFC controller), thus CS1500 reduces switching losses
especially under light-load conditions, spreads conducted
EMI energy peaks over a wide frequency band and in­creases overall system efficiency.

• Optimized Digital Loop Compensation

The proprietary digital control engine optimizes the feed­back error signal using an adaptive control algorithm, im-

DS849A6 7

proves system stability and transient response. No
external feedback error signal compensation components
are required.

• Overcurrent Mitigation

The CS1500s digital controller algorithm limits the ON
time of the Power MOSFET by the following equation:

Where T
turned on and V

is the max time that the power MOSFET is

on

is the rectified line voltage. In the

rect

event of a sudden line surge or sporadic, high dv/dt line
voltages, this equation may not limit the ON time appro­priately. For this type of line disturbance, additional pro­tection mechanisms such as fusible resistors, fast-blow
fuses, or other current-limiting devices are recommend­ed.

• Over Voltage Protection

Under steady-state conditions, the voltage loop keeps
PFC output voltage close to its nominal value. Under light
load startup or feedback loop open conditions, the output
voltage may pass the overvoltage protection threshold.
The digital control engine initiates a fast response loop to
shut down gate driving signal to reduce the energy deliv­ered to the output for PFC capacitor protection. When the
link voltage drop below V
normal operation.

OVP-VOVP(Hy)

, PFC resumes

CS1500