Cirrus Logic CRD5376 User Manual
CRD5376
Multichannel Seismic Reference Design
Features
z Four Channel Seismic Acquisition Node
– CS3301A geophone amplifiers (2x)
– CS3302A hydrophone amplifiers (2x)
– CS5372A dual ∆Σ modulators (2x)
– CS5376A quad digital filter (1x)
– CS4373A ∆Σ test DAC (1x)
– Precision voltage reference
– Clock recovery PLL
z On-board Microcontroller
– SPI™ interface to digital filter
– USB communication with PC
z PC Evaluation Software
– Register setup & control
– FFT frequency analysis
– Time domain analysis
– Noise histogram analysis
General Description
The CRD5376 board is a reference design for the Cirrus
Logic multichannel seismic chip set. Data sheets for the
CS3301A, CS3302A, CS4373A, CS5371A/72A, and
CS5376A devices should be consulted when using the
CRD5376 reference design.
Pin headers connect external differential geophone or
hydrophone sensors to the analog inputs of the measurement channels. An on-board test DAC creates
precision differential analog signals for in-circuit performance testing without an external signal source.
The reference design includes an 8051-type microcontroller with hardware SPI™ and USB serial interfaces.
The microcontroller communicates with the digital filter
via SPI and with the PC evaluation software via USB.
The PC evaluation software controls register and coefficient initialization and performs time domain, histogram,
and FFT frequency analysis on captured data.
The CRD5376 features a special breakout connector
used to detach the acquisition and control sections for
remote sensor applications.
ORDERING INFORMATION
CRD5376 Reference Design
www.cirrus.com
Copyright © Cirrus Logic, Inc. 2007
(All Rights Reserved)
NOV ‘07
DS612RD2
REVISION HISTORY
Revision Date Changes
RD1 FEB 2006 Initial Release.
RD2 NOV 2007 BOM change to latest revision of silicon. Minor layout enhancements.
CRD5376
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find the one nearest to you go to www.cirrus.com
IMPORTANT NOTICE
Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of
relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility
is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of
patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied
under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the
information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated
circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes,
or for creating any work for resale.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE
PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS
OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER.
IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER
AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM
ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.
Windows, Windows 2000, Windows XP, and Windows NT are trademarks or registered trademarks of Microsoft Corporation.
Intel and Pentium are registered trademarks of Intel Corporation.
USBXpress is a registered trademark of Silicon Laboratories, Inc.
SPI is a trademark of Motorola, Inc.
Microwire is a trademark of National Semiconductor Corporation.
I2C is a registered trademark of Philips Semiconductor.
I
2 DS612RD2
CRD5376
TABLE OF CONTENTS
1. INITIAL SETUP ......................................................................................................................... 5
1.1 Kit Contents ....................................................................................................................... 5
1.2 Hardware Setup ................................................................................................................. 5
1.2.1 Default Jumper Settings ........................................................................................ 6
1.3 Software Setup .................................................................................................................. 7
1.3.1 PC Requirements .................................................................................................. 7
1.3.2 Seismic Evaluation Software Installation .............................................................. 7
1.3.3 USBXpress Driver Installation ............................................................................... 7
1.3.4 Launching the Seismic Evaluation Software ......................................................... 8
1.4 Self-Testing CRD5376 .......................................................................................................9
1.4.1 Noise Test ............................................................................................................. 9
1.4.2 Distortion Test ..................................................................................................... 10
2. HARDWARE DESCRIPTION ................................................................................................. 11
2.1 Block Diagram ................................................................................................................ 11
2.2 Analog Hardware ............................................................................................................. 12
2.2.1 Analog Inputs ...................................................................................................... 12
2.2.2 Differential Amplifiers .......................................................................................... 16
2.2.3 Delta-Sigma Modulators ..................................................................................... 17
2.2.4 Delta-Sigma Test DAC ........................................................................................ 18
2.2.5 Voltage Reference .............................................................................................. 18
2.3 Digital Hardware .............................................................................................................. 19
2.3.1 Digital Filter ......................................................................................................... 19
2.3.2 Microcontroller .................................................................................................... 22
2.3.3 Phase Locked Loop ............................................................................................ 25
2.3.4 RS-485 Telemetry ............................................................................................... 26
2.3.5 UART Connection ............................................................................................... 28
2.3.6 External Connector ............................................................................................. 28
2.4 Power Supplies ................................................................................................................ 28
2.4.1 Analog Voltage Regulators ................................................................................. 29
2.5 PCB Layout ..................................................................................................................... 29
2.5.1 Layer Stack ......................................................................................................... 29
2.5.2 Differential Pairs .................................................................................................. 30
2.5.3 Bypass Capacitors .............................................................................................. 31
3. SOFTWARE DESCRIPTION .................................................................................................. 32
3.1 Menu Bar ......................................................................................................................... 32
3.2 About Panel ..................................................................................................................... 33
3.3 Setup Panel ..................................................................................................................... 34
3.3.1 USB Port ............................................................................................................. 35
3.3.2 Digital Filter ......................................................................................................... 36
3.3.3 Analog Front End ................................................................................................ 37
3.3.4 Test Bit Stream ................................................................................................... 37
3.3.5 Gain/Offset .......................................................................................................... 38
3.3.6 Data Capture ....................................................................................................... 39
3.3.7 External Macros .................................................................................................. 40
3.4 Analysis Panel ................................................................................................................. 41
3.4.1 Test Select .......................................................................................................... 42
3.4.2 Statistics .............................................................................................................. 43
3.4.3 Plot Enable .......................................................................................................... 43
3.4.4 Cursor ................................................................................................................. 44
3.4.5 Zoom ................................................................................................................... 44
3.4.6 Refresh ............................................................................................................... 44
DS612RD2 3
CRD5376
3.4.7 Harmonics ........................................................................................................... 44
3.4.8 Spot Noise ........................................................................................................... 44
3.4.9 Plot Error ............................................................................................................. 44
3.5 Control Panel ................................................................................................................... 45
3.5.1 DF Registers ....................................................................................................... 46
3.5.2 DF Commands .................................................................................................... 46
3.5.3 SPI ......................................................................................................................46
3.5.4 Macros ................................................................................................................ 47
3.5.5 GPIO ................................................................................................................... 47
3.5.6 Customize ........................................................................................................... 48
3.5.7 External Macros .................................................................................................. 48
4. BILL OF MATERIALS ........................................................................................................... 49
5. LAYER PLOTS ...................................................................................................................... 51
6. SCHEMATICS ........................................................................................................................ 57
LIST OF FIGURES
Figure 1. CRD5376 Block Diagram ............................................................................................... 11
Figure 2. Differential Pair Routing ................................................................................................. 30
Figure 3. Quad Group Routing ...................................................................................................... 30
Figure 4. Bypass Capacitor Placement ......................................................................................... 31
LIST OF TABLES
Table 1. Amplifier Pin 13 Jumper Settings ...................................................................................... 6
Table 2. SDTKI Input Jumper Settings............................................................................................6
Table 3. PLL Clock Input Jumper Settings ...................................................................................... 6
Table 4. Pin Header Input Connections ........................................................................................ 12
Table 5. Analog Switch Settings.................................................................................................... 15
Table 6. Amplifier Pin 13 Jumper Settings .................................................................................... 16
Table 7. SDTKI Input Jumper Settings.......................................................................................... 22
Table 8. Clock Input / Output Jumper Settings.............................................................................. 25
4 DS612RD2
1. INITIAL SETUP
1.1 Kit Contents
The CRD5376 reference design kit includes:
• CRD5376 reference design board
• USB cable (A to mini-B)
• Software download information card
The following are required to operate CRD5376, and are not included:
• Bipolar power supply with clip lead outputs (± 3.3 V, 300 mA)
• PC running Windows XP
• Internet access to download the evaluation software
®
or Windows 2000™ with an available USB port
1.2 Hardware Setup
CRD5376
To set up the CRD5376 reference design hardware:
• Verify all jumpers are in the default settings (see next section).
• With power off, connect the CRD5376 power inputs to the power supply outputs.
J8 pin 17 = -3.3 V
J8 pin 18 = 0 V
J8 pin 19 = +3.3 V
J8 pin 20 = 0 V
• Connect the USB cable between the CRD5376 USB connector and the PC USB port.
• Proceed to the Software Setup section to install the evaluation software and USB driver.
DS612RD2 5
1.2.1 Default Jumper Settings
* indicates the default jumper installation for CRD5376.
Amplifier CS3301A CS3302A
CH1 U16 *R128 + *R84 R129
CH2 U2 *R86 + *R92 R87
CH3 U33 R95 + R132 *R94
CH4 U3 R58 + R100 *R59
Table 1. Amplifier Pin 13 Jumper Settings
CS5376A uController MCLK/2
SDTKI *R74 R83
CRD5376
Table 2. SDTKI Input Jumper Settings
Input Clock Jumper
1.024 MHz *R16
2.048 MHz R18
4.096 MHz R82
Table 3. PLL Clock Input Jumper Settings
6 DS612RD2
1.3 Software Setup
1.3.1 PC Requirements
The PC hardware requirements for the Cirrus Seismic Evaluation system are:
CRD5376
• Windows XP
•Intel
• VGA resolution or higher video card
• Minimum 64MB RAM
• Minimum 40MB free hard drive space
®
Pentium® 600MHz or higher microprocessor
®
, Windows 2000™, Windows NT™
1.3.2 Seismic Evaluation Software Installation
Important: For reliable USB communication, the USBXpress® driver must be installed after the Seismic
Evaluation Software installation but before launching the application. The USBXpress driver files are in-
cluded in a sub-folder as part of the installation.
To install the Cirrus Logic Seismic Evaluation Software:
• Go to the Cirrus Logic Industrial Software web page (http://www.cirrus.com/industrialsoftware
the link for “Cirrus Seismic Evaluation GUI” to get to the download page and then click the link for “Cir-
rus Seismic Evaluation GUI Release Vxx” (xx indicates the version number).
• Read the software license terms and click “Accept” to download the “SeismicEvalGUI_vxx.zip” file to
any directory on the PC.
• Unzip the downloaded file to any directory and a “Distribution\Volume1” sub-folder containing the installation application will automatically be created.
• Open the “Volume1” sub-folder and run “setup.exe”. If the Seismic Evaluation Software has been previously installed, the uninstall wizard will automatically remove the previous version and you will need
to run “setup.exe” again.
). Click
• Follow the instructions presented by the Cirrus Seismic Evaluation Installation Wizard. The default installation location is “C:\Program Files\Cirrus Seismic Evaluation”.
An application note, AN271 - Cirrus Seismic Evaluation GUI Installation Guide, is available from the Cirrus
Logic web site with step-by-step instructions on installing the Seismic Evaluation Software.
1.3.3 USBXpress Driver Installation
Important: For reliable USB communication, the USBXpress driver must be installed after the Seismic
Evaluation Software installation but before launching the application. The USBXpress driver files are in-
cluded in a sub-folder as part of the installation.
The Cirrus Logic Seismic Evaluation Software communicates with CRD5376 via USB using the USBXpress driver from Silicon Laboratories (http://www.silabs.com
files are included as part of the installation package.
To install the USBXpress driver (after installing the Seismic Evaluation Software):
• Connect CRD5376 to the PC through an available USB port and apply power. The PC will detect
DS612RD2 7
). For convenience, the USBXpress driver
CRD5376
CRD5376 as an unknown USB device.
• If prompted for a USB driver, skip to the next step. If not, using Windows Hardware Device Manager
go to the properties of the unknown USB API device and select “Update Driver”.
• Select “Install from a list or specific location”, then select “Include this location in the search” and then
browse to “C:\Program Files\Cirrus Seismic Evaluation\Driver\”. The PC will recognize and install the
USBXpress device driver.
• After driver installation, cycle power to CRD5376. The PC will automatically detect it and add it as a
USBXpress device in the Windows Hardware Device Manager.
An application note, AN271 - Cirrus Seismic Evaluation GUI Installation Guide, is available from the Cirrus
Logic web site with step-by-step instructions on installing the USBXpress driver.
1.3.4 Launching the Seismic Evaluation Software
Important: For reliable USB communication, the USBXpress driver must be installed after the Seismic
Evaluation Software installation but before launching the application. The USBXpress driver files are in-
cluded in a sub-folder as part of the installation.
To launch the Cirrus Seismic Evaluation Software, go to:
• Start
or:
• C:\Program Files\Cirrus Seismic Evaluation\SeismicGUI.exe
For the most up-to-date information about the software, please refer to it’s help file:
• Within the software: Help
or:
• C:\Program Files\Cirrus Seismic Evaluation\SEISMICGUI.HLP
Ö
Programs Ö Cirrus Seismic Evaluation Ö Cirrus Seismic Evaluation
Ö
Contents
8 DS612RD2
CRD5376
1.4 Self-Testing CRD5376
Noise and distortion self-tests can be performed once hardware and software setup is complete.
First, initialize the CRD5376 reference design:
• Launch the evaluation software and apply power to CRD5376.
• Click ‘OK’ on the About panel to get to the Setup panel.
• On the Setup panel, select Open Target on the USB Port sub-panel.
• When connected, the Board Name and MCU code version will be displayed.
1.4.1 Noise Test
Noise performance of the measurement channel can be tested as follows:
• Set the controls on the Setup panel to match the picture:
DS612RD2 9
• Once the Setup panel is set, select Configure on the Digital Filter sub-panel.
• After digital filter configuration is complete, click Capture on the Data Capture sub-panel.
• Once the data record is collected, the Analysis panel is automatically displayed.
• Select Noise FFT from the Test Select control to display the calculated noise statistics.
• Verify the noise performance (S/N) is 124 dB or better.
1.4.2 Distortion Test
• Set the controls on the Setup panel to match the picture:
CRD5376
• Once the Setup panel is set, select Configure on the Digital Filter sub-panel.
• After digital filter configuration is complete, click Capture on the Data Capture sub-panel.
• Once the data record is collected, the Analysis panel is automatically displayed.
• Select Signal FFT from the Test Select control to display the calculated noise statistics.
• Verify the distortion performance (S/D) is 112 dB or better.
10 DS612RD2
2. HARDWARE DESCRIPTION
2.1 Block Diagram
CRD5376
Figure 1. CRD5376 Block Diagram
Major blocks of the CRD5376 reference design include:
• CS3301A Geophone Amplifier (2x)
• CS3302A Hydrophone Amplifier (2x)
• CS5372A Dual ∆Σ Modulators (2x)
• CS5376A Digital Filter
• CS4373A ∆Σ Test DAC
• Analog Switch Multiplexer
• Precision Voltage Reference
• Microcontroller with USB
• Phase Locked Loop
• RS-485 Transceivers
• Voltage Regulators
DS612RD2 11
CRD5376
2.2 Analog Hardware
2.2.1 Analog Inputs
2.2.1.1 External Inputs - INA
External signals into CRD5376 are from two major classes of sensors, moving coil geophones and piezoelectric hydrophones. Geophones are low-impedance sensors optimized to measure vibrations in land
applications. Hydrophones are high-impedance sensors optimized to measure pressure in marine applications. Other sensors for earthquake monitoring and military applications are considered as geophones
for this datasheet.
External signals connect to CRD5376 through 3-pin headers on the left side of the PCB. For each channel
(CH1, CH2, CH3, CH4), these headers make connections to the differential INA amplifier inputs and to
either a GND or GUARD signal for connection to the sensor cable shields, if present.
Signal Input Pin Header
CH1 INA J16
CH2 INA J1
CH3 INA J2
CH4 INA J7
Table 4. Pin Header Input Connections
2.2.1.2 GUARD Output, GND Connection
The CS3302A hydrophone amplifier provides a GUARD signal output designed to actively drive the cable
shield of a high impedance sensor with the common mode voltage of the sensor differential signal. This
GUARD output on the cable shield minimizes leakage by minimizing the voltage differential between the
sensor signal and the cable shield.
By default, the GUARD signal is output to pin 3 of the input signal headers on the left side of the PCB for
channels 3 and 4, which use the CS3302A amplifier. There is no GUARD signal output for channels 1 and
2 since they use the CS3301A amplifier, so the GUARD pins for these channels are connected to GND
through 0 Ω jumpers.
2.2.1.3 Internal Inputs - DAC_OUT, DAC_BUF
The CS4373A test DAC has two high performance differential test outputs, a precision output (DAC_OUT)
and a buffered output (DAC_BUF). The DAC_OUT signal is wired directly to the INB inputs of the
CS3301A/02A amplifiers for testing the performance of the electronics channel. The DAC_BUF signal is
wired to the INA inputs of the amplifiers through differential analog switches and is used to test the performance of the measurement channel with a sensor attached.
2.2.1.4 Input Protection
Sensor inputs must have circuitry to protect the analog electronics from voltage spikes. Geophone coils
are susceptible to magnetic fields (especially from lightning) and hydrophones can produce large voltage
spikes if located near an air gun source.
12 DS612RD2
CRD5376
Discrete switching diodes quickly clamp the analog inputs to the power supply rails when the input voltage
spikes. These diodes are reverse biased in normal operation and have low reverse bias leakage and capacitance characteristics to maintain high linearity on the analog inputs.
Specification Value
Dual Series Switching Diode - ON Semiconductor BAV99LT1
Surface Mount Package Type SOT-23
Non-Repetitive Peak Forward Current (1 µs, 1 ms, 1 s)
Reverse Bias Leakage (25 C to 85 C)
Reverse Bias Capacitance (0 V to 5 V) 1.5 pF - 0.54 pF
Once a voltage spike is shunted to the power supply rail, a discharge path to ground must be present or
the power supply will itself spike. Transient voltage suppressors clamp the ±2.5 V analog supply rails in
the event of a voltage spike.
Specification Value
Dual Surface Mount TVS - Diodes Inc. MMBZ5V6AL-7
Surface Mount Package Type SOT-23
Working Voltage, Leakage Current
Breakdown Voltage, Threshold Current 5.6 V, 20 mA
Clamp Voltage, Peak Current 8.0 V, 3.0 A
2.0 A, 1.0 A, 500 mA
0.004 µA - 0.4 µA
3.0 V, 5 µA
2.2.1.5 Input RC Filters
Following the diode clamps is an RC filter network that bandwidth limits the sensor inputs into the amplifiers to 'chop-the-tops-off' residual voltage spikes not clamped by the discrete diodes. In addition, all Cirrus Logic component ICs have built in ESD protection diodes guaranteed to 2000 V HBM / 200 V MM
(JEDEC standard). The small physical size of these ESD diodes restricts their current capacity to 10 mA.
For land applications using the CS3301A amplifier (CRD5376 channels 1 and 2), the INA input has a common-mode and differential-mode RC filter. The common-mode filter sets a low-pass corner to shunt very
high frequency components to ground with minimal noise contribution. The differential-mode filter sets a
low-pass corner high enough not to affect the magnitude response of the measurement bandwidth.
For marine applications that use the CS3302A amplifier (CRD5376 channels 3 and 4), the inherent capacitance of the piezoelectric sensor is connected to the INA sensor inputs and combined with large differential-mode resistors (412 kΩ + 2 kΩ) to create an analog high-pass RC filter. Assuming a hydrophone
group capacitance of 128 nF, the high-pass RC filter cut-off frequency is 3 Hz and eliminates the low-frequency components of ocean noise. In addition to high-pass filtering, the 2 kΩ resistor serves as a current-
limiting resistor to protect the amplifier inputs against transient voltage spikes.
DS612RD2 13
Land Common Mode Filter Specification Value
Common Mode Capacitance 10 nF + 10%
Common Mode Resistance
200 Ω
Common Mode -3 dB Corner @ 6 dB/octave 80 kHz + 10%
Land Differential Filter Specification Value
Differential Capacitance 10 nF + 10%
Differential Resistance
200 Ω + 200 Ω = 400 Ω
Differential -3 dB Corner @ 6 dB/octave 40 kHz + 10%
Marine Differential Filter Specification Value
Hydrophone Group Capacitance 128 nF + 10%
Differential Resistance
-3 dB Corner @ 6 dB/octave 3 Hz + 10%
412 kΩ + 2 kΩ = 414 kΩ
CRD5376
2.2.1.6 Common Mode Bias
Differential analog signals into the CS3301A/02A amplifiers need to be biased to the center of the power
supply voltage range, which for bipolar supplies is near ground potential. Resistors to create the common
mode bias are selected based on the sensor impedance and may need to be modified from the CRD5376
defaults depending on the sensor to be used. Refer to the recommended operating bias conditions for the
selected sensor, which are available from the sensor manufacturer.
Specification Value
Geophone Sensor Bias Resistance
Hydrophone Sensor Bias Resistance
20 kΩ || 20 kΩ = 10 kΩ
18 MΩ || 18 MΩ = 9 MΩ
2.2.1.7 Analog Test Switches
Analog switches on CRD5376 connect the DAC_BUF test signal to the sensor. A two stage approach permits flexibility in switch operation while maximizing performance. First, control signals from the digital filter
act as inputs to a 3-to-8 demultiplexer, selecting one of the eight outputs from the decoded GPIO input.
Next, the demultiplexer creates level shifted control signals for the analog switches using the selected output and a pull-up / pull-down circuit on the analog power supplies. These level shifted signals control the
analog switches to connect the test DAC buffered output (DAC_BUF) to the amplifier sensor input (INA).
14 DS612RD2
CRD5376
Using this level-shifting 3-to-8 demultiplexer scheme allows flexible control of the analog switches without
directly coupling them to the digital power supplies. With eight possible decoded outputs from three GPIO
pins, multiple combinations of on / off analog switch arrangements are possible.
SW[2..0] DAC_BUF to INA Connection
000 Channel 1 Only
001 Channel 2 Only
010 Channel 3 Only
011 Channel 4 Only
100 Even Channels Connected
101 Odd Channels Connected
110 All Channels Connected
111 All Channels Disconnected
Table 5. Analog Switch Settings
Independent dual analog switches for each differential channel help to eliminate crosstalk between them.
Specification Value
Analog Switch Mux - Texas Instruments CD74HC4051PWR
Surface Mount Package Type TSSOP-16
Power Supply Voltage, Current
3.3V, 160 µA
+
Individual Switch Settings - Ch1, Ch2, Ch3, Ch4 000, 001, 010, 011
Even, Odd Switch Settings - Ch2+Ch4, Ch1+Ch3 100, 101
All On Switch Setting - Ch1+Ch2+Ch3+Ch4 110
All Off Switch Setting 111
Specification Value
Analog Switch Selection - TI LittleLogic Dual-OR SN74LVC2G32DCTR
Surface Mount Package Type SSOP-8
Supply Voltage, Current
2.5 V, 10 µA
+
Specification Value
Dual SPST Analog Switches - Vishay DG2003DS
Surface Mount Package Type SOT23-8
On Resistance Match, + 5 V Supply
On Resistance Flatness, + 5 V Supply
1.6 Ω
0.2 Ω
Off Leakage Current + 1 nA
Off Isolation @ 1 MHz -61 dB
Channel Crosstalk @ 1 MHz -67 dB
Supply Voltage, Power Consumption
2.5 V, 5.5 µW
+
DS612RD2 15
CRD5376
2.2.2 Differential Amplifiers
The CS3301A/02A amplifiers act as a low-noise gain stage for internal or external differential analog signals.
Analog Signals Description
INA Sensor analog input
INB Test DAC analog input
OUTR, OUTF Analog rough / fine outputs
GUARD CS3302A guard output (jumper selection)
Digital Signals Description
MUX[0..1] Input mux selection
GAIN[0..2] Gain range selection
PWDN Power down mode enable
CLK CS3301A clock input (jumper selection)
2.2.2.1 MCLK/2 Input vs. GUARD Output
By default, channels 1 and 2 of CRD5376 use the CS3301A geophone amplifier while channels 3 and 4
use the CS3302A hydrophone amplifier. The CS3301A amplifier is chopper stabilized and connects pin
13 to a clock source (MCLK/2) to run the chopper circuitry synchronous to the modulator analog sampling
clock. The CS3302A device is not chopper stabilized (with 1/f noise typically buried below the low-frequency ocean noise) to achieve very high input impedance. To minimize leakage from high impedance
sensors connected to the CS3302A amplifier, pin 13 produces a GUARD signal output to actively drive a
sensor cable shield with the common mode voltage of the sensor signal.
Comparing the CS3301A and CS3302A amplifiers, the functionality of pin 13 (CLK input vs. GUARD output) is the only external difference. CRD5376 can be converted to use any combination of CS3301A and
CS3302A amplifiers by replacing the amplifier device and properly installing the pin 13 jumpers. Only one
set of pin 13 jumpers should be installed per channel (either CS3301A or CS3302A), and the others removed.
Amplifier CS3301A CS3302A
CH1 U16 R128 + R84 R129
CH2 U2 R86 + R92 R87
CH3 U33 R95 + R132 R94
CH4 U3 R58 + R100 R59
Table 6. Amplifier Pin 13 Jumper Settings
Common amplifier configurations for CRD5376 include 3x or 4x CS3301A amplifiers for land applications,
4x CS3302A amplifiers for marine streamer applications, and 3x CS3301A amplifiers plus 1x CS3302A
amplifier for seabed reservoir monitoring applications. Replacement amplifiers can be requested as samples from the local Cirrus Logic sales representative.
16 DS612RD2
CRD5376
2.2.2.2 Rough-Fine Outputs - OUTR, OUTF
The analog outputs of the CS3301A/02A differential amplifiers are split into rough charge and fine charge
signals for input to the CS5372A ∆Σ modulators.
Analog signal traces out of the CS3301A/02A amplifiers and into the CS5372A modulators are 4-wire
INR+, INF+, INF-, INR- quad groups, and are routed with INF+ and INF- as a traditional differential pair
and INR+ and INR- as guard traces outside the respective INF+ and INF- traces.
2.2.2.3 Anti-alias RC Filters
The CS5372A ∆Σ modulators are 4th order and high frequency input signals can cause instability. Simple
single-pole anti-alias RC filters are required between the CS3301A/02A amplifier outputs and the
CS5372A modulator inputs to bandwidth limit analog signals into the modulator.
For the CRD5376, the CS3301A/02A amplifier outputs are connected to external 680 Ω series resistors,
and a differential anti-alias RC filter is created by connecting 20 nF of high linearity differential capacitance
(2x 10 nF C0G) between each half of the rough and fine signals.
2.2.3 Delta-Sigma Modulators
Each CS5372A dual modulator performs the A/D function for differential analog signals from two
CS3301A/02A amplifiers. The digital outputs are oversampled ∆Σ bit streams.
Analog Signals Description
INR1, INF1 Channel 1 analog rough / fine inputs
INR2, INF2 Channel 2 analog rough / fine inputs
VREF Voltage reference analog inputs
Digital Signals Description
MDATA[1..2] Modulator delta-sigma data outputs
MFLAG[1..2] Modulator over-range flag outputs
MCLK Modulator clock input
MSYNC Modulator synchronization input
PWDN[1..2] Power down mode enable
OFST Internal offset enable (+VD when using CS3301A/02A)
2.2.3.1 Rough-Fine Inputs - INR, INF
The modulator analog inputs are separated into rough and fine signals, each of which has an anti-alias
RC filter to limit the signal bandwidth into the modulator inputs.
2.2.3.2 Offset Enable - OFST
The CS5372A ∆Σ modulator requires differential offset to be enabled to eliminate idle tones for a terminated input. The use of internal offset to eliminate idle tones is described in the CS5372A data sheet. By
default, OFST is enabled for the CS5372A modulators on CRD5376.
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CRD5376
2.2.4 Delta-Sigma Test DAC
The CS4373A test DAC creates differential analog signals for system tests. Multiple test modes are available and their use is described in the CS4373A data sheet.
Analog Signals Description
OUT Precision differential analog output
BUF Buffered differential analog output
CAP Capacitor connection for internal anti-alias filter
VREF Voltage reference analog inputs
Digital Signals Description
TDATA Delta-sigma test data input
MCLK Clock input
SYNC Synchronization input
MODE[0..2] Test mode selection
ATT[0..2] Attenuation range selection
2.2.4.1 Precision Output - DAC_OUT
The CS4373A test DAC has a precision output (DAC_OUT) that is routed to the amplifier INB inputs of all
channels. The input impedance of the CS3301A/02A INB amplifier inputs are high enough that the precision output can be directly connected to the INB inputs of all channels simultaneously.
2.2.4.2 Buffered Output - DAC_BUF
The CS4373A test DAC has a buffered output (DAC_BUF) that is routed through differential analog
switches to the amplifier INA inputs for each channel. This output is less sensitive to loading than the precision outputs, and can drive a sensor attached to the amplifier INA inputs provided the sensor meets the
impedance requirements specified in the CS4373A data sheet.
2.2.5 Voltage Reference
A voltage reference on CRD5376 creates a precision voltage from the regulated analog supplies for the
modulator and test DAC VREF inputs. Because the voltage reference output is generated relative to the
negative analog power supply, VREF+ is near GND potential for bipolar power supplies.
Specification Value
Precision Reference - Linear Tech LT1019AIS8-2.5
Surface Mount Package Type SO-8
Output Voltage Tolerance +/- 0.05%
Temperature Drift 10 ppm / degC
Quiescent Current 0.65 mA
Output Voltage Noise, 10 Hz - 1 kHz 4 ppm
Ripple Rejection, 10 Hz - 200 Hz > 100 dB
RMS
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2.2.5.1 VREF_MOD12, VREF_MOD34, VREF_DAC
The voltage reference output is provided to the CS5372A ∆Σ modulators and the CS4373A test DAC
through separate low pass RC filters. By separately filtering the voltage reference for each device, signal
dependent sampling of VREF by one device is isolated from other devices. Each voltage reference signal
is routed as a separate differential pair from the large RC filter capacitor to control the sensitive VREF
source-return currents and keep them out of the ground plane. In addition to the RC filter function, the
100 uF filter capacitor provides a large charge-well to help settle voltage reference sampling transients.
2.3 Digital Hardware
2.3.1 Digital Filter
The CS5376A quad digital filter performs filtering and decimation of four delta-sigma bit streams from the
CS5372A modulators. It also creates a delta-sigma bit stream output to create analog test signals in the
CS4373A test DAC.
The CS5376A requires several control signal inputs from the external system.
Control Signals Description
RESETz Reset input, active low
BOOT Microcontroller / EEPROM boot mode select
TIMEB Time Break input, rising edge triggered
CLK Master clock input, 32.768 MHz
SYNC Master synchronization input, rising edge triggered
Configuration is completed through the SPI 1 port.
SPI1 Signals Description
SSIz Serial chip select input, active low
SCK1 Serial clock input
MISO Master in / slave out serial data
MOSI Master out / slave in serial data
SINTz Serial acknowledge output, active low
SSOz Serial chip select output (unused on CRD5376)
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Data is collected through the SD port.
SD Port Signals Description
SDTKI Token input to initiate an SD port transaction
SDRDYz Data ready acknowledge, active low
SDCLK Serial clock input
SDDAT Serial data output
SDTKO Token output (unused on CRD5376)
Modulator ∆Σ data is input through the modulator interface.
Modulator Signals Description
MCLK Modulator clock output
MCLK/2 Modulator clock output, half-speed
MSYNC Modulator synchronization output
MDATA[1..4] Modulator delta-sigma data inputs
MFLAG[1..4] Modulator over-range flag inputs
CRD5376
Test DAC ∆Σ data is generated by the test bit stream generator.
Test Bit Stream Signals Description
TBSDATA Test DAC delta-sigma data output
TBSCLK Test DAC clock output (unused on CRD5376)
Amplifier, modulator, test DAC and analog switch digital pins are controlled by the GPIO port.
GPIO Signals Description
GPIO[0..1]:MUX[0..1] Amplifier input mux selection
GPIO[2..4]:GAIN[0..2] Amplifier gain / test DAC attenuation
GPIO[5..7]:MODE[0..2] Test DAC mode selection
GPIO[8]:PWDN Amplifier / modulator power down
GPIO[9..11]:SW[0..2] Analog switch control
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The secondary serial port (SPI 2) and boundary scan JTAG port are unused on CRD5376.
SPI2 Signals Description
SCK2 Serial clock output (unused on CRD5376)
SO Serial data output (unused on CRD5376)
SI[1..4] Serial data inputs (unused on CRD5376)
JTAG Signals Description
TRSTz JTAG reset (unused on CRD5376)
TMS JTAG test mode select (unused on CRD5376)
TCK JTAG test clock input (unused on CRD5376)
TDI JTAG test data input (unused on CRD5376)
TDO JTAG test data output (unused on CRD5376)
2.3.1.1 MCLK vs. MCLK/2 Usage
The CS5376A digital filter creates the analog sampling clock used by the CS5372A ∆Σ modulators and
CS4373A test DAC. MCLK has strict jitter requirements to guarantee the accuracy of analog-to-digital and
digital-to-analog conversion, and so is carefully routed between the digital filter and modulators / test
DAC.
The CS3301A amplifier also requires an analog sampling clock to run the internal chopper stabilization
circuitry, but without the strict jitter or speed requirement as needed by the CS5372A ∆Σ modulators.
Therefore, the CS3301A amplifier can run equally well from the full-speed MCLK or half-speed MCLK/2.
Although MCLK could be used as the amplifier input clock, using MCLK/2 isolates the sensitive
modulator / test DAC analog sampling clock from the amplifier clock.
2.3.1.2 Configuration - SPI 1 Port
Configuration of the CS5376A digital filter is through the SPI 1 port by the on-board 8051 microcontroller
which receives commands from the PC evaluation software via the USB interface. Evaluation software
commands can write/read digital filter registers, specify digital filter coefficients and test bit stream data,
and start/stop digital filter operation.
How the digital filter receives configuration information, either from a microcontroller or configuration EEPROM, is selected by the BOOT signal. The BOOT signal is tied low on CRD5376 for microcontroller
configuration.
2.3.1.3 Digital Control Signals
The reset, synchronization and timebreak signals to the CS5376A digital filter are generated by the onboard microcontroller and applied to the CS5376A digital filter RESET, SYNC, and TIMEB inputs.
Data collection transactions are initiated by a rising edge on the SDTKI input, as described in the
CS5376A data sheet. Two options for providing the required SDTKI rising edge are available on
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