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I
MPORTANT NOTICE
“Preliminary” product information describes products that are in production, but for which full characterization data is not yet available.
Cirrus Logic, Inc. and its subsi di ar i es (“Cirrus”) believe that th e i nformation contained in this document is accurate and reliable. However, the information
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CERTAIN APPLICATIONS USING SEMICOND UCTOR PRODUCTS MA Y INVOLVE POTENTIAL RISK S OF DEATH, PERSONAL INJURY, OR S EVERE
PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IM PL ANT ED INTO THE BODY, AUTOMOTIVE SAFETY OR S ECURIT Y DEVICES, LIFE SUPPORT
PRODUCTS OR OTHER CRITICAL APPLICATIONS . INCLUSION OF CIRRUS PRODU CTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY
AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS
USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOME R AGREES , BY SUC H USE, TO F ULLY INDEMNIF Y CIRRUS, IT S OFFICERS, DIRECTORS, EMPLOYEE S, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND AL L LIABILITY, INCLUDING AT TORNEYS' FEES AND COSTS, THAT MA Y RESULT FROM O R ARISE
IN CONNECTION WITH THESE USES.
Cirrus Logic, Cirrus, the Cirrus Logic logo designs,and DSP Composer are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.
Microsoft and Windows XP are registered trademarks of Microsoft Corporation.
SPI is a trademarks of Motorola, Inc.
2
C is a registered trademark of Philips Semiconductor Corp.
I
HDMI is a trademark or registered trademark of HDMI Licensing, LLC in the United States and/or other countries.
Dolby Digital is a registered trademark of Dolby Laboratories Licensing Corporation.
Figure 5-7. MIC Pre-AMP ...........................................................................................................................5-12
Figure 5-8. Connectors and Power ............................................................................................................5-13
•Power Supply: +9V, 1.67A, 100V - 240V with AC Power Cord
•CRD USB Master USB Digital I/O Card
•USB Cable
•Document Card explaining how to get the latest board software
CRD49530-USB Kit Contents
CRD49530-USB User’s Manual
Chapter 1
Kit Contents and Requirements
Figure 1-1. CRD49530 Kit Contents
1.2 Requirements
1.2.1 PC Requirements
• Microsoft Windows® XP Operating System
• USB 2.0 Support
DS705RD3Copyright 2008 Cirrus Logic1-1
CRD49530-USB System Description
g
CRD49530-USB User’s Manual
1.2.2 Software Requirements
• Cirrus Evaluation Software Package (available from your local Cirrus Logic representative)
1.2.3 Support Hardware Requirements
• Digital or Analog Audio Source (e.g. DVD player, PC with a digital audio card/device)
• Amplified Speakers for audio playback (e.g. powered PC speakers, AVR/amp + speakers)
1.2.4 Cabling Requirements
• Digital Audio Inputs – S/PDIF Optical Cables, RCA Audio cables (Connect to digital audio card, audio
analyzer, or DVD player.)
• Digital Audio Output – S/PDIF Optical Cables (Connect to digital audio card, audio analyzer, or AVR.)
• Analog Audio Inputs – RCA Audio Cables (Connect CRD49530 line-level inputs to analog audio source.)
• Analog Audio Outputs – RCA Audio Cables (Connect CRD49530 line-level outputs to powered speakers.)
1.3 CRD49530-USB System Description
A detailed block diagram of the CRD49530-USB Customer Reference Design is shown below in
Figure 1-2. The sections that follow provide a detailed description of each block.
Analog
Analog
Analog
Analog
Analog
In
In
In
Analog
In
In
MIC In
Control Header – J11
6x
In
Preamp
SPI / I2C
HDMI Clocks/Data
HDMI_SPDIF
BRD_RESET
MIC
SPI / I2C
DSP_RESET
ADC Data
Audio Clock s
S/PDIF Data
1
0
CS42448
CS4953xx
XTAL_OUT
CS8416
CS42448_RESET
Memory Bus
SPI Master
SPI FLASH
SDRAM
FLASH
SPDIF OUT
SPDIF IN
Analog
Analog
Analog
8x
Analog
Analog
In
In
In
Analo
In
In
Out
S/PDIF
Out
4x
4x
4x
4x
S/PDIF
S/PDIF
S/PDIF
S/PDIF
In
In
In
In
Figure 1-2. CRD49530-USB Block Diagram
DS705RD3Copyright 2008 Cirrus Logic1-2
CRD49530-USB System Description
CRD49530-USB User’s Manual
1.3.1 Audio Inputs
1.3.1.1 Analog Line-level Inputs
•Connector Type: RCA Female
•Absolute Maximum Signa l Leve l: +6.5V
•Absolute Minimum Signal Level: GND - 0.7V
•Full Scale Amplitude: 2V
•Reference Designators: J12, J26-J30, or AIN1 - AIN6
1.3.1.2 Optical Digital Inputs
•Connector Type: Fiber Optic RX for Digital Audio, JIS F05 (JIS C5974-1993 F05)
•Reference Designators: J1-J2, or SPDIF_RX0-SPDIF_RX1
1.3.1.3 Coaxial Digital Inputs
•Connector Type: RCA Female
•Maximum Signal Level: +3.3V
•Minimum Signal Level: GND - 0.7V
•Reference Designators: J31-J32, or SPDIF_RX2-SPDIF_RX3
RMS
1.3.1.4 Microphone Input
•Absolute Maximum Signa l Level: +5V
•Absolute Minimum Signal Level: GND - 0.7V
•Full Scale Amplitude: 7mVp-p
•Reference Designator: J5
The microphone preamplifier shares the AIN5 ADC with the AIN5 RCA jack. Only one analog source can
be sampled at any given time. When the microphone input is selected, the AIN5 audio jack is ignored. The
default configuration enables the AIN5 audio jack.
1.3.2 Audio Outputs
1.3.2.1 Analog Line-level Outputs
•Connector Type: RCA Female
•Full Scale Amplitude: 1.21V
•Reference Designators: J33-J40, or AOUT1 - AOUT8
1.3.2.2 Optical Digital Output
•Connector Type: Fiber Optic TX for Digital Audio, JIS F05 (JIS C5974-1993 F05)
•Reference Designator: J24, or SPDIF_TX
•The S/PDIF output uses the same data line as AOUT7 and AOUT8. When the digital output has
been enabled, and you have speakers connected to AOUT7 and AOUT8 white noise will be heard.
This could damage the speakers.
RMS
1-3Copyright 2008 Cirrus LogicDS705RD3
1.3.2.3 DC Power Input
•Voltage Range: +9VDCTO +12VDC
•Minimum Power: 8W supply
•Connector Type: 2mm Female, positive center pin
•Reference Designator: J25
1.3.3 Control Header
•Connector Type: 2x25, 0.100 inch Shrouded Male
•Reference Designator: J11
This connector is the interface between the CRD49530 and the CRD USB Master. Control signals, clocks,
data, and +3.3V power are passed across this connector.
1.3.4 On-Board Voltage Selection Headers
•Connector Type: 1x3, 0.100 inch, Stake Header
•Reference Designator: J17 - J19
The CRD49530-USB is designed to operate from a single DC power input. The 9V power supply provided
with the kit is connected to the DC power input jack (J25) and is regulated down to the system voltages
(5V , 3.3V, 1.8V). The power selection headers should be set to the ‘REG’ position when using the DC wall
supply. This is the default mode of operation and should not need to be changed for most applications.
CRD49530-USB System Description
CRD49530-USB User’s Manual
It is possible to bypass the regulated power supplies for any of the voltages by removing the jumper from
the appropriate power selection header, and connecting an external voltage supply to the center pin of
that selection header.
The third configuration for the power selection headers is the ‘EXT’ position. This is a special mode of
operation, and cannot be used while connected to the CRD USB Master control board. Placing the power
selection headers in the ‘EXT’ position while connected to the CRD USB Master will prevent the board
from operating.
The unpopulated header, J3, is also designed for a special mode that brings 12V from the control header,
but cannot be used when connected to the CRD USB Master.
1.3.5 Audio Input Source Multiplexer
•Source 0: CRD USB Master USB Board (This feature is used by engineering development and
debugging purposes.)
•Source 1: CS8416 and CS42448
•Reference Designators: U1, U2
This multiplexer is used to select which audio sources feed the CS4953xx DAI pins. When the on-board
sources (CS8416, U3 and CS42448, U4) are being used, the CRD USB Master data cannot be
processed. Likewise, when the HDMI source (CRD USB Master) is selected, the on-board audio inputs
are disabled.
1.3.6 CS4953xx Audio DSP
The CS4953xx audio DSP (U5) are a family of dual-core processors designed specifically for audio
applications. The CRD49530 allows a designer to evaluate the CS4953xx DSPs in many different modes
of multi-channel input and output. The 144-pin footprint on this board is compatible with any CS4953xx (or
CS497xx) chip that uses the LQFP144 package.
DS705RD3Copyright 2008 Cirrus Logic1-4
CRD49530-USB System Description
CRD49530-USB User’s Manual
Audio input data to the DSP can come from any of the following sources:
•CS8416 (U3)
•CS42448 (U4)
•CRD USB Master (feature not currently supported)
•Audio output data from the DSP can be sent to the following destinations:
•CS42448 for conversion to Analog Output (AOUT1 - AOUT8)
•Optical S/PDIF Out (SPDIF_TX), this option disables AOUT7 and AOUT8
The CS4953xx has many applications stored in internal ROM, but a host is still required to configure the
application for a particular system. The CRD49530 allows the PC to act as a host to boot and configure
the DSP through the GUI software.
The CS4953xx can also be booted from external serial flash for custom applications that are not stored in
the DSP’s ROM.
Note: The 144-pin footprint on this board is also compatible with the CS495xx family of DSPs. The
CRD49530 can support any CS495xx chip if the alternate stuffing options shown on the DSP
schematic page have been followed.
1.3.7 CS8416 S/PDIF RX
The CS8416 (U3) is a 192 kHz S/PDIF receiver with an integrated input multiplexer. All of the S/PDIF
input jacks (RX0-RX3) are connected to the CS8416. The active S/PDIF jack is selected by changing the
internal mux through the serial host port of the CS8416. This selection is controlled through the Audio In
configuration within DSP Composer (see Chapter 4 for details).
When S/PDIF audio is being processed, the CS8416 must master MCLK for the system (see "Audio
Clocking" on page 1-6 for details).
1.3.8 CS42448 Audio Codec
The CS42448 (U4) is a high-performance, multi-channel audio codec capable of supporting sample rates
up to 192 kHz on its 6 ADCs and 8 DACs. This device is used for all analog-to-digital and digital-to-analog
conversions on the CRD49530.
All analog inputs (AIN1-AIN6) and all analog outputs (AOUT1-AOUT8) are connected to the CS42448.
The microphone input shares the AIN5 ADC with the AIN5 RCA jack. When the microphone is in use, the
AIN5 RCA jack is ignored.
When analog audio is being processed, the 24.576 MHz crystal for the CS4953xx must master MCLK for
the system (see "Audio Clocking" on page 1-6 for details).
1.3.9 Memory
The CRD49530 is populated with a 4 Mbit serial flash. There are 2 footprints (U11, U13) on the board for
compatibility with both standard 8-pin serial flash pinouts. The serial control lines are shared by both
footprints. Only one serial flash chip can be populated.
The CS4953xx can use external SDRAM (U7) to implement features such as large multi-channel audio
delays. A 64 Mbit SDRAM (166 MHz) is connected to the 150 MHz memory bus of the CS4953xx.
There is an additional unpopulated footprint for a parallel flash (U6) memory device. This device was
routed on the board as an example of how to route the memory bus when using a parallel flash memory,
1-5Copyright 2008 Cirrus LogicDS705RD3
but Cirrus recommends using serial flash for all systems. Adding a parallel flash makes the routing of the
X
O
SDRAM bus much more complicated.
1.3.10 Audio Clocking
Clocking architecture is one of the most important aspects of an audio system. The input and output clock
domains of the DSP must be synchronous when delivering audio data in an isochronous fashion (constant
bitrate delivery), even if the input/output domains operate at different frequencies (e.g. 48 kHz input/96
kHz output). Systems utilizing I
isochronous delivery.
The requirements are slightly more complicated for systems using “bursty” delivery on the input side of the
DSP, but the CRD49530 is designed to emulate isochronous systems.
The CRD49530 can operate in three different clocking modes. Each of these modes is explained in the
following sections.
1.3.10.1 Clock and Data Flow for ADC Input
2
S delivery of S/PDIF input, ADC input, or other digital audio input use
MUXED_DAI[3:0]
MUXED_LRCLK
MUXED_SCLK
CRD49530-USB System Description
CRD49530-USB User’s Manual
CS8416
S/PDIF Input
MUXED_MCLK
XTAL_OUT
SDOUT
DAIDAO
CS4953xxCS42448
UT
MTA S/PDIF
DSP_SCLK
DSP_LRCLK
DSP_DA0[3:0]
Figure 1-3. ADC Clocking
SDIN
The ADC clocking architecture is used when the ADCs are used as the only audio input (i.e. S/PDIF is
disabled as described in "USB (I2S) Audio Input" on page 4-5), and the audio input source multiplexer
(U1, U2) is used to select on-board audio sources. Figur e 1-3 illustrates this clocking configuration.
XTAL_OUT from the CS4953xx is MCLK for the system, and the codec masters the input clocks
(MUXED_SCLK/MUXED_LRCLK) of the CS4953xx. The system routing of the clocks was simplified by
using the CS8416 to drive MCLK to the system, but the internal clock multiplexer of the CS8416 is forced
to the OMCK setting to pass XTAL_OUT.
DS705RD3Copyright 2008 Cirrus Logic1-6
CRD49530-USB System Description
X
O
CRD49530-USB User’s Manual
The CS4953x x always masters its output clocks (DSP_SCLK/DSP_LRCLK).
Table 1-1. ADC Clocking
Clock NameClock Master SourceClock DriverClock Frequency
MUXED_MCLKCS4953xxCS841624.576 MHz
MUXED_SCLKMUXED_MCLKCS4244864*Input Fs (default)
MUXED_LRCLKMUXED_MCLKCS42448Input Fs
DSP_SCLKMUXED_MCLKCS4953xx64*Output Fs (default)
DSP_LRCLKMUXED_MCLKCS4953xx1*Input Fs (default)
Note: MUXED_MCLK is the clock signal that is driven by the CS8416’s RMCK pin. The CS8416
provides the recovered clock from the S/PDIF input unless it loses signal lock, in which case the
CS8416 passes the DSP clock (XTAL_OUT) that it receives on the OMCK pin.
1.3.10.2 Clock and Data Flow for S/PDIF Input
MUXED_DAI[3:0]
MUXED_LRCLK
MUXED_SCLK
CS8416
S/PDIF Input
PLL
MUXED_MCLK
DSP_DAI4
DAI
XTAL_OUT
SDOUT
DAO
DSP_SCLK
DSP_LRCLK
DSP_DA0[3:0]
SDIN
CS42448
CS4953xx
UT
MTA S/PDIF
Figure 1-4. S/PDIF Clocking
The S/PDIF clocking architecture is used when any S/PDIF RX is used as an audio source, whether S/
PDIF is the only audio input or is used at the same time as ADC audio (i.e. any S/PDIF RX is selected as
described in "USB (I2S) Audio Input" on page 4-5), and the audio input source multiplexer (U1, U2) is
used to select on-board audio sources. Figure 1- 4 illustrates this clocking configuration.
MCLK recovered from the incoming S/PDIF stream must be MCLK for the system, and the codec masters
the input clocks (MUXED_SCLK/MUXED_LRCLK) of the CS4953xx. In this configuration the internal
multiplexer of the CS8416 routes the recovered MCLK to MUXED_MCLK.
1-7Copyright 2008 Cirrus LogicDS705RD3
The CS4953x x always masters its output clocks (DSP_SCLK/DSP_LRCLK).
X
O
Table 1-2. S/PDIF Clocking
Clock NameClock Master SourceClock DriverClock Frequency
MUXED_MCLKCS8416CS8416
MUXED_SCLKMUXED_MCLKCS841664*Input Fs (default)
MUXED_LRCLKMUXED_MCLKCS8416Input Fs
DSP_SCLKMUXED_MCLKCS4953xx64*Output Fs (default)
DSP_LRCLKMUXED_MCLKCS4953xx1*Input Fs (default)
Note: MUXED_MCLK is the clock signal that is driven by the CS8416’s RMCK pin. The CS8416
provides the recovered clock from the S/PDIF input unless it loses signal lock, in which case the
CS8416 passes the DSP clock (XTAL_OUT) that it receives on the OMCK pin.
1.3.10.3 Clock and Data Flow for USB Data Delivery
This feature is used by engineering development and debugging purposes.
CRD49530-USB System Description
CRD49530-USB User’s Manual
256*S/PDIF Fs
(e.g. 12.288 MHz for 48 kHz)
MUXED_DAI[4:0]
MUXED_LRCLK
MUXED_SCLK
HDMI
SOURCE
MUXED_MCLK
DSP_SCLK
DAIDAO
CS4953xxCS42448
UT
MTA S/PDIF
DSP_LRCLK
DSP_DA0[3:0]
Figure 1-5. HDMI Clocking
SDIN
When the audio input source multiplexer (U1, U2) is used to select HDMI clocks and data, the HDMI
source masters the system MCLK, and the input clocks (MUXED_SCLK/MUXED_LRCLK) of the
CS4953xx.
DS705RD3Copyright 2008 Cirrus Logic1-8
Other Useful Information
CRD49530-USB User’s Manual
The CS4953x x always masters its output clocks (DSP_SCLK/DSP_LRCLK).
Table 1-3. HDMI Clocking
Clock NameClock Master SourceClock DriverClock Frequency
The following informat ion is located on the www.cirrus.com web site.
•CS8416 Data Sheet
•CS8416 Errata
1-9Copyright 2008 Cirrus LogicDS705RD3
1.5.5 DSP Software Utili t y Information
•DSP Composer User’s Manual
The documents listed above are updated periodically and may be more up-to-date than the information in
this document. Check the Cirrus Logic web site for the latest updates.
§§
Information Shipped with the Evaluation Kit
CRD49530-USB User’s Manual
1
1. The “§§” symbol is used throughout this manual to indicate the end of the text flow in a chapter.
DS705RD3Copyright 2008 Cirrus Logic1-10
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