Cirrus Logic CL-CR3710-33QC-A Datasheet

PRELIMINARY DRAFT

Integrated AVI/ATAPI DVD

Drive Manager Datasheet

• Integrates all required components for a complete AVI or ATAPI interface DVD drive (front-end) electronics solution:

-RF amp

- Data channel

- Servo control processor

- DVD ECC (error correction code)

- CSS (content scramble system)

- ATAPI decoder

• Reads DVD+RW, DVD-ROM, DVD-RW, CDDA, CDROM, CD-R, CD-RW, VCD, and DVCD discs

• Direct Audio/Video interface for DVD player applications

• ATAPI interface for game console and DVD loader solutions

• High-performance controller supports DVD disc speeds up to 8x and CD-ROM disc speeds up to 40x

• Partial Response Maximum Likelihood (PRML) data channel

• Servo Control Processor (SCP) on-chip

• DVD navigation support

• 208-pin LQFP/EPAD packages

RF Amp

• Provides laser power control

• Gain control in digital domain

• Generates focus error and tracking signal

• Provides RF signal for the data channel

• Bypass for external RF amp applications

CL-CR3710

OverviewFeatures

The CL-CR3710 is Cirrus Logic’s high-integration, highperformance ATAPI DVD drive manager. It integrates all required components for a DVD loader for DVD players, game consoles, and DVD-ROM drives. The CL-CR3710 includes an RF amp, servo control processor, data channel, DVD ECC, CSS authorization, CD-ROM decoder, and ATAPI interface.

The CL-CR3710 can be configured with an audio DAC (digital-to-analog converter), external buffer memory (8- or 16-bit DRAM), a local micro-controller with its RAM and ROM, and power drivers to create a complete DVD-ROM electronics solution.

The CL-CR3710 supports DVD disc speeds up to 8x and Ultra DMA host speeds up to 33.3 Mbytes/sec.

The RF signal is over-sampled by a high-speed ADC (analog-to-digital converter). The timing loop is closed in the digital domain with variable decimation and interpolation used to provide the output samples to the data recovery logic. A channel-quality logic circuit is provided to allow parametric calibration.

The CL-CR3710 data channel supports partial response maximum likelihood (PRML) data acquisition, providing state-of-the-art data recognition in a noisy environment, coming from the pick-up head.

Block Diagram

TO PO WE R

DRIVERS

FROM

IV AMP

SAMPLE

RATE GEN

VGA

SUM &

VGA

SUB-Q READ

ADCS

LOW PASS

FILTER

SYNTHE SIZER

8/16

DEMOD

EFM

DEMOD

SCP

DACS

ADC

C1/C2 ECC &

DE-INTER LEAVE

SPINDLE

CONTROL

CHANNE L

QUALI TY

DPLL &

DATA CHNL

SUBCODE

DE-INTER LEAVE

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RAM

BAC

CAPTURE

LAYERED ECC

& DVD ECC

HEADER

SEARCH &

CHECKS

MICRO

INTERFACE

BUFFER

MANAGER

CSS

AUTHENTIFICATION

CSS

DESCRAMBLE

HOST

INTERFACE

NAVIGATION

CL-CR3710

www.cirrus.com

FROM SENSORS

LOCAL

MICR OCONTRO LLER

ATAP I O R MPEG

BUFFER

MEMORY

Features (Cont.)

PRELIMINARY DRAFT

Data Channel

• Digital PLL provides flexible control of center frequency to support improved access times

• Channel quality provided for parametric calibration

• Channel data rates up to 210 Mbits/sec.

• Flexible and error-tolerant channel sync mark windowing

SCP (Servo Control Processor)

• Includes a servo control processor for focus, tracking, sled, and spindle servo loops

• Significantly faster capture for focus and tracking

• Effective in a wide range of parameter variations

• Superior response to defects, shock, and vibration

• Supports both CLV (constant linear velocity) and CAV (constant angular velocity) modes

ECC

• Real-time DVD ECC error correction

• Real-time CD-ROM layered ECC error correction with programmable number of sets of P-word and Q-word corrections per sector (up to 64 total)

• C1/C2 ECC and de-interleaving

• Real-time subcode error correction in CD-DA (compact disc digital audio) mode

Decoder

• Supports hardware streaming operation

• DVD navigation support

• Supports ADB (audio data buffering)

• Automatic target sector header search

• Hardware sector header validity check

• Supports high-speed Intel microcontrollers

• Supports nonmultiplexed and multiplexed address and data buses



- and Motorola-type

Host Interface

• True real-time hardware/software ATAPI compatibility

• Supports Ultra DMA: capable of synchronous DMA data rates up to 33.3 Mbytes/sec.

• Supports ATA PIO modes 3 and 4 transfers without IOCHRDY

Host Interface (cont.)

• Supports DMA modes 1 and 2

• Hardware implementation of:

- ATAPI packet command

- ATAPI reset command

High-Performance

• PIO/DMA ATAPI bus transfer rate:

- PIO modes 3 and 4, multiword DMA modes 1 and 2, and singleword DMA modes 1 and 2

• Data transfer rate:

- CD-ROM CLV –maximum 32 × data rate with 25% overspeed capture

- CD-ROM CAV – maximum 40× OD data rate

- DVD-ROM CLV – maximum 6× data rate with 33% overspeed capture

- DVD-ROM CAV – maximum 8× OD data rate

- DVD+R CLV – max. 4x read

• Buffer bandwidth:

- 55 Mbytes per second with 16-bit DRAM

Buffer Manager

• Dual-port circular buffer control with access-priority resolver

• Supports streaming operation

• Direct addressing of up to 4 Mbytes of DRAM

• Supports variable buffer segmentation

• Programmable timing control for SDRAM

• Host overrun control

• Supports 16-bit SDRAM

Microcontroller Interface

• Supports high-speed Intel- and Motorola-type microcontrollers

• Supports nonmultiplexed and multiplexed address and data busses

• Interrupt or polled microcontroller interface

• Microcontroller access to six external switch settings on the buffer bus

- Three-level power-down capability when idle, automatic power-up when command is received

Overview (Cont.)

The CL-CR3710 servo control processor implements the focus, tracking, sled, and spindle servo loops. An ADC is provided to convert the focus and tracking error signal. The outputs to the power drivers are linear DACs.

The CL-CR3710 supports real-time DVD ECC, CD-ROM C1/C2, and layered ECC correction, which is programmable for up to 64 P- and Q-word corrections per sector. It also supports subcode R/W correction in CD-DA (compact disc digital audio) mode.

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The buffer manager controls the flow of data from the data channel, through the ECC, and to either the host interface or the serial audio channel. Data is stored and retrieved in the external buffer memory using interleaved access cycles. The buffer memory is implemented with SDRAM devices. Up to 4 Mbytes of SDRAM can be directly addressed by the CL-CR3710.

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2002 Cirrus Logic Inc.

Features (Cont.)

PRELIMINARY DRAFT

Overview (Cont.)

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System Block Diagrams .........................................................................................................................1

Functional Decriptions............................................................................................................................2

Decoder.....................................................................................................................................2

Data Channel ............................................................................................................................4

Servo Channel...........................................................................................................................6

Register Map..........................................................................................................................................8

Pinout Information ...............................................................................................................................13

Pinout Diagram .......................................................................................................................13

Pin Decriptions ........................................................................................................................14

Package And Order Information...........................................................................................................19

Package Information ...............................................................................................................19

LQFP Ordering Information.....................................................................................................21

Table of Contents

DVD-ROM ...................................................................................................................1

DVD PLAYER ..............................................................................................................1

DVD Mode....................................................................................................................2

CD Form .......................................................................................................................3

Pickup/Sensor Interface ...............................................................................................6

Servo Control Processor ..............................................................................................6

Servo DACs..................................................................................................................6

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iii

System Block Diagrams PRELIMINARY DRAFT

System Block Diagrams

DVD-ROM

BUFFER

MEMORY

CL-CR3710

DATA

CHANNEL

DECODER

SLED/TRACK/FOCUS

DVD PLAYER

SPINDLE

SLED/TRACK/FOCUS

SPINDLE

POWER

DRIVERS

POWER

DRIVERS

CL-CR3710

RF AMP

CONTROL

PROCESSOR

CHANNEL

SERVO

RF AMP

DATA

SERVO

CONTROL

PROCESSOR

BUFFER

MEMORY

DECODER

CSS

ROM MC

DVD/CD-ROM

ECC

DVD/CD-ROM

ROM MC

ATAPI

ECC

SENSOR

AC-3

AUDIO

DECODER

MPEG2

VIDEO

DECODER

BUFFER MEMORY

(2 MBYTES)

USER

CONTROL

6 CHANNEL

AUDIO

NTSC/PAL ENCODER

HOST

INTERFACE

ATAPI

LED

DISPLAY

ROM MC

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Functional Decriptions

This section overviews the main functional blocks of the CL-CR3710 Integrated AVI/ATAPI DVD Drive Manager, and is divided into the following sub-sections:

• "Decoder" on page 2

• "Data Channel" on page 4

• "Servo Channel" on page 6

Decoder

The CL-CR3710 contains a highly automated DVD/CD decoder that takes EFM data from the Analog Front and Digital PRML read channel and transform this data through a series of operations into user data and sends it to the Host controller.

The sequence of operation is as follows:

The high level firmware sets up the decoder through the UP control interface. The decoder is controlled through a register set. The high level FW sets up the mode of operation (CD or DVD), the buffer manager and the host interface. The external SDRAM buffer is controlled through a set of address pointers programmed by the FW. This address pointers controls the data flow from the DISC, to and fro to the ECC Block and the HOST.

Functional Decriptions

DVD Mode

The actual data that is written on the DVD DISC is a transformed version of the user data and follows the DVD Physical Specification.

To understand the decoder flow the transformation process needs to be understood, which is beyond the scope of this document. In summary the user data is organized in sectors (2048 bytes). The transformation process involves adding ID (Sector #) and other information such as copy protection etc. to the data, Scrambling the data, ECC encoding, splitting the data into recording frames , EFM modulation and creation of EFMP frames with unique sync patterns inserted for EFMP frame identification.

The function of the decoder is to take this transformed data and convert back into the user format.

Once the FW sets the start transfer control bit(s) in the decoder, the Decoder starts processing the data from the Read Channel. The data is in the EFMP format (Eight to Fourteen Modulation Plus) as defined in the DVD Physical Specification. The first step is to synchronize and align the data on the EFMP frame boundaries by detecting unique sync patterns that are embedded in the EFMP data stream. Once the data is aligned on the EFMP frame boundary it is de-serialized into 16-bit symbols, and than demodulated into 8 bits of data according to the EFMP modulation standard.

The next step is to determine the right starting point to start the transfer of data into the buffer. The FW will program the Target Header or ID information. Once the incoming data ID matches the programmed ID, data transfer to the Buffer starts. The data transfer

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Functional Decriptions PRELIMINARY DRAFT

always start on an ECC boundary. The HW monitors the subsequent ID to detect any interruption in the DVD data stream.

After sufficient data is stored (at least 1 ECC Block = 16 sectors) in the Buffer, the Error Correction (ECC) system can start the Error Detection and Correction. The Error Correction algorithm is programmable to allow for multi-pass correction, depending upon the application e.g. in the DVD-ROM case, one would program it with more passes than for DVD-Movie case.

Once ECC system has corrected one ECC block, this data can be transferred to the host. However before transferring this data need to be de-scrambled. The de-scrambling process is done during Host transfer to save Buffer BW.

All the Disc Transfer, ECC correction, Descrambling and Host Transfers are done in parallel without any intervention from the micro-controller. The hardware keeps track of how many sectors are transferred from the disc to the buffer, how many sectors have been corrected and how many transferred to the host. This is a fully automated operation also known as "full streaming".

CD Form

The actual data that is written on the CD DISC is a transformed version of the user data and follows the CD Physical Specification. The Physical format of a CD disc is defined by the CD-Digital Audio Physical Specification. All CD whether CD-ROM or CD-Audio follows this standard. The recordable formats also follow this format, except for the linking area for multi-session recordings.

Again it is beyond the scope of this document to describe the CD formats as unlike the DVD format, there are host of different formats that the decoder needs to process. These are CD-DA, CD-ROM Mode 0, CD-ROM Mode 2/Form1 CD-ROM Mode 2/ Form 2 plus CD-Recordable data. In addition for the CD-DA mode the decoder needs to process the Sub Channel Data. The Sub-Channel contains additional information that is embedded in the EFM data stream, which contains sector identifications and other information unique to the data.

Basically there are two types of data, CD-Audio and CD-ROM (with different modes and form). For CD-Audio both the main channel and the Sub Channel Data needs to be processed, for the CD-ROM case only the main channel data is processed.

The data arriving from the Read Channel is in the EFM format, first it is synchronized and aligned on the EFM frame boundaries. After synchronization the data is demodulated using the EFM demodulation table.

CD data is protected through 2 levels of correction C1 and C2 for the CD-DA and 3 levels C1, C2 and C3 for CD-ROM formats.

C1 and C2 correction is done on the fly, i.e. before the data is transferred to the Buffer. After EFM demodulation, the data is sent to CIRC block (Cross Interleaved Reed Solomon Code) which performs C1 and C2 correction on the incoming data. It also marks data it cannot correct, these markers called C2 Pointers are used by the Audio Interpolator block to perform audio interpolation and in the case of CD-ROM data, help the C3 correction engine in identifying the errors quickly.

After the EFM demodulation, the Target Header Search looks for the target sector ID in the data stream. In the case of CD-DA this ID is in the sub channel data stream,

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PRELIMINARY DRAFT

whereas in the case of CD-ROM data it is embedded in the main channel data. Once the Target Header is found the data transfer to the Buffer starts and the de-scrambling is done while storing the data in the buffer from the disc. This data is than transferred to the Host (ATAPI or Audio DAC interface)

In the case of CD-ROM data, depending on the format additional C3 correction needs to be performed. This flow is similar to the DVD case, i.e. when sufficient sectors are available in the buffer, the ECC engine starts correcting the data and the Host transfer starts as soon as sufficient sectors are available after C3 correction.

Data Channel

The CL-CR3710 contains a partial response maximum likelihood (PRML) read channel. The channel takes the analog signals from the optical pickup's (OPU) photo detector outputs, detects the EFM or EFM+ data, and sends the data to the decoder. Figure 1 illustrates the Data Channel architecture.

OFFSET

CONTROL

Functional Decriptions

PD A

PD B

PD C PD D

ATTENUATOR

AND

SUMMATION

OFFSET

CONTROL

VGA

DAC

LPF

DAC

Figure 1. Data Channel Diagram

RF ADC

OFFSET

CONTROL

GAIN

CONTROL

SEQUENCE

DETECT OR

DIGIT AL

EQUALIZER

ENVELOPE

DETECT

DEFECT

DETECT

RF TRACK

CROSSING

CHANNEL

QUALI TY

ITR

TO DECODER

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