Cirrus Logic CDB8422 User Manual
Evaluation Board for CS8422
CS8406
CS8422
RX Input
TX Output
Canned
Oscillator
Crystal
Oscillator
Jumper
ILRCK
ISCLK
SDIN
Mux
XTI
FPGA
OLRCK2
OSCLK2
SDOUT2
ILRCK
ISCLK
SDIN
OMCK
Header
Header
Resistors
Hardware
Switches
Header
RMCK
USB Micro-
controller
I2C/SPI
OLRCK1
OSCLK1
SDOUT1
TDM_IN
Reset
Canned
Oscillator
Header
Reset
USB
CDB8422
Features
IEC-60958, AES3/EBU, S/PDIF Inputs
– Single-Ended Inputs via Optical and RCA
Input Jacks
– Differential Inputs via XLR Input Jack
S/PDIF Outputs
– Optical and RCA Output Jacks
– CS8406 Digital Audio Transmitter
I/O Stake Headers
– External Control Port Accessibility
– External Serial Audio I/O Accessibility
3.3 V Logic Interface
Powered by Single External Power Supply or
PC USB Port Connection
H/W Control via DIP Switches
FlexGUI S/W Control - Windows
– Pre-Defined & User-Configurable Scripts
®
Compatible
Description
Using the CDB8422 evaluation board is an ideal way to
evaluate the CS8422. Use of the board requires a digital
signal source, an analyzer, and a power supply. A Windows
PC-compatible computer is also required if using
software mode to configure the CDB8422.
S/PDIF and AES3/EBU input connections are made via
RCA phono, optical, or XLR connectors to the CS8422.
S/PDIF output connections are made via RCA phono or
optical connectors from the CS8406 (S/PDIF Tx). System timing can be provided by a S/PDIF or AES3/EBU
input signal, by the CS8422 with supplied master clock,
or by an I/O stake header with a DSP connected.
The provided Windows-based software GUI makes
configuring the CDB8422 easy. The software communicates through the PC’s USB port to configure the board
so that all features of the CS8422 can be evaluated.
The board may also be configured without a PC connection by using hardware switches; however, not all
configurations of the CDB8422 are possible in hardware mode.
ORDERING INFORMATION
CDB8422 Evaluation Board
http://www.cirrus.com
Copyright Cirrus Logic, Inc. 2010
(All Rights Reserved)
MAY '10
DS692DB2
TABLE OF CONTENTS
1. SYSTEM OVERVIEW ............................................................................................................................. 4
1.1 Power ............................................................................................................................................... 4
1.2 Grounding and Power Supply Decoupling ....................................................................................... 4
1.3 FPGA ............................................................................................................................................... 4
1.4 CS8422 ............................................................................................................................................ 4
1.5 CS8406 Digital Audio Transmitter .................................................................................................... 5
1.6 CS8422 XTI Sources ....................................................................................................................... 5
1.7 I/O Stake Headers ........................................................................................................................... 5
1.8 S/PDIF and AES3/EBU Inputs ......................................................................................................... 5
2. SOFTWARE MODE ................................................................................................................................ 6
2.1 Quick Start Guide ............................................................................................................................. 6
2.2 Configuration Options ...................................................................................................................... 7
2.2.1 S/PDIF In to S/PDIF and PCM Out ......................................................................................... 7
2.2.2 AES3/EBU In to S/PDIF and PCM Out ................................................................................... 8
2.2.3 PCM In to S/PDIF and PCM Out .............................................................................................9
2.2.4 TDM In to TDM Out ............................................................................................................... 10
2.3 Software Mode Control .................................................................................................................. 11
2.3.1 CS8422 Main Setup Tab ....................................................................................................... 12
2.3.2 CS8422 Receiver Controls and Status Tab .......................................................................... 13
2.3.3 CS8422 Interrupt Controls and Status Tab ........................................................................... 14
2.3.4 FPGA Controls Tab ............................................................................................................... 15
2.3.5 Register Maps Tab ................................................................................................................ 16
2.4 FPGA Register Quick Reference ................................................................................................... 17
2.5 FPGA Register Descriptions .......................................................................................................... 17
2.5.1 Code Revision ID (Address 01h) - Read Only ....................................................................... 17
2.5.2 MCLK Control (Address 02h) ................................................................................................ 17
2.5.2.1 SAO2 HDR MCLK Source (SAO2_Mclk) ................................................................... 17
2.5.2.2 SAO1 HDR and CS8406 MCLK Source (SAO1_Mclk) .............................................. 17
2.5.2.3 AUX MCLK Source (AUX_Mclk) ................................................................................ 18
2.5.2.4 CS8422 Reset Pin (DUT_RST) ................................................................................. 18
2.5.3 Subclock Control (Address 03h) ............................................................................................ 18
2.5.3.1 TDM Header Subclock Source (TDM_SEL) .............................................................. 18
2.5.3.2 SAI Subclock Source (SAI_MS) ................................................................................ 18
2.5.3.3 SAO2 Subclock Source (SAO2_MS) ......................................................................... 19
2.5.3.4 SAO1 Subclock Source (SAO1_MS) ......................................................................... 19
2.5.4 CS8406 Control 1 (Address 04h) .......................................................................................... 19
2.5.4.1 OMCK/ILRCK Ratio (HWCK) ..................................................................................... 19
2.5.4.2 Validity Bit (VBIT_IN) .................................................................................................19
2.5.4.3 User Data (UBIT_IN) ................................................................................................. 20
2.5.4.4 TCBL (TCBL) ............................................................................................................. 20
2.5.4.5 C BIT (CBIT_INT) ...................................................................................................... 20
2.5.4.6 Interface Format (SFMT) ........................................................................................... 20
2.5.5 CS8406 Control 2 (Address 05h) .......................................................................................... 21
2.5.5.1 CS8406 Reset Pin (8406_RST) ................................................................................. 21
2.5.5.2 AUDIO Bit (AUDIOb) ................................................................................................. 21
3. HARDWARE MODE ............................................................................................................................. 22
3.1 Quick Start Guide ........................................................................................................................... 22
3.2 Configuration Options .................................................................................................................... 23
3.2.1 AES3/EBU In to S/PDIF and PCM Out ................................................................................. 23
3.2.2 TDM In to TDM Out ............................................................................................................... 24
3.3 Hardware Mode Control ................................................................................................................. 25
4. SYSTEM CONNECTIONS ........................................................................................................
CDB8422
........... 28
2 DS692DB2
5. JUMPER SETTINGS ........................................................................................................................... 29
6. LEDS .................................................................................................................................................... 29
7. CDB8422 BLOCK DIAGRAM .............................................................................................................. 30
8. CDB8422 SCHEMATICS ...................................................................................................................... 31
9. CDB8422 LAYOUT ............................................................................................................................... 43
10. REVISION HISTORY .......................................................................................................................... 46
LIST OF FIGURES
Figure 1.Software Mode Quick Start Guide ................................................................................................ 6
Figure 2.S/PDIF In to S/PDIF and PCM Out ............................................................................................... 7
Figure 3.AES3/EBU In to S/PDIF and PCM Out ......................................................................................... 8
Figure 4.PCM In to S/PDIF and PCM Out ................................................................................................... 9
Figure 5.TDM In to TDM Out ..................................................................................................................... 10
Figure 6.CS8422 Main Setup Tab ............................................................................................................. 12
Figure 7.CS8422 Receiver Controls and Status Tab ................................................................................ 13
Figure 8.CS8422 Interrupt Controls and Status Tab ................................................................................. 14
Figure 9.FPGA Controls Tab ..................................................................................................................... 15
Figure 10.Register Maps Tab - CS8422 ................................................................................................... 16
Figure 11.Hardware Mode Quick Start Guide ........................................................................................... 22
Figure 12.AES3/EBU In to S/PDIF and PCM Out ..................................................................................... 23
Figure 13.TDM In to TDM Out ................................................................................................................... 24
Figure 14.Block Diagram ........................................................................................................................... 30
Figure 15.CS8422 & XTI (Schematic Sheet 1) ......................................................................................... 31
Figure 16.RX Inputs (Schematic Sheet 2) ................................................................................................. 32
Figure 17.PCM Input Header (Schematic Sheet 3) ................................................................................... 33
Figure 18.HW Mode Control (Schematic Sheet 4) .................................................................................... 34
Figure 19.FPGA (Schematic Sheet 5) ....................................................................................................... 35
Figure 20.MCLK Routing (Schematic Sheet 6) ......................................................................................... 36
Figure 21.Serial Audio 1 Output Header (Schematic Sheet 7) ................................................................. 37
Figure 22.Serial Audio 2 Output Header (Schematic Sheet 8) ................................................................. 38
Figure 23.TDM Header (Schematic Sheet 9) ............................................................................................ 39
Figure 24.CS8406 and Auxiliary TX (Schematic Sheet 10) ...................................................................... 40
Figure 25.USB and MCU (Schematic Sheet 11) ....................................................................................... 41
Figure 26.Power (Schematic Sheet 12) .................................................................................................... 42
Figure 27.Silk Screen ................................................................................................................................ 43
Figure 28.Top-Side Layer ......................................................................................................................... 44
Figure 29.Bottom-Side Layer .................................................................................................................... 45
CDB8422
LIST OF TABLES
Table 1. Switch Settings - AES3/EBU In to S/PDIF and PCM Out ........................................................... 23
Table 2. Switch Settings - TDM In to TDM Out ......................................................................................... 24
Table 3. S3 Settings .................................................................................................................................. 25
Table 4. S4 Settings .................................................................................................................................. 26
Table 5. S7 Settings .................................................................................................................................. 27
Table 6. System Connections ................................................................................................................... 28
Table 7. Jumper Settings .......................................................................................................................... 29
Table 8. LEDs ........................................................................................................................................... 29
DS692DB2 3
1. SYSTEM OVERVIEW
CDB8422
The CDB8422 platform provides S/PDIF and AES3/EBU digital interfaces to the CS8422 and allows for external
DSP and I²C
power supply of +5 V can be used to provide power for the CDB8422. Optionally, the evaluation board may be powered from a USB connection, which also serves as an interface to a PC. The CDB8422 is configured in software
mode using Cirrus Logic’s Windows-compatible FlexGUI software to read/write to device registers. In hardware
mode, the evaluation board is configured using several DIP switches.
This section describes the various components on the CDB8422 and how they are used. The two following sections
(Section 2 and Section 3) provide details on operating the CDB8422 in software and hardware mode, respectively.
Both sections begin with a simplified quick connect guide provided for user convenience which can be used to set
up the board quickly with the CS8422 in its startup default configuration. Next, descriptions are given for several
useful configuration options in which the board can be used. Then, complete configuration details for each mode
are described. Section 4, Section 5, and Section 6 provide a description of all stake headers, connectors, and LEDs
on the board, including the default factory settings for all jumpers. The CDB8422 schematic and layout set is shown
in Figures 15 through 29.
®
or SPITM control port interconnects. On-board voltage regulators are provided so that a single external
1.1 Power
Power and ground is supplied to the evaluation board via binding posts J2 and J3 (respectively) or the USB
connection J37. Jumper J20 allows the user to select the power source (see Section 5 for details). The voltage connected to the binding posts should be +5 V. An on-board voltage regulator provides +3.3 V for the
CS8422’s VA, VL, and V_REG supplies. All voltage inputs are referenced to ground using the black binding
post J3.
1.2 Grounding and Power Supply Decoupling
The CDB8422 demonstrates the optimal power supply and grounding arrangements for the CS8422.
Figure 14 provides an overview of the connections to the CS8422. Figure 27 shows the component place-
ment, Figure 28 shows the top layout, and Figure 29 shows the bottom layout. Power supply decoupling capacitors are located as close as possible to the CS8422. Extensive use of ground plane fill helps reduce
radiated noise.
1.3 FPGA
The FPGA controls digital signal routing between the CS8422, the CS8406, and the I/O stake headers. It
also provides routing control of the system master clock from an on-board canned oscillator, an on-board
crystal oscillator, and the CS8422. The FPGA configures the CDB8422 in hardware mode and routes serial
control signals from the micro controller to the CS8422 in software mode. The Cirrus FlexGUI software provides full control of the FPGA’s routing and configuration options, see Section 2.3, Section 2.4, and Section
2.5 for details. A subset of the FPGA’s options are accessible in hardware mode using DIP switches, see
Section 3.3 for details.
1.4 CS8422
A complete description of the CS8422 can be found in the CS8422 product data sheet.
When the evaluation board is connected to a PC via the USB connector, the CS8422 is placed in software
mode and is configured using the Cirrus FlexGUI. The device configuration registers are accessible via the
“Register Maps” tab of the Cirrus FlexGUI software. This tab provides low-level control of each bit. For easier configuration, additional tabs provide high-level control. Section 2.3 provides configuration details.
4 DS692DB2
When the evaluation board is not connected to a PC, the CS8422 is placed in hardware mode and is configured using DIP switches. Certain switch settings require a board reset to take affect, see Section 3.3 for
more information.
1.5 CS8406 Digital Audio Transmitter
A complete description of the CS8406 transmitter and a discussion of the digital audio interface can be
found in the CS8406 data sheet.
The CS8406 converts the output PCM data stream from the CS8422 into S/PDIF data that is output to the
optical (J28) and RCA (J27) connectors. In software mode, device configuration pins are controlled by using
the “FPGA Controls” tab of the Cirrus FlexGUI software, see Section 2.3 for details.
1.6 CS8422 XTI Sources
The CS8422 XTI clock source is selected by jumper J23. The clock signal may be provided by the socketed
on-board canned oscillator (Y1), socketed on-board parallel resonant crystal (Y2), or input serial header
J22. The oscillator and crystal are mounted in pin sockets, allowing for easy removal and replacement. The
device footprint on the board for Y1 will only accommodate half-can-sized oscillators. Section 5 describes
which jumper position selects each clock source.
1.7 I/O Stake Headers
CDB8422
The evaluation board has been designed to allow interfacing with external systems via several serial port
headers and a control port header (J26). The input serial port header (J22) provides access to the input serial audio port of the CS8422. The output serial port headers provide access to both output serial audio
port 1 (J24) and output serial audio port 2 (J25) of the CS8422. All three serial port headers can be placed
in master or slave mode with respect to the CS8422. The TDM input header (J30) allows TDM data to be
input from another system into the CS8422.
The control port header provides bidirectional access to the I²C or SPI control port signals by simply removing all the shunts from the “PC Control” position. The user may then connect a ribbon cable connector to
the “External Connection” pins for external control of board functions. A single row of “GND” pins is provided
to maintain signal ground integrity. Two unpopulated pull-up resistors are also available should the user
choose to use the CDB8422 logic supply (VL) externally.
1.8 S/PDIF and AES3/EBU Inputs
The CDB8422 allows for both S/PDIF and AES3/EBU input signals to be connected to the CS8422. Four
pairs of optical and RCA connectors are provided to connect single-ended S/PDIF signals to the four receiver ports on the CS8422. A single XLR connector is provided to connect a differential AES3/EBU signal to
either of the two differential receiver ports on the CS8422.
Figure 16 illustrates how the S/PDIF and AES3/EBU inputs are connected and routed. Table 7 details the
associated jumper selections. The CS8422 data sheet specifies the maximum allowed input voltage levels.
Note that, as a result of signal attenuation resulting from PCB parasitics, the input S/PDIF signal amplitude
at the receiver input pins of the CS8422 may be lower than at the input connectors. See the CS8422 data
sheet for the minimum signal amplitude required at the receiver input pins of the CS8422.
DS692DB2 5
CDB8422
Shunt right 2 pins of J20
to receive power from
USB +5 V DC power.
Connect USB to board.
Open Flex GUI software
on PC and load quick
setup script.
*See section 2.2 for
quick setup descriptions.
Provide S/PDIF
input to board via
J1 or J7.
PCM digital audio
input can be provided
to the board via
header J22.
1
7
8
PCM digital audio output can be
received from the board via
headers J24 and J25.
Shunt top 2 pins on J4
if using optical input
J1. Shunt bottom 2
pins on J4 if using
coaxial input J7.
4
Shunt the right 2 pins on all rows.
Connect a ribbon cable to left 2
pins of all rows if external system
connect is required.
5
Shunt the middle
2 pins on J23.
2
Receive S/PDIF
output from board
via J28 or J27.
Shunt the top 2 pins
on J31.
6
AES3/EBU input
can also be
provided to the
board via J19.
9
Shunt the top 2 pins on
J21 and J29.
3
TDM input can be
provided to the board via
header J30.
10
11
12
13
2. SOFTWARE MODE
Connecting a USB port cable from a PC to the USB connector (J37) on the CDB8422 and launching the provided
graphical user interface (Cirrus Logic FlexGUI) software enables one to use the board in software mode. The GUI
for the CDB8422 allows the user to configure the CS8422 and FPGA registers via the on-board I²C or SPI control
bus.
2.1 Quick Start Guide
Figure 1 below is a simplified quick start up guide made for user convenience. The user may choose from
steps 8 through 13 depending on the desired measurement. Refer to Section 2.2 for details on how the var-
ious components on the board interface with each other in different board configurations. Refer to Section
2.3 for descriptions on control settings in the Cirrus FlexGUI software.
Figure 1. Software Mode Quick Start Guide
6 DS692DB2
2.2 Configuration Options
CS8422
CS8406
S/PDIF Tx
Optical
S/PDIF In
(SLAVE)
J1
OR
RX0
Buffer Buffer
Header
J24
Buffer
Header
J25
(MASTER)
(MASTER)
J7
J4
Coaxial
S/PDIF In
OSCL K1
OLRC K1
SDOUT1
OSCL K2
OLRC K2
SDOUT2
ISCLK
ILRCK
SDIN
OSCLK2
OLRCK2
SDOUT2
OSCLK1
OLRCK1
SDOUT1
Optical
S/PDIF
Out
J28
AND
J27
J31
Coaxial
S/PDIF
Out
S/PDIF
OUT
RMCK
OMCK
MCLK OUT
MCLK OUT
PCM Out
through SRC
PCM Out
no SRC
In software mode, to configure the CDB8422 for making performance measurements, one needs to use Cirrus Logic’s Windows compatible FlexGUI software to program the various components on the board. This
section serves to give a deeper understanding of the on-board circuitry and the digital clock and data signal
routing involved in several common software mode configurations of the CDB8422. These scripts only serve
as a starting point; after loading a script, the GUI can be further configured as needed (clock ratios, serial
formats, etc).
2.2.1 S/PDIF In to S/PDIF and PCM Out
The CS8422’s S/PDIF receiver and SRC output performance can be tested by loading the “SPDIF In to
SPDIF and PCM Out” quick setup file provided with the software package. The script configures the dig-
ital clock and data signal routing on the board as shown in Figure 2.
Digital S/PDIF input can be provided on the optical (J1) or RCA (J7) jacks. Jumper J4 selects which input
signal is connected to the RX0 pin of the CS8422. The script configures the CS8422’s internal circuitry to
send the input audio data through its SRC to serial output port 1. This data is presented as PCM audio at
header J24 and S/PDIF audio at J27 (coaxial) and J28 (optical). The input data is also passed through
(SRC is bypassed) to serial output port 2. This data is presented as PCM audio at header J25. Refer to
Section 2.3 for details on software configuration.
CDB8422
Figure 2. S/PDIF In to S/PDIF and PCM Out
DS692DB2 7
2.2.2 AES3/EBU In to S/PDIF and PCM Out
CS8422
CS8406
S/PDIF Tx
(SLAVE)
Buffer Buffer
Header
J24
Buffer
Header
J25
(MASTER)
(MASTER)
OSCLK 1
OLRCK1
SDOUT1
OSCLK 2
OLRCK2
SDOUT2
ISCLK
ILRCK
SDIN
OSCL K2
OLRCK2
SDOUT2
OSCL K1
OLRCK1
SDOUT1
Optical
S/PDIF
Out
J28
AND
J27
J31
Coaxial
S/PDIF
Out
S/PDIF
OUT
RMCK
OMCK
MCLK OUT
MCLK OUT
J19
J21
AES3/EBU
In
J29
RXP0
RXP1
RXN0
RXN1
PCM Out
through SRC
PCM Out
no SRC
The CS8422’s AES3/EBU receiver and SRC output performance can be tested by loading the “AES3 In
to SPDIF and PCM Out” quick setup file provided with the software package. The script configures the
digital clock and data signal routing on the board as shown in Figure 3.
Digital AES3/EBU input is provided by the XLR jack J19 to the RXP0 and RXN0 pins of the CS8422. The
script configures the CS8422’s internal circuitry to send the input audio data through its SRC to serial output port 1. This data is presented as PCM audio at header J24 and S/PDIF audio at J27 (coaxial) and J28
(optical). The input data is also passed through (SRC is bypassed) to serial output port 2. This data is
presented as PCM audio at header J25. Refer to Section 2.3 for details on software configuration.
CDB8422
Figure 3. AES3/EBU In to S/PDIF and PCM Out
8 DS692DB2
2.2.3 PCM In to S/PDIF and PCM Out
CS8406
S/PDIF Tx
(SLAVE)
Buffer Buffer
Header
J24
Buffer
Header
J25
(MASTER)
(MASTER)
OSCLK1
OLRCK1
SDOUT1
OSCLK2
OLRCK2
SDOUT2
ISCLK
ILRCK
SDIN
OSCLK2
OLRCK2
SDOUT2
OSCLK1
OLRCK1
SDOUT1
Optical
S/PDIF
Out
J28
AND
J27
J31
Coaxial
S/PDIF
Out
S/PDIF
OUT
RMCK
OMCK
MCLK OUT
MCLK OUT
CS8422
J23
XTI
Y1
ISCLK
ILRCK
SDIN
Buffer
(SLAVE)
PCM In
MCLK
ISCLK
ILRCK
Header
J22
SDIN
PCM Out
through SRC
PCM Out
no SRC
The CS8422’s serial input port and SRC output performance can be tested by loading the “PCM In to
SPDIF and PCM Out” quick setup file provided with the software package. The script configures the digital clock and data signal routing on the board as shown in Figure 4.
PCM audio input is provided by the PCM input header J22. The jumper position on J23 may be changed
to use the MCLK signal from J22 for the CS8422’s XTI signal. The script configures the CS8422’s internal
circuitry to send the input audio data through its SRC to serial output port 1. This data is presented as
PCM audio at header J24 and S/PDIF audio at J27 (coaxial) and J28 (optical). The input data is also
passed through (SRC is bypassed) to serial output port 2. This data is presented as PCM audio at header
J25. Refer to Section 2.3 for details on software configuration.
CDB8422
Figure 4. PCM In to S/PDIF and PCM Out
DS692DB2 9
2.2.4 TDM In to TDM Out
CS8422
Optical
S/PDIF In
J1
OR
RX0
Buffer
Header
J24
Buffer
Header
J25
(MASTER)
(MASTER)
J7
J4
Coaxial
S/PDIF In
OSCLK1
OLRCK1
SDOUT1
OSCLK2
OLRCK2
SDOUT2
OSCLK2
OLRCK2
SDOUT2
OSCLK1
OLRCK1
SDOUT1
XTI
J23
Y1
Header
J30
TDM
OSCLK
TDM
OLRCK
TDM IN
Buffer
TDM
Out
TDM_IN
TDM
In
PCM Out
no SRC
RMCK
MCLK OUT
MCLK OUT
GPO3
(XTI)
The CS8422’s TDM output performance can be tested by loading the “TDM In to TDM Out” quick setup
file provided with the software package. The script configures the digital clock and data signal routing on
the board as shown in Figure 5.
TDM audio input data is provided by the TDM input header J30. The LRCK and SCLK signals located at
header J30 should be used to clock in the input TDM data. Optionally, digital S/PDIF input can be provided
on the optical (J1) or RCA (J7) jacks. Jumper J4 selects which input signal is connected to the RX0 pin of
the CS8422. The script configures the CS8422’s internal circuitry to multiplex the TDM input and S/PDIF
input data together and send the output data to serial output port 1. This data is presented as TDM audio
at header J24. The S/PDIF input data is also passed through (not multiplexed) to serial output port 2. This
data is presented as PCM audio at header J25. Refer to Section 2.3 for details on software configuration.
CDB8422
Figure 5. TDM In to TDM Out
10 DS692DB2
2.3 Software Mode Control
The CDB8422 may be used with the Microsoft® Windows®-based FlexGUI graphical user interface, allowing software control of the CS8422 and FPGA registers. The latest control software may be downloaded
from www.cirrus.com/msasoftware. Step-by-step instructions for setting up the FlexGUI are provided as follows:
1. Download and install the FlexGUI software as instructed on the Website.
2. Connect the CDB to the host PC using a USB cable (make sure pin 1 and pin 2 of J20 are shunted).
3. Launch the Cirrus FlexGUI. Once the GUI is launched successfully, all registers are set to their default
reset state.
4. Refresh the GUI by clicking on the “Update All Devices” button. The default state of all registers are now
visible.
For standard set-up:
5. Set up the CS8422 in the “CS8422 Main Setup”, “CS8422 Receiver Controls and Status”, and “CS8422
Interrupt Controls and Status” tabs as desired.
6. Set up the FPGA and CS8406 in the “FPGA Controls” tab as desired.
7. Begin evaluating the CS8422.
CDB8422
For quick set-up, the CDB8422 may, alternatively, be configured by loading a predefined sample script file:
8. On the File menu, click "Restore Board Registers..."
9. Browse to Boards\CDB8422\Scripts\.
10. Choose any one of the provided scripts to begin evaluation.
To create personal scripts files:
11. On the File menu, click "Save Board Registers..."
12. Enter any name that sufficiently describes the created setup.
13. Choose the desired location and save the script.
14. To load this script, follow the instructions from step 8 above.
DS692DB2 11
2.3.1 CS8422 Main Setup Tab
Figure 6. CS8422 Main Setup Tab
The “CS8422 Main Setup” tab provides high-level control of the serial port related registers within the
CS8422. A description of each control group is outlined below. See the CS8422 data sheet for complete
register descriptions.
RMCK Control - Configures the CS8422’s RMCK source and behavior.
SAI Control - Configures the serial audio input port of the CS8422.
SAO1 and SAO2 Control - Configures the two serial audio output ports of the CS8422.
SRC Control - Configures the CS8422’s sample rate converter (SRC).
GPO Control - Specifies the signals located on each of the four GPO pins of the CS8422.
TDM Control - Enables TDM Mode on either serial audio output port of the CS8422.
Quick Setup - Loads register settings for preset configurations of the CDB8422, see Section 2.2.
Miscellaneous Controls - Controls the power-down bit of CS8422, resets to return either the CS8422 or
CDB8422 to default setup, and an update button to read all registers and reflect the current values in the
GUI.
CDB8422
12 DS692DB2
2.3.2 CS8422 Receiver Controls and Status Tab
Figure 7. CS8422 Receiver Controls and Status Tab
The “CS8422 Receiver Controls and Status” tab provides high-level control of the CS8422’s S/PDIF receiver register settings. A description of each group is outlined below. See the CS8422 data sheet for
complete register descriptions.
Receiver Input Control - Configures the CS8422’s receiver input pins and mux.
Receiver Data Control - Configures the CS8422’s receiver data processing.
Receiver Error Unmasking - Configures the CS8422’s receiver error unmasking.
Receiver Error - Shows the status for the CS8422’s unmasked receiver errors.
Receiver Channel Status - Shows the status bits for the CS8422’s selected receiver channel.
Receiver Status - Shows CS8422’s receiver errors occurring within last input data block.
Receiver Format Detect Status - Shows the data format detected on the CS8422’s receiver.
Update CS8422 - Reads all registers in the CS8422 and reflects the current values in the GUI.
CDB8422
DS692DB2 13
2.3.3 CS8422 Interrupt Controls and Status Tab
Figure 8. CS8422 Interrupt Controls and Status Tab
The “CS8422 Interrupt Controls and Status” tab provides high-level control of the CS8422’s interrupt pin
register settings. A description of each control group is outlined below. See the CS8422 data sheet for
complete register descriptions.
INT Pin Control - Controls the CS8422’s INT pin polarity and modes.
Interrupt Error Unmasking - Controls the CS8422’s interrupt error unmasking to affect the INT pin.
Interrupt Status - Shows the status of CS8422’s unmasked interrupt errors.
Update CS8422 - Reads all registers in the CS8422 and reflects the current values in the GUI.
CDB8422
14 DS692DB2
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