Cirrus Logic CDB61884 User Manual
CDB61884
Octal T1/E1/J1 Line Interface Evaluation Board
Features
Socketed CS61884 Octal L ine Interface
Unit
Binding post connectors for power and line
interface connections
Components supplied for all operational
modes E1 75Ω, E1 120 Ω andT1/J1 100 Ω
Socketed termination circuitry for easy
testing
ConnectorforIEEE1149.1JTAGBoundary
Scan
LEDIndicatorsforLossof Signal(LOS) and
power
Supports Hardware, Serial, and Parallel
Host Modes
Easy-to-use evaluation software
On-board socketed reference clock
oscillator
Description
The CS61884 evaluation board is used to demostrate
the functions of a CS61884 Octal Line Interface Unit in
either E1 75 Ω, E1 120 Ω, or T1/J1 100 Ω applications.
The evaluation board can be operated in either Hardware Mode or Host Mode . In Hardware Mode, s witches
and bed stake headers are used to control the line configuration and chann el operations f or all eight channels.
In Host Mode (Serial or Parallel), the evaluation software, switches, and bed stake headers are used to
control the line con figuration and operating mode settings for each channel.
In both Hardware and Host modes, the board may be
configured for E1 75 Ω, E1 120 Ω, or T1/ J 1 100 Ω operating modes. In both modes binding post connectors
provide easy connections between the line interface
connections of the CS61884 and any E1/T1 analyzing
equipment, which ma y be used to evaluate the CS61884
device. Bed stake headers a llow easy access to each
channel’s clock and data I/O digital interface.
Eight LED indictors display the Loss of Signal (LOS)
conditions for each channel during Hardware and Host
modes. An LED indictor is used on the Interrupt pin to
indicate a change of state.
Preliminary Product Information
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
ORDERING INFORM ATION
CS61884-IQ -40° to 85° C 144-pin LQFP
CDB61884 Evaluation Board
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product withoutnotice.
CopyrightCirrus Logic, Inc. 2002
(All Rights Reserved)
DS485DB1
MAR ‘02
1
TABLE OF CONTENTS
1. CDB61884 EVALUATION BOARD LAYOUT ..........................................................................4
2. BOARD COMPONENT DESCRIPTIONS .................................................................................5
2.1 Power Connections ............................................................................................................5
2.2 Master Clock Selection ......................................................................................................5
2.3 Operating Mode Selection .................................................................................................6
2.4 Line Interface Connections ................................................................................................6
2.5 TXOE Selection .................................................................................................................6
2.6 Clock Edge Selection .........................................................................................................7
2.7 Jitte r Attenuator Select ion ..................................................................................................7
2.8 Loopback Mode Selection ..................................................................................................7
2.9 Line Lengt h Selec tion ........................................................................................................7
2.10 Line Impedanc e Selection ................................................................................................8
2.11 Coder/Motorola/Intel Selection .........................................................................................8
2.12 G.772 Monitoring Address Selection ...............................................................................8
2.13 Mux/Non-Mux/BITS Clock Selection ................................................................................8
2.14 Digital Signal Connections ...............................................................................................9
2.15 LOS Indicators .................................................................................................................9
2.16 JT AG Connec tion .............................................................................................................9
2.17 Host Interface Connection ...............................................................................................9
3. HOST SETUP DESCRIPTION ..................................................................................................9
4. HOST SOFTWARE INTERFACE .............................................................................................9
4.1 Starting the Software .......................................................................................................10
4.2 Software Interface Buttons ...............................................................................................10
4.2.1 Bit Indicator Description ......................................................................................10
4.3 Set All Button Description ................................................................................................10
4.3.1 Clear All Button Description ................................................................................11
4.3.2 Write All Button Description ................................................................................11
4.3.3 Read All Button Description ................................................................................11
4.4 Write Button Description ..................................................................................................11
4.5 Read Button De scription ..................................................................................................11
4.6 Program Exit Function .....................................................................................................11
CDB61884
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts/sales.cfm
IMPORTANT NOTICE
"Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. "Advance" product infor-
mation describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information containedinthis document isaccurate and reliable. However, theinformation issubject to changewithoutnotice and is provided "AS IS" without warranty
of any kind (express or implied). Customers are advised to obtain the latest version of relevant information toverify, before placing orders, that information being
reliedon is current and complete. All products are sold subject totheterms and conditions of sale suppliedat the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this
information as the basis for manufacture or sale of any items, or for infringement of patents or other rightsof thirdparties. Thisdocumentis the property of Cirrus
and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or
other intellectual property rights. Cirrus owns the copyrights of the informationcontained herein and gives consent for copies to be madeof the information only
for usewithin your organization with respect to Cirrus integrated circuitsor other parts of Cirrus. This consent does not extendto other copying suchas copying
for general distribution, advertising or promotional purposes, or for creating any work for resale.
An export permit needs to be obtained fromthe competent authorities of the Japanese Government if any of the products or technologies described in thismaterial and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. An export license and/or quota needs to be
obtained fromthecompetentauthorities of the Chinese Governmentif any of the products or technologies describedinthis material is subject to the PRC Foreign
Trade Law and is to be exported or taken out of the PRC.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE
PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BESUITABLE FOR USE IN LIFE-SUPPORT DEVICESOR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSIONOFCIRRUSPRODUCTS
IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.
2 DS485DB1
5. CS61884 CONFIGURATION SCREENS ............................................................................... 12
5.1 Choose Parallel Port Settings ..........................................................................................12
5.2 Access and Configure the Read / Write Registers .......................................................... 12
5.2.1 Access Configurati on Screens ............................................................................ 12
5.2.2 Select Register to Configure ...............................................................................12
5.3 Lo opbac k /Bits Clock Screen ........................................................................................... 13
5.4 LOS/AIS/DFM/JA Register Screen .................................................................................. 14
5.5 Transmitter Re gister Screen ............................................................................................ 15
5.6 AWG Re gister Screen ..................................................................................................... 16
5.7 G lobal Control Register Screen . ...................................................................................... 17
6. BOARD CONFIGURATIONS .................................................................................................18
6.1 E1 75 Ω Mode Setup ....................................................................................................... 18
6.2 E1 120 Ω Mode Setup .....................................................................................................19
6.3 T1/J1 100 Ω Mode Setup ................................................................................................20
7. EVALUATION HINTS .............................................................................................................21
LIST OF FIGURES
Figure 1. CDB61884 Board Layout................................................................................................. 4
Figure 2 . On-board Logic Power Selection.....................................................................................5
Figure 3 . Master Clock Selections .................................................................................................. 5
Figure 4 . Hardware/Host Mode Selection....................................................................................... 6
Figure 5 . Transmitter Enable Selection...........................................................................................7
Figure 6 . Clock Edge Selection....................................................................................................... 7
Figure 7 . Jitter Attenuator Selection................................................................................................7
Figure 8 . Loopba ck Mode Selection................................................................................................7
Figure 9 . Switch S9 Settings ........................................................................................................... 8
Figure 1 0. Digital Signal Control/Access.........................................................................................9
Figure 11. CDB61884 Software Opening Sc reen ......................................................................... 10
Figure 1 2. Register Bit Box........................................................................................................... 10
Figure 1 3. Set All Button............................................................................................................... 10
Figure 1 4. Clear All Button ............................................................................................................11
Figure 1 5. Write All Button............................................................................................................11
Figure 1 6. Read All Button............................................................................................................ 11
Figure 1 7. Write Button.................................................................................................................11
Figure 1 8. Read Button................................................................................................................. 11
Figure 1 9. Opening Screen for Port and Address Selection Screen.............................................12
Figure 2 0. Loopb ac k/G.703 B its Clock Selection Screen ............................................................. 13
Figure 2 1. LOS/AIS/DFM/JAERR Status/Enable Selection Screen.............................................14
Figure 2 2. Transmitter Register Screen........................................................................................15
Figure 2 3. AWG Registers Screen................................................................................................16
Figure 2 4. Global Control Screen..................................................................................................17
CDB61884
LIST OF TABLES
Table 1 . External Impedanc e Res istor Values ...................................................................................... 6
Table 2. ProtectionResistor Selection .................................................................................................6
Table 3. Switch Settings for Host Mode ................................................................................................9
Table4.E175Ω Operational Mode Switch/Jumper Position .............................................................18
Table5.E1120Ω Operational Mode Switch/Jumper Position ........................................................... 19
Table 6. T1/J1 100 Ω Operational Mode Switch/Jum per Position....................................................... 20
DS485DB1 3
1. CDB61884 EVALUATION BOARD LAYOUT
CDB61884
Figure 1. CDB61884 Board Layout
4 DS485DB1
2. BOARD COMPONENT DESCRIPTIONS
CDB61884
2.1 Power Connections
Power for the evaluation board is supplied by an
external +3.3 V DC power supply. A +5 V DC
power supply can also be connected to the on-board
control logic. The LED labeled “D3” will illuminate when power is supplied to the on-board control logic.
– Connectthe +3.3VDC power supply tothe+3V
binding post and the +5 VDC power supply to
the +5 V binding post if 5 Volt logic is required
– Jumper J13 shown in Figure 2 allows all the
external logic on the evaluation board to be
connected to either +3 V or +5 V binding post.
J13
3V
VLOGIC
5V
On-board logic connected
to +3 V binding post
2.2 Master Clock Selection
In both hardware and host modes, the MCLK pin is
configured by placing a short block on one of the
positions of bed stake header J1. Figure 3 shows
the different positions of the J1 bed stake header.
HIGH
EXTERNAL SOURCE
OSCILLATOR
GND
J1
Data Recovery Mode
MCLK
HIGH
J1
On-board Oscillator
OSCILLATOR
EXTERNAL SOURCEEXTERNAL SOURCE
GND
MCLK
J13
3V
VLOGIC
5V
On-board logic connected
to +5 V binding post
Figure 2. On-board Logic Power Selection
– To measure the current consumption of only
the CS61884 device,place a shortblock on
Jumper J13 to connect the Vlogic power
supplies to the +5 V binding post. This will
isolate the CS61884 device from all the onboard logic, to allow the current measurement
to be made at the +3 V binding post.
HIGH
J1
External Clock Source
OSCILLATOR
EXTERNAL SOURCE
GND
MCLK
HIGH
J1
Receivers Powered Down
OSCILLATOR
GND
MCLK
Figure 3. Master Clock Selections
– A 2.048 MHz clock oscillator is provided on the
evaluation board for use as the on-board clock
source for a ll E1 modes.
– A 1.544 MHz clock oscillator is also provided
with the e valuation board for use as the onboard clock source for the T1/J1 operation
modes.
– A BNC connector (labeled J16) provides the
connection for an external clock source.
DS485DB1 5
CDB61884
2.3 Operating Mode Selection
The operating mode for the CS61884 can be selected by setting switch S15 to one of the positions
shown in Figure 4.
S15
MODE
Selects Serial
Host Mode
S15
Hardware
Serial Host
Parallel Host
Selects Parallel
Host Mode
Hardware
Serial Host
Parallel Host
Hardware Mode
S15
Hardware
Serial Host
Parallel Host
MODE MODE
Selects
Figure 4. Hardware/Host Mode Selection
2.4 Line Interface Connections
In both hardware and host modes, the receive line
signals (RTIP/RRING) are connected to the binding post labeled RXT 0-7 and RXR 0-7. The line
signals from the binding posts are coupled to the
device throughtwo octal transformers (T1andT9).
The receivers of the device use external resistors to
match the line impedance. These resistors are socketed for ease in changing the line impedance,forinternal or external line impedance matching. During
internal line impedance matching mode, the resistor values are the same (15 Ω) for all modes of operation: E1 75 Ω, E1 120 Ω or T1/J1 100 Ω. During
external line impedance matching mode the receiver resistors need to be change to the values shown
in Table 1.
Table 1. ExternalImpedance ResistorValues
T1/J1 100 Ω E1 75 Ω E1 120 Ω
12.5Ω 9.31Ω 15Ω
The jumpers listed in Table 2 areusedtoplaceor
bypass 1 KΩ protection resistors in series with the
receive line signals (RTIP/RRING). These resistors are used for receiver protection while in external line impedance matching mode and should not
be used during internal line impedance matching
mode. To place the 1 KΩ resistors in series with the
receive line signals, remove the short blocks from
each of the jumpers described in Table 2. To bypass the 1 KΩ resistors, place a short block on each
jumper shown in Table 2.
Table 2. Protection Resistor Selection
Jumper Description
J29 Channel 0 RRING signal
J30 Channel 0 RTIP Sig nal
J37 Channel 1 RTIP Sig nal
J38 Channel 1 RRING Signal
J46 Channel 2 RRING Signal
J47 Channel 2 RTIP Sig nal
J54 Channel 3 RTIP Sig nal
J55 Channel 3 RRING Signal
J65 Channel 4 RRING Signal
J66 Channel 4 RTIP Sig nal
J73 Channel 5 RTIP Sig nal
J74 Channel 5 RRING Signal
J81 Channel 6 RRING Signal
J82 Channel 6 RTIP Sig nal
J89 Channel 7 RTIP Sig nal
J90 Channel 7 RRING Signal
The transmit line signals (TTIP/TRING) from the
device are coupled to the line binding post (TXT 07 and TXR 0-7) through two octal transformers (T1
and T 9). External protection circuitry such as diodes or chokes are recommended for protection.
For further information on line protection refer to
Application Note AN34, “Secondary Line Protection for T1 and E1 Line Cards” (AN34REV1 SEP
'94).
2.5 TXOE Selection
Jumper J23 is used to enable or High-Z all eight
transmitters in both hardware and host mode. A
shorting block on Jumper J23 places all the trans-
6 DS485DB1
CDB61884
mitters in a high impedance state. Removing the
shorting block, enables the transmitters. See
HI
TXOE
LO
J23
Enable all eight
transmitters
eight transmitters
HI
TXOE
LO
J23
Hi-Z all
Figure 5. Transmitter Enable Selection
Figure 5.
2.6 Clock Edge Selection
In clock/data recovery mode, jumper J93 selects
the edge of RCLK and SCLK on which the
RPOS/RDATA, RNEG, and SDO data signals are
valid. When in data recovery mode, jumper J93 selects the output polarity of RPOS/RNEG.The function of J93 applies to both the hardware and host
mode. Figure 6 shows the settings for jumper J93
and the effect in both clock/data recovery and data
recovery only mode.
HI
CKLE
LO
Clock/Data Recovery -
RPOS/RNEG= falling
edge RCLK SDO =
rising edge SCLK
Data Recovery -
RPOS/RNEG
J93
polarity active high
In host mode, switch S10 has no effect on the
CS61884 device and should be set to the open
(middle) position.
S10
HIGH
OPEN
LOW
JASEL JASEL JASEL
Hardwa reMode
-JAplacedin
transmit path
OPEN
S10
HIGH
LOW
Hardwa reMode
- JA Disabled
S10
HIGH
OPEN
LOW
Hardwa reMode
-JAplacedin
receive path
Figure 7. Jitter Attenuator Selection
2.8 Loopback Mode Selection
In hardware mode, the Loopback modes are configured with switches S1 through S8 (0-7). Figure 8
shows the three different settings for all eight loop
back switches.
In host mode, switches S1 through S8 must be set
to the NONE (middle) position to allow host interface control.
S1 - S8 S1 - S8 S1 - S8
LloopnoneRloop
LloopnoneRloop
LloopnoneRloop
HI
CKLE
LO
Figure 6. Clock Edge Selection
2.7 Jitter Attenuator Selection
In hardware mode, switch S10 (JASEL) controls
the position of the jitter attenuator for all eight
channels. The corner frequency and FIFO length
can not be changed in hardware mode. Figure 7
Clock/Data Recovery -
RPOS/RNEG= rising
edge RCLK SDO =
falling edge SCLK
Data Recovery -
RPOS/RNEG
polarity active low
J93
0-7
Hardware Mode -
Selects Remote
Loopback
0-7
Hardware Mode -
Selects no
Loopback
0-7
Hardware Mode -
Selects local
Loopback
Figure 8. Loopback Mode Selection
2.9 Line Length Selection
In hardware mode, the transmit pulse shapes for E1
75 Ω, E1 120 Ω and T1(J1) 100 Ωare selected with
switches S12 through S14 (LEN 2-0). Refer to the
CS61884 Data Sheet for the correct settings.
shows the settings for switch S10.
DS485DB1 7
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