Cirrus Logic CDB61584A User Manual

Socketed CS61584A Dual Line Interface
All Required Components for CS61584A
Evaluation
Locations to Evaluate Protection Circuitry
LED Status Indications for Alarm Conditions
Support for Hardware and Host Modes
ORDERING INFORMATION:
CDB61584A
CDB61584A
Product Databook
Dual Line
Interfac e U n i t

DESCRIPTION

The evaluation board includes a socketed CS61584A dual line interface device and all support components necessary for evaluation. The board is powered by an external +5 Volt supply.
The board may be configured for 100 twisted-pair T1, 75 coax E1, or 120 twisted-pair E1 operation. Bind­ing posts and bantam jacks are provided for line interface connections. Several BNC connectors provide clock and data I/O at the system interface. Reference timing may be derived from a quartz crystal, crystal os­cillator, or an external reference clock. Four LED indicators monitor device alarm conditions.
5V+0V
CHANNEL1
CHANNEL2
TCLK1
TPOS1
(TDATA1)
TNEG1 RCLK1
RPOS1
(RDATA1)
RNEG1
(BPV1)
V+
HardwareControl
andModeCircuit
LEDStatus
Indicators
SerialInterface
ControlCircuit
TCLK2 TPOS2
(TDATA2)
TNEG2
RCLK2
RPOS2
(RDATA2)
RNEG2
(BPV2)
RESET
CIRCUIT
CS61584A
XTL
TTIP1
TRING1 RTIP1
RRING1
Oscillator
Circuit
TTIP2
TRING2 RTIP2
RRING2
CHANNEL1
REFCLK
CHANNEL2
DS261DB2 MAR ‘98
Copyright  Cirrus Logic, I nc. 1998
(All Rights Reserv ed)
CDB61584A
Dual Line Interface Unit

POWER SUPPLY

As shown on the evaluation board schematic in Figures 1-5, power is supplied to the board from an external +5 Volt supply connected to the two bind­ing posts labeled V+ and GND. Zener diode Z1 protects the components on the board from re­versed supply connections a nd over-voltage da m­age. Capacitor C16 provides power supply decoupling and ferrite bead L1 helps isolate the CS61584A and buffe r supplies. Both sides of the evaluation board contain extensive areas of ground plane to insure optimum perfo rm ance.
Capacitors C3, C5-C8, C13, C18, and C38 provide power supply decoup ling for the CS61584A. The BGREF pin is pulled down through resistor R10 to provide an in ternal current referenc e. The buffers are decoup led usi ng capa citors C 9, C15, and C1 9. Ferrite bea ds L2 -L4 he lp re duce th e pow er sup ply noise that i s c oupl ed from the buffers to the p ower supply.

BOARD CONFIGURATION

Slide switch SW6 selects hardware or host mode operation. Hardware mode is selected when switch SW6 is in the "HW" position and sets the MODE pin of the CS61584A to a logic 0. Host mode is se­lected wh en switch SW6 is in the "SW" pos ition and sets the MODE pin of the CS61584A to a logic 1.

Hardware Mode

In Hardware m ode operat ion, the evaluation board is configured using DIP switches SW2, SW 3, and SW4. In this mode, t he switc he s est ab li s h the digi­tal contro l inputs for bo th line interfa ce channels. Closing a DIP switch towards the label sets the CS61584A control pi n of the same name to a logic
1. The host pr ocessor interfac e J26 should not be used in the Hardware mo de.
The CDB61584A switches and functions are listed below:
- TAOS1, TAOS2: transmit all ones;
- LLOOP: local loopback of both channe ls;
- RLOOP1,2: remote loopback 1,2;
- PD1, PD2: power down;
- ATTEN0, ATTEN1: jitter attenuator selection;
- CLKE: RCLK edge polarity;
- 1XCLK: clock frequency selection;
- CONx1, CONx2: line configuration settings.
All switch inputs are pulled-down using resistor networks RP2-RP5.
The LOS1 and LOS2 LED indicators illuminate when the line interface receiver has detected a lo s s of signal. Headers J7 and J13 must be jumpered in the "TNEG" position to provide connectivity to the BNC input in Hardware mode.

Host Mode

In Host mode o perat io n, t he e valua tion bo ard sup ­ports serial-po rt operation o ver interface port J26 using the printer port of a host PC equipped with the enclosed software. The evaluation board is con­nected to the host PC using the ribbon cable provid­ed. The SW2 switch position labeled "ATTEN0" must be open to set th e P/S pin of the CS6 1584A to a logic 0 and en able serial-por t ope ration.
An external m icroprocessor may also in terface to the evaluation board for the purposes of system software development. The CS61584A interrupt pin is connecte d to pin 23 of interf ace port J26 to facilitate software developme nt. The SW2 switch position labele d "CL KE/ IPOL" es tabl ishes the po ­larity of the interrupt pin. If an active low interrupt is selected (IPOL low), the interrupt pin must be pulled-up through resistor R55 by placing a jumper on header J24. The SW2 switch position labeled "RLOOP1" must be in the open position for proper operation of the interrupt.
The LOS1 and LOS2 LED indicators illuminate when the line interface receiver has detected a lo s s of signal. If coder mode is enabled in the CS61584A registe r set , the A IS alarm cond itio n is
52 DS261DB2
CDB61584A
Dual Line Interface Unit
provided when headers J7 and J13 are jumpered in the "AIS" position. The AIS1 and AIS2 LED indi­cators illuminate when the line interface receiver has detected the all-ones rec eive input sign al. Re­sistors R26 and R 27 pull -dow n the TNE G(1,2) in ­puts when coder mode is disabled b ut headers J7 and J13 are jumpered i n the " A IS " position.
Further details concerning Host mode operation are described in t he "readme.txt" file on the enclosed disk.

Manual Reset

A momentary contact switch SW1 provides a man­ual reset by forcing the RESET pin of the CS61584A to a l ogic 1 . Alth ough th e t ransm it and receive circuitry are continuously calibrated, the reset can b e used to in it iali ze t he cont rol l ogic and clear the register set. Both channels are powered up after exit in g r eset.

TRANSMIT CIRCUIT

The transmit clock and data signals are supplied on BNC inputs labeled TCLK(1,2), TPOS(1,2), and TNEG(1,2). In Hardware and Host mode (with coder mode disabled), data is supplied on the TPOS(1,2) and TN EG( 1,2) BNC inpu ts in RZ for ­mat. In Host mode with code r mode enabled , data is supplied on the TDATA(1,2) BNC input in NRZ format and the TNEG(1,2) BNC input may be used to indicate the AIS alarm condition as described in the Host Mode section.
The transmitter output is transformer coupled to the line interfa ce through 1:1.15 step-up transforme rs T1 and T4. The signal is available at either the TTIP(1,2) and TRING(1,2) binding posts or the TX(1,2) bant am jacks.
Capacitors C2 and C11 prevent output stage imbal­ances from prod ucing a DC cu rrent that m ay satu­rate the transformer and result in an output level offset. Capacitors C1 and C12 p rovide tran smitter return loss and are socketed so the value may be changed according to the application. A 220 pF ca-
pacitor is required for 100 twisted-pair T1 or 120 twisted-pa ir E1 applications. A 470 pF ca­pacitor is requi red for 75 coax E1 applic ations. These capacitors are included with the evaluation board.
Optional diode locations D6-D9 and D10-D13 and optional resistor locations R8-R9 and R18-R19 provide test locat ions to evaluate transm it line in­terface prote ction circuit ry.

RECEIVE CIRCUIT

The rece ive signal is inp ut at eit her the RTIP(1,2 ) and RRING(1,2) binding posts or the RX(1,2) ban­tam jack s. The receive signal is tra nsformer cou­pled to the CS61584A through 1:1.15 step-down transformers T2 and T3.
The receive line is terminated by resistors R3-R4 and R14-R15 to pro vide impedance matching and receiver return l oss. Th ey are socket ed so the val­ues may be cha nged according to the applicati on. The evaluati on board is supplied from the factory with 38.3 resistors for terminating 100 twisted­pair T1 lines, 45.3 resistors for terminating 120 twisted-pair E1 lines, and 28.7 resistors for termi­nating 75 coaxial E1 lines. Capacitors C4 and C10 provide a differential input voltage reference.
Optional resistor loc ations R1 -R2, R12-R 13, R16­R17, and R24 -R25 provi de t est loc ations t o eva lu­ate receiv e l ine interface protection circuitry.
The recov ere d clo ck and d at a sign al s ar e a vail able on BNC outputs labeled RCLK(1,2), RPOS(1,2), and RNEG(1,2). In Hardware and Host mode (with coder mode disabled), data is available on the RPOS(1,2) and RNEG(1,2) BNC outputs in RZ format. In Host mode with coder mode enabled, data is ava ilable on the RDATA(1,2) BNC output in NRZ format an d bipolar viol ations are re ported on BPV(1,2).
DS261DB2 53
CDB61584A
Dual Line Interface Unit

REFERENCE CLOCK

The CDB61584A requires a T1 or E1 reference clock for op eration. Th is clock may operate at e i­ther a 1-X rate (1.544 MHz or 2.048 MHz) or an 8­X rate (12.352 MHz or 16.384 MH z) and can be supplied by eithe r a qua rtz crys tal, cryst al osci lla­tor, or exte rnal referenc e. The eva luation boar d is supplied from the fa ctory wi th two crystal oscilla ­tors for T1 and E1 operation.

Quartz Crystal

A quartz cry sta l m ay be inse rt ed at s oc ket Y 1. Be ­cause the c rystal operate s at a n 8-X ra te, t he S W2 switch position l abel ed "1XC LK " must be op en to set the 1XCL K pin of the CS61584A to a logic 0 and enable 8-X clock ope ration.

Crystal Oscillator

A crystal oscillator may be inserted at socket U4 in the orient atio n indi cated by the s ilksc reen . Hea der J14 must be jumpered in the "OSC" position to pro­vide connectivity to the REFCLK pin of the CS61584A. The SW2 switch position labeled "1XCLK" must be open (logic 0) for 8-X clock op­eration or closed (logic 1) for 1-X clock operation.

External Reference

An external reference may be provided at the REF­CLK BNC input . Head er J1 4 must be ju mper ed in the "REFCL K" p os ition t o p rov ide c onnec ti vity to the REFCLK pin of the CS61584A. The SW2 switch position labeled "1XCLK" must be open (logic 0) for 8-X clock operation or closed (logic 1) for 1-X clock operation.

BUFFERING

Buffers U2, U3, and U6 provide additional drive capability for the BNC and Host mode connections. The buffer outputs are filtered with an RC network to reduce the transients caused by buffer switching.

JTAG ACCESS

The CS61584A im plements JTAG bound ary scan to support board-level testing. Interface port J56 provides access to the four JTAG pins on the CS61584A. The J-TMS pin of the CS61584A is pulled-down by resistor R28 to disable boundary scan unles s the pin i s externa lly pull ed high us ing the interfa ce port.

TRANSFORMER SELECTION

The evaluati on board is supplied from the factory with Pulse Engi ne ering PE-65388 transformer s in­stalled at locations T1-T4. They are socketed to permit the evaluation of other transformers.

LINE PROTECTION EVALUATION

Several optional resistor and diode locations on the transmit and receive line interface allow for the in­stallation and evaluation of various types of protec­tion circuitr y. Each locatio n is drilled wit h 60 mil vias to permit the installation of sockets. These sockets can be obtained from McKenzie at (510) 651-2700 by requesting part #PPC-SIP-1X32­620C and are identical to the socket type installed at the re c eive resist or locations on t he board. They allow the line protection circuitry to be easily changed d uring testi ng. Note that the traces form­ing shorts between the socket locations on the line interface may need to be cut prior to the installation of protectio n circuitry.

PROTOTYPING AREA

Four prototyping areas with power supply and ground connec t ions are provided on the evaluation board. These areas c an be used to de velop and test a variety of additional circ uits such as fram er de­vices, system synchronizer PLLs, or specialized in­terface log ic .
54 DS261DB2
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