Cirrus Logic CDB5566 User Manual
CDB5566
5 kSps, 24-bit, High-throughput
Evaluation Board
Features
Two Analog Input Channels Multiplexed to the CS5566 ADC
Pre-configured to require a minimum number of external
connections to your data acquisition system.
All functionality accessible through the connector interface
and board-level options.
On-board 4.096 V Reference
Pre-configured for Master mode SPI™ communication to a
data capture system.
ΔΣ
ADC
General Description
The CDB5566 is a versatile tool designed for evaluating the functionality and performance of the CS5566 ADC (Analog-to-Digital
Converter). The SPI serial port on the CDB5566 evaluation board
is configured in Master mode and will start transmitting data after
power-up upon reset. This evaluation board is designed to connect
to your data capture system or will interface to the CapturePlus II
data acquisition system available from Cirrus Logic.
The CS5566 delta-sigma ADC produces fully settled conversions to
full specified accuracy at 5 kSps. This ability to produce fully settled
conversions for every sample makes it suitable for converting multiplexed input signals. To help evaluate this feature, the CDB5566
includes two differential analog inputs multiplexed into the CS5566.
The multiplexer can be switched at the CS5566 ADC sample speed
and the ADC will produce fully settled conversion data for each input
channel.
All evaluation board functionality for evaluating the CS5566 ADC is
accessed through the connector interface and board-level options.
Schematics in PADS™ PowerLogic™ format are available for
download at:
http://www.cirrus.com/en/products/pro/detail/P1120.html
ORDERING INFORMATION
CDB5566 Evaluation Board
.
www.cirrus.com
Copyright Cirrus Logic, Inc. 2009
(All Rights Reserved)
OCT ‘09
DS806DB3
CDB5566
TABLE OF CONTENTS
1. INTRODUCTION ....................................................................................................................... 3
1.1 Overview ............................................................................................................................ 4
2. QUICK START .......................................................................................................................... 5
3. HARDWARE DESCRIPTION ...................................................................................................6
3.1 Absolute Maximum Ratings ............................................................................................... 6
3.2 Power Supply ..................................................................................................................... 6
3.3 Analog Section ................................................................................................................... 6
3.3.1 Analog Input Buffers .............................................................................................. 6
3.3.2 Multiplexer ............................................................................................................. 7
3.3.3 ADC Reset ............................................................................................................ 7
3.3.4 Voltage Reference ................................................................................................ 7
3.3.5 ADC Reference Frequency ................................................................................... 7
3.4 Digital Section .................................................................................................................... 8
3.4.1 Hardware Configuration ........................................................................................ 8
3.4.2 SPI™ Serial Port Communications ....................................................................... 8
APPENDIX A. MAXIMIZING THE PERFORMANCE OF THE CS5566 ........................................ 9
A.1 PCB Layout Considerations .............................................................................................. 9
A.2 Hardware Considerations .................................................................................................. 9
APPENDIX B. BILL OF MATERIALS ................................................ ........................................ 10
APPENDIX C. SCHEMATICS ..................................................................................................... 11
APPENDIX D. LAYER PLOTS ................................................................................................... 16
APPENDIX E. CALIBRATION FUNCTION ................................................................................. 25
APPENDIX E. REVISION HISTORY ..........................................................................................26
LIST OF FIGURES
Figure 1. CDB5566 Block Diagram .................................................................................................4
Figure 2. CDB5566 Board Layout ................................................................................................... 5
Figure 3. Schematic - Block Diagram............................................................................................ 11
Figure 4. Schematic - Power Supplies .......................................................................................... 12
Figure 5. Schematic - Input Buffers and Multiplexer ..................................................................... 13
Figure 6. Schematic - CS5566 ...................................................................................................... 14
Figure 7. Schematic - Configuration & Misc. ................................................................................. 15
Figure 8. Top Silkscreen ............................................................................................................... 16
Figure 9. Top Solder Mask ............................................................................................................ 17
Figure 10. Top Routing.................................................................................................................. 18
Figure 11. Ground Plane ............................................................................................................... 19
Figure 12. Power Plane................................................................................................................. 20
Figure 13. Bottom Solder Mask..................................................................................................... 21
Figure 14. Bottom Silkscreen ........................................................................................................ 22
Figure 15. Top Solder Paste Mask................................................................................................23
Figure 16. Bottom Routing ............................................................................................................ 24
LIST OF TABLES
Table 1. Power Supply Connections ...............................................................................................6
Table 2. Analog Input Connections ................................................................................................. 6
Table 3. Analog Input Channel Selection ........................................................................................ 7
Table 4. Hardware Configuration Signals........................................................................................ 8
Table 5. Serial Interface Connections ............................................................................................. 8
2 DS806DB3
CDB5566
1. INTRODUCTION
The CDB5566 evaluation board is a platform for evaluating the CS5566 ADC performance. The evaluation board is designed to connect to the SPI serial port of a processor or data capture system or will interface directly to the CapturePlus II data acquisition system available from Cirrus Logic. The CapturePlus II
data acquisition system is a powerful integrated hardware/software tool designed to fully exercise the
CDB5566 and other Cirrus Logic evaluation boards.
The CDB5566 evaluation board is designed to simplify the hardware setup required to evaluate the
CS5566. Interfacing the CDB5566 evaluation board to a user-supplied data capture system can be as
simple as connecting the SPI port and using the CDB5566 default hardware configuration. In this configuration, simply press the Reset switch on the CDB5566 and it will automatically begin transmitting data to
the data capture system.
All evaluation board functionality for evaluating the CS5566 ADC is accessed through the connector interface and board-level options.
The CS5566 delta-sigma ADC produces fully settled conversions to full specified accuracy at 5 kSps. The
ability to produce fully settled conversions for every sample makes it suitable for converting multiplexed
input signals. To help evaluate this feature, the CDB5566 includes two differential analog inputs multiplexed into the CS5566. The multiplexer can be switched at the CS5566 ADC sample speed and the ADC
will produce fully settled conversion data for each input channel.
For detailed information on the CS5566 ADC, please reference data sheet DS806 at www.cirrus.com
.
DS806DB3 3
CDB5566
CS5566
M
U
X
VREF
4.096 V
XTAL
16 MHz
Communication/Control
Interface
Master/Slave
Serial Port
Digital Inputs
to ADC
Digital Outputs
from ADC
INPUT A
+2.5V GND -2.5V GND +3.3V GND
J8
J6
J7
LMP7732
Differential
Analog Inputs
INPUT B
LMP7732
Figure 1. CDB5566 Block Diagram
1.1 Overview
The CDB5566 evaluation board has both analog and digital circuit sections. The analog section consists
of the CS5566 ADC, two analog input signal buffers, controlled through a multiplexer, that condition the
signals into the ADC, and a precision 4.096 V reference. The digital section consists of board operation
configuration control signals, reset circuitry, an SPI™ serial port, a jumper connection for initiating ADC
calibration, and an EEPROM for evaluation board identification.
The evaluation board operates from +2.5V, -2.5V, +3.3V and communicates through an SPI™ serial port.
Figure 1 illustrates the CDB5566 block diagram.
4 DS806DB3
2. QUICK START
Master/Slave SPI ADC MCLK Out
Digital Control Signals to ADC & Mux
ADC Reset Analog Inputs
DC Supply
Buffer Enable Calibrate 4.096 V Reference
CDB5566
NOTES:
1. Shaded boxes marked with "OPT. CONFIG." are not necessary for operation in an end user product.
2. Calibration function has been removed from the device but still appears on the PCB. J2 must be shorted (grounded)
for proper operation. See Appendix E for details.
2
Figure 2. CDB5566 Board Layout
CDB5566
The CDB5566 evaluation board is designed to interface with a data acquisition system. To connect and
configure the CDB5566 perform the following initialization procedure:
1. Verify that the power supplies are off.
2. Connect the power supplies to the CDB5566 as shown in Table 1 on page 6.
3. Verify that the power is off to the analog input signal & control signal sources.
4. Connect the analog input signal source to the evaluation board per Table 2 on page 6. Verify from Table 4
on page 8 that the analog input channel selected is INPUT A.
5. Configure the CDB5566 by connecting the control signal sources to the evaluation board as shown in
Table 3 on page 7. Apply logic-level inputs as required to override the resistor pull-ups/pull-downs.
6. Make connections to the SPI™ serial port connector as shown in Table 5 on page 8. The CS5566 ADC
serial port is configured by default to operate in the SSC (Synchronous Self Clocking) mode. Refer to the
CS5566 data sheet for more information on serial communication modes and signal timing.
7. Turn on the power supplies to the evaluation board.
8. Apply power to the signal source.
9. Press the Reset switch on the evaluation board.
10. The CS5566 ADC's SPI™ serial port should now be communicating data.
DS806DB3 5
3. HARDWARE DESCRIPTION
3.1 Absolute Maximum Ratings
Observe the following limits to ensure the CDB5566 component ratings are not exceeded.
• CS5566
– The absolute maximum supply voltage that can be applied to the +3.3V power supply
connection is +3.6V.
– The absolute maximum power supply voltage that can be applied between pins VL and V1-
is 6.1 V.
• LMP7732
– The absolute maximum power supply voltage that can be applied between the +2.5V and
-2.5V power supply connections is +5.5V.
3.2 Power Supply
Power supply connections and requirements are specified in Table 1. below.
Table 1. Power Supply Connections
CDB5566
Power Supply
Requirement
+2.5 V DC, ±5%, <50 mA E5 E3 TP2, TP1 (GND)
-2.5 V DC, ±5%, <50 mA E9 E7 TP4, TP3 (GND)
+3.3 V DC, ±5%, <50 mA E16 E13 TP6, TP5 (GND)
Power Supply
Connection
Associated
Ground Return
Associated
T est Points
Important: It is recommended that all power supplies be isolated from utility ground to prevent the introduction of a ground loop. One ground connection may already exist through the serial port connection to
utility ground. Using the Cirrus Logic CapturePlus II system simplifies making connections to the
CDB5566 by providing electrical isolation between the two.
Using twisted/shielded wire will reduce electrical noise induced onto the power supply cables.
Power supplies are to be adequately regulated and sufficiently low noise to meet the application requirements.
3.3 Analog Section
3.3.1 Analog Input Buffers
The analog input signal connections to the input buffers are made at the INPUT A andINPUT B connectors, as specified in Table 2.
Table 2. Analog Input Connections
Analog Input
Channel
INPUT A J4 -4.096 V to +4.096 V 50 Ohms
INPUT B J5 -4.096 V to +4.096 V 50 Ohms
Connection
Differential Input Signal
Voltage Range Impedance
There are two analog input channels on the evaluation board. Each analog inpu
t channel consists of
two low-noise amplifiers configured as unity gain non-inverting buffers. The buffers utilize two National
Semiconductor LMP7732 precision, low-noise, low-voltage, dual op-amps. These op-amps enable both
the inputs and outputs of the analog input buffer to operate virtually rail to rail. The channel input impedance is 50 Ohms.
6 DS806DB3
CDB5566
For detailed information on the LMP7732 precision industrial op-amps, please visit National Semiconductor’s website at www.national.com
The analog inputs are designed for connections to differential input signals. The usable input voltage
range is -4.096 V to +4.096 V. The theoretical input frequency range of the CS5566
Nyquist frequency of 2.5 kHz. The analog input buffer amplifiers are configured for a cutoff frequency of
16.8 kHz to band-limit noise into the ADC. Changing the cutoff frequency will change the noise bandwidth
accordingly.
3.3.2 Multiplexer
Analog input channel selection is controlled through the multiplexer. The multiplexer is configured with a
pull-down resistor on the MUX control line to enable input channel labeled "INPUT A" by default. To select
channel B, apply 3.3 V to the multiplexer input control line (MUX).
Signal levels for controlling the multiplexer that selects between analog input channels A and B is shown
in Table 3.
.
is from DC to the
Table 3. Analog Input Channel Selection
Multiplexer
Control Input (MUX)
0V A
3.3 V B
Input Channel
Enabled
During multiplexing, the maximum sample rate for each channel is half that of the ADC’s maximum sample rate. Additionally, the Nyquist frequency for each channel is half of the ADC’s Nyquist frequency.
3.3.3 ADC Reset
The CS5566 ADC makes use of an externally generated power-on reset. Therefore, after power is applied to the ADC, the reset pin must be driven low then released. Pressing the Reset button generates a
reset cycle. A reset cycle can be generated at any time during ADC operation. The ADC RST
pin (active
low) is held inactive through a pull-up resistor.
3.3.4 Voltage Reference
The voltage reference IC provided generates a 4.096 V precision reference.
3.3.5 ADC Reference Frequency
The reference frequency for the CS5566 ADC is provided by a 8.000 MHz oscillator.
DS806DB3 7
CDB5566
3.4 Digital Section
3.4.1 Hardware Configuration
The CDB5566 evaluation board hardware comes pre-configured so the only connection required between
it and a data acquisition system is the serial port connection.
The hardware setup is reconfigurable through the hardware control interface connectors. Configure the
evaluation board by setting the appropriate control line to the appropriate logic level.
Table 4. Hardware Configuration Signals
Function Default Level Label Connector Test Point
Input Channel Select INPUT A = Selected (Low) MUX J6, Pin 16 J3, Pin 2
Analog Input Buffers Buffers = Enabled (High) BUFEN J1 J3, Pin1
Serial Port Mode Sync. Self Clock = Enabled (High) SMODE J6, Pin 12 J3, Pin 3
Data Ready Flag Data Ready When Set (Low) RDY
Reset Reset = Inactive (High) RST
Bipolar / Unipolar Mode Bipolar = Enabled (High) BP / UP
Sleep Mode Sleep = Inactive (High) SLEEP
Serial Port Communication Chip Select = Enabled (Low) CS
Data Conversion Mode Continuous Conversion = Active (Low) CONV
J8, Pin 10 J3, Pin 4
J6, Pin 6; S1 J3, Pin 6
J6, Pin 2 J3, Pin 8
J6, Pin 4 J3, Pin 9
J8, Pin 2 E23
J8, Pin 12 E21
3.4.2 SPI™ Serial Port Communications
The CS5566 ADC communications port features an SPI™ serial port. It can be configured for SSC mode
(Master) or SEC mode (Slave) mode as shown in Table 4. Test points are provided to monitor serial communications.
Connections to the serial interface are made according to the following table.
Table 5. Serial Interface Connections
Function Label Connector Test Point
Chip Select CS J8, Pin 2 E23
Serial Data Input SDI J8, Pin 4 E24
Serial Data Output SDO J8, Pin 6 E25
Serial Clock SCLK J8, Pin 8 E26
8 DS806DB3
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