Evaluation Board for CS53L21
CDB53L21
Features
Selectable Analog Inputs
– Stereo Line-Level RCA Jacks
– Stereo Microphone 1/8” Jacks
Stereo Microphone Input Jacks
8- to 96-kHz S/PDIF Output
– CS8406 Digital Audio Transmitter
I/O Stake Headers
– External Control Port Accessibility
– External DSP Serial Audio I/O Accessibility
Independent, Regulated Supplies
1.8 V to 3.3 V Logic Interface
Hardware Control
– 4 Pre-Defined Switch Settings
FlexGUI S/W Control - Windows
– Pre-Defined & User-Configurable Scripts
®
Compatible
Description
The CDB53L21 evaluation board is an excellent means
for evaluating the CS53L21 ADC. Evaluation requires
an analog audio source, an analog/digital analyzer and
power supplies. Optionally, a Windows
computer may be used to evaluate the CS53L21 in Software Mode.
System timing can be provided by the CS53L21 with
supplied master clock, or by using an I/O stake header
with a DSP connected.
RCA phono jacks are provided for the CS53L21 analog
inputs. 1/8” jacks are also available for microphone inputs. A digital data output is available from the CS8406
via RCA phono or optical connectors.
The Windows software provides a GUI to make configuration of the CDB53L21 easy. The software
communicates through the PC’s serial port or USB port
to configure the control port registers so that all features
of the CS53L21 can be evaluated. The evaluation board
may also be configured to accept external timing and
data signals for operation in a user application during
system development.
PC-compatible
Layout and Grounding Recommendations
Software Mode
Control Port
Reset
Hardware Mode
Switches
S/PDIF Output
(CS8406)
FPGA
Reset
MCLK
Oscillator
(socket)
ORDERING INFORMATION
CDB53L21 Evaluation Board
I²C/SPI Header
MCLK
Reset
Clocks/Data Header
Reset
CS53L21
Analog Input
(Line or MIC)
http://www.cirrus.com
Copyright © Cirrus Logic, Inc. 2006
(All Rights Reserved)
MARCH '06
DS700DB1
TABLE OF CONTENTS
1. SYSTEM OVERVIEW ............................................................................................................................. 4
1.1 Power ............................................................................................................................................... 4
1.2 Grounding and Power Supply Decoupling ...................... ... .... ... ... ... ... .... ........................................... 4
1.3 FPGA ................................................................................................................................................ 4
1.4 CS53L21 Audio A to D Converter ..................................................................................................... 4
1.5 CS8406 Digital Audio Transmitter ............... ... ... ... .... ........................................................................ 5
1.6 Oscillator ........................................................................................................................................... 5
1.7 I/O Stake Headers ............................................................................................................................ 5
1.8 Analog Input ..................................................................................................................................... 5
1.9 Stand-Alone Switches ...................................................................................................................... 6
1.10 Control Port Connectors ................................................................................................................. 6
1.10.1 RS-232 and USB Connectors ...............................................................................................6
2. SOFTWARE MODE CONTROL ............................................................................................................. 7
2.1 General Configuration Tab ............................................................................................................... 8
2.2 ADC Configuration Tab .................................................................................................................... 9
2.3 ADC Volume Controls Tab ............................................................................................................. 10
2.4 Mix Volume Controls Tab ............................................................................................................... 11
2.5 Register Maps Tab ......................................................................................................................... 12
3. HARDWARE MODE CONTROL .......................................................................................................... 13
3.1 FPGA H/W Control ......................................................................................................................... 13
3.2 CS53L21 H/W Control .................................................................................................................... 16
4. PERFORMANCE PLOTS ..................................................................................................................... 17
5. SYSTEM CONNECTIONS AND JUMPERS ........................................................................................ 20
6. BLOCK DIAGRAM ............................................................................................................................... 22
7. SCHEMATICS ...................................................................................................................................... 23
8. BOARD LAYOUT ................................................................................................................................. 30
9. REVISION HISTORY ............................................................................................................................ 33
CDB53L21
2 DS700DB1
LIST OF FIGURES
Figure 1.General Configuration Tab ............................................................................................................ 8
Figure 2.ADC Configuration Tab ................................................................................................................. 9
Figure 3.ADC Volume Controls Tab .......................................................................................................... 10
Figure 4.Mix Volume Controls Tab ............................................................................................................ 11
Figure 5.Register Maps Tab - CS53L21 ................................................................................................... 12
Figure 6.Routing 4 ..................................................................................................................................... 14
Figure 7.Routing 6 ..................................................................................................................................... 14
Figure 8.Routing 8 ..................................................................................................................................... 15
Figure 9.Routing 10 ................................................................................................................................... 15
Figure 10.0 dB FFT, Single-Speed Mode ........................................... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ......... 17
Figure 11.0 dB FFT, Double-Speed Mode ... ... ... .... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... .... ............ 17
Figure 12.-60 dB FFT, Single-Speed Mode ................................. .... ... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ......... 17
Figure 13.-60 dB FFT, Double-Speed Mode ... ... .... ... ... .......................................... ................................... 17
Figure 14.No Input FFT, Single-Speed Mode ........................................................................................... 17
Figure 15.No Input FFT, Double-Speed Mode .......................... ... .... ......................................................... 17
Figure 16.THD+N vs. Frequency, Single-Speed Mode ............................................................................. 18
Figure 17.THD+N vs. Frequency, Double-Speed Mode ..................... ... ... ... .... ... ... ... .... ............................ 18
Figure 18.THD+N vs. Amplitude, Single-Speed Mode .............................................................................. 18
Figure 19.THD+N vs. Amplitude, Double-Speed Mode ............................................................................ 18
Figure 20.Fade-to-Noise Linearity, Single-Speed Mode ...........................................................................18
Figure 21.Fade-to-Noise Linearity, Double-Speed Mode .......................................................................... 18
Figure 22.Frequency Response, Single-Speed Mode .............................................................................. 19
Figure 23.Frequency Response, Double-Speed Mode ............................. ... .... ... ...................................... 19
Figure 24.Channel Crosstalk, Single-Speed Mode ................................................................................... 19
Figure 25.Channel Crosstalk, Double-Speed Mode .................................................................................. 19
Figure 26.Block Diagram ........................................................................................................................... 22
Figure 27.CS53L21 (Part of Schematic Sheet 1) ...................................................................................... 23
Figure 28.Analog I/O (Part of Schematic Sheet 1) .................................................................................... 24
Figure 29.S/PDIF I/O (Schematic Sheet 2) ............................................................................................... 25
Figure 30.FPGA (Schematic Sheet 3) ....................................................................................................... 26
Figure 31.Level Shifters & I/O Stake Header (Schematic Sheet 4) .......................................................... 27
Figure 32.Control Port I/O (Schematic Sheet 5) ....................................................................................... 28
Figure 33.Power (Schematic Sheet 6)lm .................................................................................................. 29
Figure 34.Silk Screen ................................................................................................................................ 30
Figure 35.Top-Side Layer ......................................................................................................................... 31
Figure 36.Bottom-Side Layer .................................................................................................................... 32
CDB53L21
LIST OF TABLES
Table 1. MCLK and Clock/Data Routing Options ...................................................................................... 13
Table 2. CS53L21 H/W Mode Control .......................... ... .......................................... ................................ 16
Table 3. System Connections ................ ... ... ... ... .... ...................................... .... ... ... ... .... ... ... ... ................... 20
Table 4. Jumper Settings ................... .... ... ... ... ... .... ... ....................................... ... ... ... .... ... ... ...................... 21
DS700DB1 3
CDB53L21
1. SYSTEM OVERVIEW
The CDB53L21 evaluation board is an excellent means for evaluating the CS53L21 ADC. Digital audio signal outputs are provided, and an FPGA is used for easily configuring the board. Section 2. “Software Mode Control” on
page 7 and Section 3. “Hardware Mode Control” on page 13 provide configuration details.
The CDB53L21 schematic set has been partitioned into seven pages and is sh own in Figures 27 through 33. “Sys-
tem Connections and Jumpers” on page 20 provides a description of all stake headers and connectors, including
the default factory settings for all jumpers.
1.1 Power
Power is supplied to the evaluation board through the +5.0 V binding posts. Jumpers connect the ADC’s
supplies to a regulated voltage of +1.8 V, 2.5 V or +3.3 V for VL and +1.8 V or 2.5 V for VD and VA. All voltage inputs must be referenced to the black binding post ground connector.
For current measurement purposes only, a series resistor is connected to each supply. The current is easily
calculated by measuring the voltage drop across this resistor. NOTE: The stake headers connected in parallel with these resistors must be shunted with the supplied jumper during normal operation.
WARNING: Please refer to the CS53L21 data sheet for allowable voltage levels.
1.2 Grounding and Power Supply Decoupling
The CS53L21 requires careful attention to power supply and grounding arrangements to optimize performance. The CDB53L21 demonstrates these optimal arrangements. Figure 26 on page 22 provides an overview of the connections to the CS53L21. Figure 34 on pag e 30 shows the com ponent pla cement, Figur e 35
on page 31 shows the top layout, and Figure 36 on page 32 shows the bottom layout. The decoupling ca-
pacitors are located as close to the CS53L21 as possible. Extensive use of ground plane fill in the evaluation
board yields large reductions in radiated noise.
1.3 FPGA
The FPGA provides digital signal routing between the CS53L21, CS8406 and the I/O stake header. It also
configures the Hardware Mode options of the CS8406 and provides routing control of the system master
clock from an on-board oscillator and the I/O stake header. The Cirrus FlexGUI software and “FPGA H/W
Control” switches provide full control of the FPGA’s routing and configuration options. Section 2. “Software
Mode Control” on page 7 and Section 3. “Hardware Mode Control” on page 13 provide configuration details.
1.4 CS53L21 Audio A to D Converter
A complete description of the CS53L21 (Figure 27 on page 23) is included in the CS53L21 product data
sheet.
The CS53L21 may be configured using either the Cirrus FlexGUI or the on-board “CS53L21 H/W Control”
switches. The Software Mode control port registers are accessible through the “Register Maps” tab of the
Cirrus FlexGUI software. This tab provides low-level control of each bit. For easier configuration, additional
tabs provide high-level control. The Hardware Mode, stand-alone controls for the CS53L21 are accessible
through the on-board, stand-alone switches, “CS53L21 H/W Control.”
Clock and data source selections are made in the cont rol port of the FPGA, accessible through the “Gene ral
Configurations” tab of the C irr us FlexGUI software or throu gh t he on-board “FPGA H/W Control” switches.
Section 2. “Software Mode Control” on page 7 and Section 3. “Hardware Mode Control” on page 13 provide
configuration details.
4 DS700DB1
1.5 CS8406 Digital Audio Transmitter
A complete description of the CS8406 transmitter ( Figure 29 on page 25 ) and a discussion of the d igital audio interface are included in the CS8406 data sheet.
The CS8406 converts the PCM data generated by the CS53L21 to the standard S/PDIF data stream and
routes this signal to the optical and RCA connectors. The CS8406 operates in slave mode only, accepting
either a 128xFs or 256xFs master clock, and can operate in eithe r the Left-Justified or I²S inte rface format.
Selections are made in the control port of the FPGA, accessible through the “General Configurations” tab
of the Cirrus FlexGUI software or through the on-boa rd switches, “FPGA H/W Control.” Section 2. “Software
Mode Control” on page 7 and Section 3. “Hardware Mode Control” on page 13 provide configuration details.
1.6 Oscillator
The on-board oscillator provides one of the system master clocks. Selections are made in the control port
of the FPGA, accessible through the “General Configurations” tab of the Cirrus FlexGUI software or through
the on-board switches, “FPGA H/W Control.” Section 2. “Software Mode Control” on page 7 and Section 3.
“Hardware Mode Control” on page 13 provide configuration details.
The oscillator is mounted in pin sockets, allowing easy removal or replacement. Additional sockets are also
installed, allowing the optional use of a full- or half-can-sized oscillator.
1.7 I/O Stake Headers
CDB53L21
The evaluation board has been designed to allow interfacing with external systems via a se rial port hea der
(reference designation J5) and a control port header, “CS53L21 S/W Control.” The serial port header provides access to the serial audio signals required to interface with a DSP (Figure 31 on page 27). Selections
are made in the control port of the FPGA, accessible through the “ General Configur ations” tab of the Cirrus
FlexGUI software or through the on-board switches, “FPGA H/W Control.” Section 2. “Software Mode Con-
trol” on page 7 and Section 3. “Hardware Mode Control” on page 13 provide configuration details.
The control port header provides bidirectional access to the SPI™/I²C
moving all the shunt jumpers from the “PC” position. The user may then choose to connect a ribbon cable
to the “CONTROL” position, allowing operation of the CS53L21 in a user-application for system development. A single “GND” row for the ribbon cable’s ground connection is provided to maintain signal integrity.
Two unpopulated pull-up resistors are also available should the user choose to use the CDB for the I²C power rail.
1.8 Analog Input
RCA connectors supply the line-level analog inputs through an AC-coupled passive filter. The signal from
these inputs may be driven to individual inputs or to all inputs of the CS53L21. A microphone may be connected to one or both of the 1/8” jacks, MIC1 and MIC2.
To accommodate the microphone bias output available on certain input pins of the CS53L21, additional
stake headers are provided to MUX both the input audio signal and the output bias signal to or from the
CS53L21. Figure 28 on page 24 in the schematic set illustrates how signals are routed. Table 4 on page 21
provides more details for how to connect the jumpers. The CS53L21 data sheet details the required singleended signal amplitude that will drive the inputs to full scale.
®
control port signals by simp ly re-
DS700DB1 5
1.9 Stand-Alone Switches
The “FPGA H/W Control” and “CS53L21 H/W Control” switches control all Hardware Mode options.
Section 3. “Hardware Mode Control” on page 13 provides a description of each topology.
1.10 Control Port Connectors
A graphical user interface is available for the CDB53L21, allowing easy ma nipulation of ea ch registe r. This
GUI interfaces with the CDB via the RS-232 or USB connectors and controls all Software Mode options.
Section 2. “Software Mode Control” on page 7 provides a description of the Graphical User Interface (GUI).
1.10.1 RS-232 and USB Connectors
Connecting a cable to the R S-232 connector or the USB 1.0/2.0 connector and launching the Cirrus
FlexGUI software enables the CDB53L21 in Software Mode.
CDB53L21
6 DS700DB1
CDB53L21
2. SOFTWARE MODE CONTROL
The CDB53L21 may be used with the Microsoft Windows-based FlexGUI graphical user interface, allowing software
control of the CS53L21 and FPGA registers. The latest control software may be downloaded from
www.cirrus.com/msasoftware. Step-by-step instructions for setting up the FlexGUI are provided as follows :
1. Download and install the FlexGUI software as instructed on the Website.
2. Connect and apply power to the +5.0 V binding post.
3. Connect the CDB to the host PC using either a 9-pin serial or USB cable .
4. Launch the Cirrus FlexGUI. Once the GUI is launched successfully, all registers are set to their default reset
state.
5. Enable the CS53L21 by engaging the “Enable CS53L21” push button.
6. Refresh the GUI by clicking on the “Update” button. The default state of all registers are now visible.
7. Engage and then disengage the “Power Down” push button in the “ADC Basic Configurations” group. This
performs the necessary write sequence to the CS53L21 for Software Mode operation.
For standard setup:
8. Set up the signal routing in the “General Configurations” tab as desired.
9. Set up the CS53L21 in the “ADC Configuration”, “ADC Volume Controls” or “Mix Volume Controls” tab as
desired.
10. Begin evaluating the CS53L21.
For quick setup, the CDB53L21 may, alternatively, be configured by loading a predefined sample script file:
11. On the File menu, click "Restore Board Registers..."
12. Browse to Boards\CDB53L21\Scr ipt s\.
13. Choose any one of the provided scripts to begin evaluation.
To create personal scripts files:
14. On the File menu, click "Save Board Registers..."
15. Enter any name that sufficiently describes the created setup.
16. Choose the desired location and save the script.
17. To load this script, follow the instructions from step 11 above.
DS700DB1 7
2.1 General Configuration Tab
The “General Configuration” tab provides high-level control of signal routing on the CDB53L21. This tab also
includes basic controls for the CS53L21 for quickly setting up the CDB53L21 in simp le config urations. Status text detailing the ADC’s specific configuration is shown in parenthesis or appears directly below the associated control. This text may change depending on the setting of the associated control. A description of
each control group is outlined below:
ADC Basic Configuration - Includes basic register controls in the CS53L21 used for setting up the interface
format, clocking functions and internal analog input routing. See Section 2.2 through Section 2.4 for more
CS53L21 controls.
S/PDIF Transmitter Control - Includes all available Hardware Mode controls for setting up the CS8406.
Clock/Data Routing and ADC Reset - Includes controls used for routing clocks and data between the
CS53L21, oscillator and the I/O stake header. Also included is a reset control for the CS53L21.
Update - Reads all registers in the FPGA and CS53L21 and reflects the current values in the GUI.
Reset - Resets FPGA to default routing configuration.
CDB53L21
Figure 1. General Configuration Tab
8 DS700DB1
2.2 ADC Configuration Tab
The “ADC Configuration” tab provides high-level control of all setu p configurations fo r the CS53L21. Status
text detailing the ADC’s specific configuration is shown in parenthesis or app ears directly below the associated control. This text will change depending on the setting of the associated control. A description of each
control group is outlined below (a description of each register is included in the CS53L21 data sheet):
Power Control - Includes all register controls for powering down specific circuits within the CS53L21.
ADC input Configuration - Includes controls for the internal MUX, analog input, microphon e bias output an d
channel mix.
Serial Port Configuration - Includes controls for all settings related to the transmission and relationship of
data and clocks within the CS53L21.
Update - Reads all registers in the CS53L21 and reflects the current values in the GUI.
Reset - Resets the CS53L21.
CDB53L21
Figure 2. ADC Configuration Tab
DS700DB1 9
2.3 ADC Volume Controls Tab
The “ADC Volume Controls” tab provides high-level control of all volume settings in the ADC of the
CS53L21. Status text detailing the ADC’s specific configuration is shown in parenthesis or inside the control
group of the affected control. This text will change depending on the setting of the associated control. A description of each control group is outlined below (a description of each register is included in the CS53L21
data sheet):
Digital Volume Control - Includes digital volume controls and adjustments for the ADC.
ALC Configuration - Includes all configuration settings for the Automatic Level Control (ALC).
Analog Volume Control - Includes all analog volume controls and adjustments for the ADC.
Noise Gate Configuration - Includes all configuration settings for the noise gate.
Update - Reads all registers in the CS53L21 and reflects the current values in the GUI.
Reset - Resets the CS53L21.
CDB53L21
Figure 3. ADC Volume Controls Tab
10 DS700DB1
2.4 Mix Volume Controls Tab
The “Mix Volume Controls” tab provides high-level control of the ADC channel mix fun ctions. Status text detailing the ADC’s specific configuration is shown in read-only edit boxes or appears directly below the associated control. This text will change, depending on the setting of the associated control. A description of
each control group is outlined below (a description of each register is included in the CS53L21 data sheet):
Digital Volume Control - ADC channel mix volume controls and adjustments.
Update - Reads all registers in the CS53L21 and reflects the current values in the GUI.
Reset - Resets the CS53L21.
CDB53L21
Figure 4. Mix Volume Controls Tab
DS700DB1 11
2.5 Register Maps Tab
The Advanced Register Debug tab provides low-level control of the CS53L21 individual register settings.
Register values can be modified bit-wise or byte-wise. For bit-wise, click the appropriate push-b utton for the
desired bit. For byte-wise, the desired hex value can be typed directly into the register address box in the
register map. The “FPGA” and “GPIO” tabs may be ignored.
CDB53L21
Figure 5. Register Maps Tab - CS53L21
12 DS700DB1
CDB53L21
3. HARDWARE MODE CONTROL
The CDB may be configured without the use of a software control port through the use of two switches, “FPGA H/W
Control” and “CS53L21 H/W Control.” These switches are enabled in Hardwa re Mode only a nd ignore d in Software
Mode. The CDB53L21 automatically enters Hardware Mode upon initial power up, or wh en exiting Softwar e Mo de,
by terminating the Cirrus FlexGUI software or by disconnecting the RS-232 serial cable or USB cable.
3.1 FPGA H/W Control
The “FPGA H/W Control” switch S3 sets up the CDB in 4 pre-defined routing topologies in Hardware Mode.
The tables and figures below describe each switch setting. The At-A-Glance Controls table pro vides a quick
reference for all presets.
At-A-Glance Controls
S[3:2] S[1] (See Note 1.) S[0]
00 - Reserved
01 - I/O Header MCLK / I/O Header clocks/data route through
FPGA
10 - Oscillator MCLK / I/O Header clocks/data route through FPGA
11 - Reserved
0 - CS53L21 Slave Routing
1 - CS53L21 Master Routing
0 - No Loopback Routing
1 - Reserved
Signal
S[3:0] General Description Detailed Description
Routing
0 0000 Reserved
1 0001 Reserved
2 0010 Reserved
3 0011 Reserved
I/O MCLK
4
Figure 6
5 0101 Reserved
6
Figure 7
7 0111 Reserved
8
Figure 8
9 1001 Reserved
10
Figure 9
11 1011 Reserved
12-15 Reserved
0100 I/O Clocks/Data
0110 CS53L21 Clocks, I/O Data
Oscillator MCLK
1000 I/O Clocks/Data
1010 CS53L21 Clocks, I/O Data
1) I/O masters MCLK. 2) I/O masters PCM clocks.
3) SDOUT to CS8406 and I/O Header
1) I/O masters MCLK. 2) CS53L21 masters PCM clocks.
3) SDOUT to CS8406 and I/O Header
1) Oscillator masters MCLK. 2) I/O masters PCM clocks.
3) SDOUT to CS8406 and I/O Header
1) Oscillator masters MCLK. 2) CS53L21 masters PCM clocks.
3) SDOUT to CS8406 and I/O Header
Table 1. MCLK and Clock/Data Routin g Op tion s
Notes:
1. The S[1] setting affects FPGA signal routing only and is independent of the
H/W Control” switch S5. These settings must be made manually by the user and have to be consistent.
M/S setting of the “CS53L21
DS700DB1 13
CS8406
OMCK
(256Fs)
ILRCK/
ISCLK
I/O Header
MCLK
LRCK/SCLK
SDOUT
SDIN
CDB53L21
Oscillator
CS53L21
MCLK
LRCK/SCLK
SDOUT
(LJ)
CS8406
OMCK
(256Fs)
ILRCK/
ISCLK
I/O Header
MCLK
LRCK/SCLK
SDOUT
SDIN
Figure 6. Routing 4
Oscillator
CS53L21
MCLK
LRCK/SCLK
SDOUT
(LJ)
Figure 7. Routing 6
14 DS700DB1
CS8406
OMCK
(256Fs)
ILRCK/
ISCLK
I/O Header
MCLK
LRCK/SCLK
SDOUT
SDIN
CDB53L21
Oscillator
CS53L21
MCLK
LRCK/SCLK
SDOUT
(LJ)
CS8406
OMCK
(256Fs)
ILRCK/
ISCLK
I/O Header
MCLK
LRCK/SCLK
SDOUT
Figure 8. Routing 8
Oscillator
SDIN
(LJ)
MCLK
LRCK/SCLK
CS53L21
SDOUT
Figure 9. Routing 10
DS700DB1 15
3.2 CS53L21 H/W Control
The stand-alone “CS53L21 H/W Control” switch S5 controls the Hardware Mode options of the CS53L21.
A description of each switch is outlined in the following table. See the CS53L21 Data Sheet, Section 4.2
“Hardware M
ode” for further details on setting these switches.
Switch Position Function
M/S (Note 1.) LO LRCK and SCLK are inputs to CS53L21.
HI LRCK and SCLK are outputs to CS53L21.
MCLKDIV2
I2S/LJ
(Note 2.)
LO Internal MCLK to CS53L21 not divided.
HI Internal MCLK to CS53L21 divided by 2.
LO CS53L21 Interface Format: Left-Justified.
HI CS53L21 Interface Format: I²S.
CDB53L21
Table 2. CS53L21 H/W Mode Control
Notes: 1. The
switch S3.
2. The I2S/LJ setting affects the CS53L21 only. The S/PDIF Transmitter input data format in HW Mode is
always
Header will have to be used.
M/S setting affects the CS53L21 only and is independent of S[1] setting in the “FPGA H/W Control”
These settings must be made manually by the user and have to be consistent.
LJ and is independent of this setting. If the user desires I2S format PCM SDOUT data, the I/O
16 DS700DB1
4. PERFORMANCE PLOTS
+0
+0
+0
+0
+0
+0
CDB53L21
-10
-20
-30
-40
-50
-60
-70
-80
d
B
-90
F
-100
S
-110
-120
-130
-140
-150
-160
-170
-180
20 20k50 100 200 500 1k 2k 5k 10k
Hz
-10
-20
-30
-40
-50
-60
-70
-80
d
B
-90
F
S
-100
-110
-120
-130
-140
-150
-160
-170
-180
20 20k50 100 200 500 1k 2k 5k 10k
Hz
Figure 10. 0 dB FFT, Single-Speed Mode Figure 11. 0 dB FFT, Double-Speed Mode
-10
-20
-30
-40
-50
-60
-70
-80
d
B
-90
F
S
-100
-110
-120
-130
-140
-150
-160
-170
-180
20 20k50 100 200 500 1k 2k 5k 10k
Hz
-10
-20
-30
-40
-50
-60
-70
-80
d
B
-90
F
S
-100
-110
-120
-130
-140
-150
-160
-170
-180
20 20k50 100 200 500 1k 2k 5k 10k
Hz
Figure 12. -60 dB FFT, Single-Speed Mode Figure 13. -60 dB FFT, Double-Speed Mode
-10
-20
-30
-40
-50
-60
-70
-80
d
B
-90
F
S
-100
-110
-120
-130
-140
-150
-160
-170
-180
20 20k50 100 200 500 1k 2k 5k 10k
Hz
-10
-20
-30
-40
-50
-60
-70
-80
d
B
-90
F
S
-100
-110
-120
-130
-140
-150
-160
-170
-180
20 20k50 100 200 500 1k 2k 5k 10k
Hz
Figure 14. No Input FFT, Single-Speed Mode Figure 15. No Input FFT, Double-Speed Mode
DS700DB1 17
CDB53L21
80
80
80
+10
+10
-
-82
-84
-86
-88
-90
-92
-94
-96
-98
-100
20 20k50 100 200 500 1k 2k 5k 10k
Hz
-66
-68
-70
-72
-74
-76
-78
-80
d
B
-82
F
-84
S
-86
-88
-90
-92
-94
-96
-98
-100
20 20k50 100 200 500 1k 2k 5k 10k
Hz
Figure 16. THD+N vs. Frequency, Single-Speed Mode Figure 17. THD+N vs. Frequency, Double-Speed Mode
-
-82
-84
-86
-88
-90
-92
-94
-96
-98
-100
-120 -10-110 -100 -90 -80 -70 -60 -50 -40 -30 -20
dBr
-
-82
-84
-86
-88
d
B
-90
F
S
-92
-94
-96
-98
-100
-120 -20-100 -80 -60 -40
dBr
Figure 18. THD+N vs. Amplitude, Single-Sp eed Mode Figure 19. THD+N vs. Amplitude, Double-Speed Mode
TTTT
+8
+6
+4
+2
+0
-2
-4
-6
-8
-10
-140 +0-120 -100 -80 - 60 -40 -20
Figure 20. Fade-to-Noise Linearity, Single-Speed Mode Figure 21. Fade-to-Noise Linearity, Double-Speed Mode
dBr
TTTT
+8
+6
+4
+2
d
B
+0
F
S
-2
-4
-6
-8
-10
-140 +0-120 -100 -80 -60 -40 -20
dBr
18 DS700DB1
CDB53L21
+0
+0
+0
+0
F
i33
-0.2
-0.4
-0.6
-0.8
-1
-1.2
-1.4
-1.6
-1.8
-2
20 20k50 100 200 500 1k 2k 5k 10k
Hz
Figure 22. Frequency Response, Single-Speed Mode Figure 23. Frequency Response, Double-Speed Mod e
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
20 20k50 100 200 500 1k 2k 5k 10k
Figure 24. Channel Crosstalk, Single-Speed Mode Figure 25. Channel Crosstalk, Double-Speed Mode
Hz
-0.2
-0.4
-0.6
-0.8
d
B
-1
F
S
-1.2
-1.4
-1.6
-1.8
-2
20 20k50 100 200 500 1k 2k 5k 10k
-10
-20
-30
-40
d
-50
B
F
-60
S
-70
-80
-90
-100
-110
20 20k50 100 200 500 1k 2k 5k 10k
Hz
Hz
DS700DB1 19
5. SYSTEM CONNECTIONS AND JUMPERS
CONNECTOR REF INPUT/OUTPUT SIGNAL PRESENT
+5V J26 Input +5.0 V Power Supply.
GND J27 Input Ground Reference .
RS232 J95 Input/Output Serial connection to PC for SPI / I²C control port signals.
USB J94 Input/Output USB connection to PC for SPI / I²C control port signal.
S/PDIF OPTICAL
OUT
S/PDIF COAX OUT J68 Output CS8406 digital audio output via coaxial cable.
I/O Header J5 Input/Output I/O for Clocks & Data.
S/W CONTROL J109 Input/Output I/O for external SPI / I²C control port signals.
MICRO JTAG J1 10 Input/Output I/O for programming the micro controller (U84).
FPGA JTAG J78 Input/Output I/O for programming the FPGA (U14).
MICRO RESET S4 Input Reset for the micro controller (U84).
FPGA PROGRAM S2 Input Reload Xilinx Flash program into the FPGA (U14).
H/W BOARD RESET S1 Input Reset for the CS53L21 (U1).
LINEB
LINEA
MIC1
MIC2
OPT2 Output CS8406 digital audio o utput via optical cable.
J62
J7
J35
J51
Input RCA phono jacks for analog input signal to CS53L21.
Input Microphone jacks for analog input signal to CS53L21.
Table 3. System Connections
CDB53L21
20 DS700DB1
JMP LABEL PURPOSE POSITION FUNCTION SELECTED
J31 VL
J25 VA
J28 VD
J52
J47
J53
J2 LINEB MUX
J1 LINEA MUX
J3
J8
J14
J12 MIC2 Bias Selects bias for MIC2
VL
VA
VD
(AIN2B
Select)
(AIN3B
Select)
(AIN3A
Select)
Selects source of voltage for
the VL supply
Selects source of voltage for
the VA supply
Selects source of voltage for
the VD supply
Current Measurement
Selects signal source for the
ADC I/O
Selects signal source for the
ADC I/O
Selects signal source for MIC1
and MIC2 bias or signal source
for the ADC input
Selects signal source for MIC2
bias or signal source for the
ADC input
Selects signal source for the
ADC input
Table 4. Jumper Settings
*+1.8V Voltage source is +1.8 V regulator.
+2.5V Voltage source is +2.5 V regulator.
+3.3V Voltage source is +3.3 V regulator.
*+1.8V Voltage source is +1.8 V regulator.
+2.5V Voltage source is +2.5 V regulator. .
*+1.8V Voltage source is +1.8 V regulator.
+2.5V Voltage source is +2.5 V regulator. .
*SHUNTED 1 Ω series resistor is shorted.
OPEN
(AIN3B
Select)
(AIN2B
Select)
*AIN1B LINEB signal routed to AIN1B of ADC.
(AIN3A
Select)
AIN2A LINEA signal routed to AIN2A of ADC.
*AIN1A LINEA signal routed to AIN1A of ADC.
BIAS1 to
MIC2
BIAS1 to
MIC1
*LINEB LINEB MUX routed to AIN2B of ADC.
BIAS2 to
MIC2
MIC2 MIC2 signal routed to AIN3B of ADC.
*LINEB LINEB MUX routed to AIN3B of ADC.
MIC2 MIC2 signal routed to AIN3A of ADC.
MIC1 MIC1 signal routed to AIN3A of ADC.
*LINEA LINEA MUX routed to AIN3A of ADC.
BIAS1 J3 (for Bias on AIN2B of ADC) routed to MIC2.
BIAS2 J8 (for Bias on AIN3B of ADC) routed to MIC2.
*Not con-
nected
*Default factory settings
1 Ω series resistor in power supply path.
LINEB signal routed to jumper J8.
LINEB signal routed to jumper J3.
LINEA signal routed to jumper J14.
Bias on AIN2B of ADC routed to jumper J12.
Bias on AIN2B of ADC routed to MIC1.
Bias on AIN3B of ADC routed to jumper J12.
Jumper placed on pin 2.
CDB53L21
DS700DB1 21
22 DS700DB1
6. BLOCK DIAGRAM
Software Mode
Control Port
Hardware Mode
Switches
Figure 27 on page 23
I²C/SPI Header
Figure 27 on page 23
Figure 32 on page 28
S/PDIF Out
Figure 29
on page 25
Oscillator
Figure 31
on page 27
(CS8406)
(socket)
Reset
MCLK
Hardware Mode
Switches
Figure 30 on page 26
FPGA
Figure 30
on page 26
Reset
Clocks/Data Header
Figure 31 on page 27
MCLK
CS53L21
Figure 27 on page 23
Reset
Reset
Analog Input
Figure 28 on page 24
CDB53L21
Figure 26. Block Diagram
DS700DB1 23
7. SCHEMATICS
Figure 27. CS53L21 (Part of Schematic Sheet 1)
CDB53L21
24 DS700DB1
Figure 28. Analog I/O (Part of Schematic Sheet 1)
CDB53L21
DS700DB1 25
Figure 29. S/PDIF I/O (Schematic Sheet 2)
CDB53L21
26 DS700DB1
Figure 30. FPGA (Schematic Sheet 3)
CDB53L21
DS700DB1 27
Figure 31. Level Shifters & I/O Stake Header (Schematic Sheet 4)
CDB53L21
28 DS700DB1
Figure 32. Control Port I/O (Schematic Sheet 5)
CDB53L21
DS700DB1 29
Figure 33. Power (Schematic Sheet 6)lm
CDB53L21
30 DS700DB1
8. BOARD LAYOUT
CDB53L21
CS53L21
Figure 34. Silk Screen
CS53L21
CS53L21
CDB53L21
DS700DB1 31
Figure 35. Top-Side Layer
CDB53L21
32 DS700DB1
Figure 36. Bottom-Side Layer
CDB53L21
9. REVISION HISTORY
Revision Changes
DB1 Initial Release
CDB53L21
Contacting Cirrus Logic Support
For all product questions and inquiries, contact a Cirrus Logic Sales Representative.
To find the one nearest to you, go to www.cirrus.com
IMPORTANT NOTICE
Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject
to change without not ice and is pr ovided "AS IS" witho ut warr anty of any kind (express or implied). Customers are advised to obtain the latest version of relevant
information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale
supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus
for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third
parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights,
copyrights, trademarks, trade secrets or other inte llectual property rig hts. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent
does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE
IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED,
INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT
THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL
APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, T O FULLY INDEMNIF Y CIRRUS, ITS OF FICE RS, DI RECTORS, EMPLOYEES, DISTRI BUTORS AND
OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION
WITH THESE USES.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks
or service marks of their respective owners.
I²C is a registered trademark of Philips Semiconductor.
SPI is a trademark of Motorola, Inc.
Windows
is a registered trademark of Microsoft Corporation.
DS700DB1 33
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