Cirrus Logic CDB53L21 User Manual

Evaluation Board for CS53L21

CDB53L21

Features

 Selectable Analog Inputs

– Stereo Line-Level RCA Jacks – Stereo Microphone 1/8” Jacks

 Stereo Microphone Input Jacks  8- to 96-kHz S/PDIF Output

– CS8406 Digital Audio Transmitter

 I/O Stake Headers

– External Control Port Accessibility – External DSP Serial Audio I/O Accessibility

 Independent, Regulated Supplies  1.8 V to 3.3 V Logic Interface  Hardware Control

– 4 Pre-Defined Switch Settings

 FlexGUI S/W Control - Windows

– Pre-Defined & User-Configurable Scripts

Compatible

Description

The CDB53L21 evaluation board is an excellent means for evaluating the CS53L21 ADC. Evaluation requires an analog audio source, an analog/digital analyzer and power supplies. Optionally, a Windows computer may be used to evaluate the CS53L21 in Software Mode.

System timing can be provided by the CS53L21 with supplied master clock, or by using an I/O stake header with a DSP connected.

RCA phono jacks are provided for the CS53L21 analog inputs. 1/8” jacks are also available for microphone inputs. A digital data output is available from the CS8406 via RCA phono or optical connectors.

The Windows software provides a GUI to make configuration of the CDB53L21 easy. The software communicates through the PC’s serial port or USB port to configure the control port registers so that all features of the CS53L21 can be evaluated. The evaluation board may also be configured to accept external timing and data signals for operation in a user application during system development.

PC-compatible

 Layout and Grounding Recommendations

Software Mode

Control Port

Reset

Hardware Mode

Switches

S/PDIF Output

(CS8406)

FPGA

Reset

MCLK

Oscillator

(socket)

ORDERING INFORMATION

CDB53L21 Evaluation Board

I²C/SPI Header

MCLK

Reset

Clocks/Data Header

Reset

CS53L21

Analog Input (Line or MIC)

http://www.cirrus.com

MARCH '06

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TABLE OF CONTENTS

1. SYSTEM OVERVIEW ............................................................................................................................. 4

1.1 Power ............................................................................................................................................... 4

1.2 Grounding and Power Supply Decoupling ...................... ... .... ... ... ... ... .... ........................................... 4

1.3 FPGA ................................................................................................................................................ 4

1.4 CS53L21 Audio A to D Converter ..................................................................................................... 4

1.5 CS8406 Digital Audio Transmitter ............... ... ... ... .... ........................................................................ 5

1.6 Oscillator ........................................................................................................................................... 5

1.7 I/O Stake Headers ............................................................................................................................ 5

1.8 Analog Input ..................................................................................................................................... 5

1.9 Stand-Alone Switches ...................................................................................................................... 6

1.10 Control Port Connectors ................................................................................................................. 6

1.10.1 RS-232 and USB Connectors ...............................................................................................6

2. SOFTWARE MODE CONTROL ............................................................................................................. 7

2.1 General Configuration Tab ............................................................................................................... 8

2.2 ADC Configuration Tab .................................................................................................................... 9

2.3 ADC Volume Controls Tab ............................................................................................................. 10

2.4 Mix Volume Controls Tab ............................................................................................................... 11

2.5 Register Maps Tab ......................................................................................................................... 12

3. HARDWARE MODE CONTROL .......................................................................................................... 13

3.1 FPGA H/W Control ......................................................................................................................... 13

3.2 CS53L21 H/W Control .................................................................................................................... 16

4. PERFORMANCE PLOTS ..................................................................................................................... 17

5. SYSTEM CONNECTIONS AND JUMPERS ........................................................................................ 20

6. BLOCK DIAGRAM ............................................................................................................................... 22

7. SCHEMATICS ...................................................................................................................................... 23

8. BOARD LAYOUT ................................................................................................................................. 30

9. REVISION HISTORY ............................................................................................................................ 33

CDB53L21

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LIST OF FIGURES

Figure 1.General Configuration Tab ............................................................................................................ 8

Figure 2.ADC Configuration Tab ................................................................................................................. 9

Figure 3.ADC Volume Controls Tab .......................................................................................................... 10

Figure 4.Mix Volume Controls Tab ............................................................................................................ 11

Figure 5.Register Maps Tab - CS53L21 ................................................................................................... 12

Figure 6.Routing 4 ..................................................................................................................................... 14

Figure 7.Routing 6 ..................................................................................................................................... 14

Figure 8.Routing 8 ..................................................................................................................................... 15

Figure 9.Routing 10 ................................................................................................................................... 15

Figure 10.0 dB FFT, Single-Speed Mode ........................................... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ......... 17

Figure 11.0 dB FFT, Double-Speed Mode ... ... ... .... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... .... ............ 17

Figure 12.-60 dB FFT, Single-Speed Mode ................................. .... ... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ......... 17

Figure 13.-60 dB FFT, Double-Speed Mode ... ... .... ... ... .......................................... ................................... 17

Figure 14.No Input FFT, Single-Speed Mode ........................................................................................... 17

Figure 15.No Input FFT, Double-Speed Mode .......................... ... .... ......................................................... 17

Figure 16.THD+N vs. Frequency, Single-Speed Mode ............................................................................. 18

Figure 17.THD+N vs. Frequency, Double-Speed Mode ..................... ... ... ... .... ... ... ... .... ............................ 18

Figure 18.THD+N vs. Amplitude, Single-Speed Mode .............................................................................. 18

Figure 19.THD+N vs. Amplitude, Double-Speed Mode ............................................................................ 18

Figure 20.Fade-to-Noise Linearity, Single-Speed Mode ...........................................................................18

Figure 21.Fade-to-Noise Linearity, Double-Speed Mode .......................................................................... 18

Figure 22.Frequency Response, Single-Speed Mode .............................................................................. 19

Figure 23.Frequency Response, Double-Speed Mode ............................. ... .... ... ...................................... 19

Figure 24.Channel Crosstalk, Single-Speed Mode ................................................................................... 19

Figure 25.Channel Crosstalk, Double-Speed Mode .................................................................................. 19

Figure 26.Block Diagram ........................................................................................................................... 22

Figure 27.CS53L21 (Part of Schematic Sheet 1) ...................................................................................... 23

Figure 28.Analog I/O (Part of Schematic Sheet 1) .................................................................................... 24

Figure 29.S/PDIF I/O (Schematic Sheet 2) ............................................................................................... 25

Figure 30.FPGA (Schematic Sheet 3) ....................................................................................................... 26

Figure 31.Level Shifters & I/O Stake Header (Schematic Sheet 4) .......................................................... 27

Figure 32.Control Port I/O (Schematic Sheet 5) ....................................................................................... 28

Figure 33.Power (Schematic Sheet 6)lm .................................................................................................. 29

Figure 34.Silk Screen ................................................................................................................................ 30

Figure 35.Top-Side Layer ......................................................................................................................... 31

Figure 36.Bottom-Side Layer .................................................................................................................... 32

CDB53L21

LIST OF TABLES

Table 1. MCLK and Clock/Data Routing Options ...................................................................................... 13

Table 2. CS53L21 H/W Mode Control .......................... ... .......................................... ................................ 16

Table 3. System Connections ................ ... ... ... ... .... ...................................... .... ... ... ... .... ... ... ... ................... 20

Table 4. Jumper Settings ................... .... ... ... ... ... .... ... ....................................... ... ... ... .... ... ... ...................... 21

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CDB53L21

1. SYSTEM OVERVIEW

The CDB53L21 evaluation board is an excellent means for evaluating the CS53L21 ADC. Digital audio signal outputs are provided, and an FPGA is used for easily configuring the board. Section 2. “Software Mode Control” on

page 7 and Section 3. “Hardware Mode Control” on page 13 provide configuration details.

The CDB53L21 schematic set has been partitioned into seven pages and is sh own in Figures 27 through 33. “Sys-

tem Connections and Jumpers” on page 20 provides a description of all stake headers and connectors, including

the default factory settings for all jumpers.

1.1 Power

Power is supplied to the evaluation board through the +5.0 V binding posts. Jumpers connect the ADC’s supplies to a regulated voltage of +1.8 V, 2.5 V or +3.3 V for VL and +1.8 V or 2.5 V for VD and VA. All voltage inputs must be referenced to the black binding post ground connector.

For current measurement purposes only, a series resistor is connected to each supply. The current is easily calculated by measuring the voltage drop across this resistor. NOTE: The stake headers connected in parallel with these resistors must be shunted with the supplied jumper during normal operation.

WARNING: Please refer to the CS53L21 data sheet for allowable voltage levels.

1.2 Grounding and Power Supply Decoupling

The CS53L21 requires careful attention to power supply and grounding arrangements to optimize performance. The CDB53L21 demonstrates these optimal arrangements. Figure 26 on page 22 provides an overview of the connections to the CS53L21. Figure 34 on pag e 30 shows the com ponent pla cement, Figur e 35

on page 31 shows the top layout, and Figure 36 on page 32 shows the bottom layout. The decoupling ca-

pacitors are located as close to the CS53L21 as possible. Extensive use of ground plane fill in the evaluation board yields large reductions in radiated noise.

1.3 FPGA

The FPGA provides digital signal routing between the CS53L21, CS8406 and the I/O stake header. It also configures the Hardware Mode options of the CS8406 and provides routing control of the system master clock from an on-board oscillator and the I/O stake header. The Cirrus FlexGUI software and “FPGA H/W Control” switches provide full control of the FPGA’s routing and configuration options. Section 2. “Software

Mode Control” on page 7 and Section 3. “Hardware Mode Control” on page 13 provide configuration details.

1.4 CS53L21 Audio A to D Converter

A complete description of the CS53L21 (Figure 27 on page 23) is included in the CS53L21 product data sheet.

The CS53L21 may be configured using either the Cirrus FlexGUI or the on-board “CS53L21 H/W Control” switches. The Software Mode control port registers are accessible through the “Register Maps” tab of the Cirrus FlexGUI software. This tab provides low-level control of each bit. For easier configuration, additional tabs provide high-level control. The Hardware Mode, stand-alone controls for the CS53L21 are accessible through the on-board, stand-alone switches, “CS53L21 H/W Control.”

Clock and data source selections are made in the cont rol port of the FPGA, accessible through the “Gene ral Configurations” tab of the C irr us FlexGUI software or throu gh t he on-board “FPGA H/W Control” switches.

Section 2. “Software Mode Control” on page 7 and Section 3. “Hardware Mode Control” on page 13 provide

configuration details.

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1.5 CS8406 Digital Audio Transmitter

A complete description of the CS8406 transmitter ( Figure 29 on page 25 ) and a discussion of the d igital audio interface are included in the CS8406 data sheet.

The CS8406 converts the PCM data generated by the CS53L21 to the standard S/PDIF data stream and routes this signal to the optical and RCA connectors. The CS8406 operates in slave mode only, accepting either a 128xFs or 256xFs master clock, and can operate in eithe r the Left-Justified or I²S inte rface format.

Selections are made in the control port of the FPGA, accessible through the “General Configurations” tab of the Cirrus FlexGUI software or through the on-boa rd switches, “FPGA H/W Control.” Section 2. “Software

Mode Control” on page 7 and Section 3. “Hardware Mode Control” on page 13 provide configuration details.

1.6 Oscillator

The on-board oscillator provides one of the system master clocks. Selections are made in the control port of the FPGA, accessible through the “General Configurations” tab of the Cirrus FlexGUI software or through the on-board switches, “FPGA H/W Control.” Section 2. “Software Mode Control” on page 7 and Section 3.

“Hardware Mode Control” on page 13 provide configuration details.

The oscillator is mounted in pin sockets, allowing easy removal or replacement. Additional sockets are also installed, allowing the optional use of a full- or half-can-sized oscillator.

1.7 I/O Stake Headers

CDB53L21

The evaluation board has been designed to allow interfacing with external systems via a se rial port hea der (reference designation J5) and a control port header, “CS53L21 S/W Control.” The serial port header provides access to the serial audio signals required to interface with a DSP (Figure 31 on page 27). Selections are made in the control port of the FPGA, accessible through the “ General Configur ations” tab of the Cirrus FlexGUI software or through the on-board switches, “FPGA H/W Control.” Section 2. “Software Mode Con-

trol” on page 7 and Section 3. “Hardware Mode Control” on page 13 provide configuration details.

The control port header provides bidirectional access to the SPI™/I²C moving all the shunt jumpers from the “PC” position. The user may then choose to connect a ribbon cable to the “CONTROL” position, allowing operation of the CS53L21 in a user-application for system development. A single “GND” row for the ribbon cable’s ground connection is provided to maintain signal integrity. Two unpopulated pull-up resistors are also available should the user choose to use the CDB for the I²C power rail.

1.8 Analog Input

RCA connectors supply the line-level analog inputs through an AC-coupled passive filter. The signal from these inputs may be driven to individual inputs or to all inputs of the CS53L21. A microphone may be connected to one or both of the 1/8” jacks, MIC1 and MIC2.

To accommodate the microphone bias output available on certain input pins of the CS53L21, additional stake headers are provided to MUX both the input audio signal and the output bias signal to or from the CS53L21. Figure 28 on page 24 in the schematic set illustrates how signals are routed. Table 4 on page 21 provides more details for how to connect the jumpers. The CS53L21 data sheet details the required singleended signal amplitude that will drive the inputs to full scale.

control port signals by simp ly re-

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1.9 Stand-Alone Switches

The “FPGA H/W Control” and “CS53L21 H/W Control” switches control all Hardware Mode options.

Section 3. “Hardware Mode Control” on page 13 provides a description of each topology.

1.10 Control Port Connectors

A graphical user interface is available for the CDB53L21, allowing easy ma nipulation of ea ch registe r. This GUI interfaces with the CDB via the RS-232 or USB connectors and controls all Software Mode options.

Section 2. “Software Mode Control” on page 7 provides a description of the Graphical User Interface (GUI).

1.10.1 RS-232 and USB Connectors

Connecting a cable to the R S-232 connector or the USB 1.0/2.0 connector and launching the Cirrus FlexGUI software enables the CDB53L21 in Software Mode.

CDB53L21

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CDB53L21

2. SOFTWARE MODE CONTROL

The CDB53L21 may be used with the Microsoft Windows-based FlexGUI graphical user interface, allowing software control of the CS53L21 and FPGA registers. The latest control software may be downloaded from

www.cirrus.com/msasoftware. Step-by-step instructions for setting up the FlexGUI are provided as follows :

1. Download and install the FlexGUI software as instructed on the Website.

2. Connect and apply power to the +5.0 V binding post.

3. Connect the CDB to the host PC using either a 9-pin serial or USB cable .

4. Launch the Cirrus FlexGUI. Once the GUI is launched successfully, all registers are set to their default reset

state.

5. Enable the CS53L21 by engaging the “Enable CS53L21” push button.

6. Refresh the GUI by clicking on the “Update” button. The default state of all registers are now visible.

7. Engage and then disengage the “Power Down” push button in the “ADC Basic Configurations” group. This performs the necessary write sequence to the CS53L21 for Software Mode operation.

For standard setup:

8. Set up the signal routing in the “General Configurations” tab as desired.

9. Set up the CS53L21 in the “ADC Configuration”, “ADC Volume Controls” or “Mix Volume Controls” tab as desired.

10. Begin evaluating the CS53L21.

For quick setup, the CDB53L21 may, alternatively, be configured by loading a predefined sample script file:

11. On the File menu, click "Restore Board Registers..."

12. Browse to Boards\CDB53L21\Scr ipt s\.

13. Choose any one of the provided scripts to begin evaluation.

To create personal scripts files:

14. On the File menu, click "Save Board Registers..."

15. Enter any name that sufficiently describes the created setup.

16. Choose the desired location and save the script.

17. To load this script, follow the instructions from step 11 above.

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2.1 General Configuration Tab

The “General Configuration” tab provides high-level control of signal routing on the CDB53L21. This tab also includes basic controls for the CS53L21 for quickly setting up the CDB53L21 in simp le config urations. Status text detailing the ADC’s specific configuration is shown in parenthesis or appears directly below the associated control. This text may change depending on the setting of the associated control. A description of each control group is outlined below:

ADC Basic Configuration - Includes basic register controls in the CS53L21 used for setting up the interface format, clocking functions and internal analog input routing. See Section 2.2 through Section 2.4 for more CS53L21 controls.

S/PDIF Transmitter Control - Includes all available Hardware Mode controls for setting up the CS8406. Clock/Data Routing and ADC Reset - Includes controls used for routing clocks and data between the

CS53L21, oscillator and the I/O stake header. Also included is a reset control for the CS53L21.

Update - Reads all registers in the FPGA and CS53L21 and reflects the current values in the GUI. Reset - Resets FPGA to default routing configuration.

CDB53L21

Figure 1. General Configuration Tab

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2.2 ADC Configuration Tab

The “ADC Configuration” tab provides high-level control of all setu p configurations fo r the CS53L21. Status text detailing the ADC’s specific configuration is shown in parenthesis or app ears directly below the associated control. This text will change depending on the setting of the associated control. A description of each control group is outlined below (a description of each register is included in the CS53L21 data sheet):

Power Control - Includes all register controls for powering down specific circuits within the CS53L21. ADC input Configuration - Includes controls for the internal MUX, analog input, microphon e bias output an d

channel mix. Serial Port Configuration - Includes controls for all settings related to the transmission and relationship of

data and clocks within the CS53L21.

Update - Reads all registers in the CS53L21 and reflects the current values in the GUI. Reset - Resets the CS53L21.

CDB53L21

Figure 2. ADC Configuration Tab

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2.3 ADC Volume Controls Tab

The “ADC Volume Controls” tab provides high-level control of all volume settings in the ADC of the CS53L21. Status text detailing the ADC’s specific configuration is shown in parenthesis or inside the control group of the affected control. This text will change depending on the setting of the associated control. A description of each control group is outlined below (a description of each register is included in the CS53L21 data sheet):

Digital Volume Control - Includes digital volume controls and adjustments for the ADC. ALC Configuration - Includes all configuration settings for the Automatic Level Control (ALC). Analog Volume Control - Includes all analog volume controls and adjustments for the ADC. Noise Gate Configuration - Includes all configuration settings for the noise gate. Update - Reads all registers in the CS53L21 and reflects the current values in the GUI. Reset - Resets the CS53L21.

CDB53L21

Figure 3. ADC Volume Controls Tab

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