Cirrus Logic CDB5381 User Manual
Evaluation Board for CS5381
CDB5381
Features
Demonstrates recommended layout and
grounding arrangements
CS8406 generates S/PDIF, and EIAJ-340
compatible digital audio
Requires only an analog signal source and
power supplies for a complete Analog-toDigital-Converter system
Description
The CDB5381 evaluation board is an excellent means
for quickly evaluating the CS5381 24-bit, stereo A/D converter. Evaluation requires a digital signal analyzer, an
analog signal source, and a power supply.
Also included is a CS8406 digital audio interface transmitter which generates S/PDIF, and EIAJ-340
compatible audio data. The digital audio data is available
via RCA phono and optical connectors.
ORDERING INFORMATION
CDB5381 Evaluation Board
ANALOG
INPUT
Cirrus Logic, Inc.
www.cirrus.com
CS5381
TRA N SMITTER
I/O FOR
CLOCKS
AND DATA
CopyrightCirrus Logic, Inc. 2003
(All Rights Reserved)
CS8406
AES/EBU
S/PDIF
S/PDIF
OUTPUT
FEB ‘03
DS563DB1
1
TABLE OF CONTENTS
1. CDB5381 SYSTEM OVERVIEW .............................................................................................. 3
2. CS8406 DIGITAL AUDIO TRANSMITTER ...............................................................................3
3. INPUT/OUTPUT FOR CLOCKS AND DATA ...........................................................................3
4. POWER SUPPLY CIRCUITRY ................................................................................................. 3
5. GROUNDING AND POWER SUPPLY DECOUPLING ............................................................ 3
6. ANALOG INPUT FILTER ......................................................................................................... 3
LIST OF FIGURES
Figure 1. System Block Diagram and Signal Flow .......................................................................... 5
Figure 2. Differential Analog Audio Input......................................................................................... 6
Figure 3. CS5381 ............................................................................................................................ 7
Figure 4. Level Shifters ................................................................................................................... 8
Figure 5. I/O for Clocks/Data........................................................................................................... 9
Figure 6. CS8406 Digital Audio Interface ........................................................................................ 9
Figure 7. Reset Circuit................................................................................................................... 10
Figure 8. Power Circuit.................................................................................................................. 11
Figure 9. Top Layer Silkscreen ..................................................................................................... 12
Figure 10. Top Layer .....................................................................................................................13
Figure 11. Bottom Layer................................................................................................................ 14
CDB5381
LIST OF TABLES
Table 1. System Connections ........................................................................................................4
Table 2. CDB5381 Jumper and Switch Settings ............................................................................ 4
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find one nearest you go to
IMPORTANT NOTICE
“Preliminary” product information describes products that are in producti on, but for which full characterization data is not yet available. “Advance” product information
describes products that are i n development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “ AS IS” without warranty of any kind
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www.cirrus.com
2 DS563DB1
CDB5381
1. CDB5381 SYSTEM OVERVIEW
The CDB5381 evaluation board is an excellent means of quickly evaluating the CS5381. The
CS8406 digital audio interface transmitter provides an easy interface to digital audio signal analyzers including the majority of digital audio test equipment.
The CDB5381 schematic has been partitioned into 7 schematics shown in Figure 2 through
Figure 8. Each partitioned schematic is represented in the system diagram shown in Figure 1.
Notice that the system diagram also includes the interconnections between the partitioned schematics.
2. CS8406 DIGITAL AUDIO TRANSMITTER
The system generates and encodes standard S/PDIF data using a CS8406 Digital Audio Transmitter (see Figure 6). The outputs of the CS8406 are RS422 compatible differential line drivers.
2
The CS8406 supports both Left Justified and I
S2. A description of the CS8406 is included in the CS8406 datasheet.
3. INPUT/OUTPUT FOR CLOCKS AND DATA
The evaluation board has been designed to allow interfacing to external systems via the 10-pin
header, J13. The schematic for the clock/data input/output is shown in Figure 5.
S data formats, as determined by the DIP switch,
The CDB5381 allows some flexibility as to the generation of the clocks. When the CS5381 and
CS8406 are in slave mode, the SCLK and LRCK must be provided via the header, J13. MCLK
must be generated from the on board oscillator, Y1. This oscillator is socketed to allow other frequency oscillators to be used.
4. POWER SUPPLY CIRCUITRY
Power is supplied to the evaluation board by six binding posts (-12 V, +12 V, VD, VL, GND,
+5 V), see Figure 8. -12 V and +12 V supply the input amplifiers while the VD input supplies the
VD pin of the CS5381. VL supplies power to the VL pin of the CS5381 and to the level shifter
circuits. The +5 V input supplies power to the +5 V digital circuitry and the VA pin of the CS5381.
5. GROUNDING AND POWER SUPPLY DECOUPLING
The CS5381 requires careful attention to power supply and grounding arrangements to optimize
performance. Figure 3 details the power distribution used on this board. The decoupling capacitors are located as close to the CS5381 as possible. Extensive use of ground plane fill in the
evaluation board yields large reductions in radiated noise.
6. ANALOG INPUT FILTER
The CDB5381 implements a fully differential analog input buffer, as shown in Figure 2. Note that
there is no attenuation associated with the input buffer, so a 2 Vrms differential input applied at
the XLR connectors will provide a full-scale 2 Vrms differential input to the CS5381.
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CDB5381
CONNECTOR INPUT/OUTPUT SIGNAL PRESENT
-12 V Input -12 V power for the input op-amps
+12 V Input +12 V power for the input op-amps
VD Input +3.3 V to +5 V power for the CS5381
VL Input +2.5 V to +5 V power for the CS5381
GND Input Ground connection from power supply
+5 V Input + 5 Volt power
AINL Input Differential analog input left channel
AINR Input Differential analog input right channel
Optical Output Output Digital audio output
Coax Output Output Digital audio output
Table 1. System Connections
JUMPER/SWITCH PURPOSE POSITION FUNCTION SELECTED
J7 VD Power Source ADJ
*+3.3 V
+5 V
J8 VL Power Source ADJ
*+3.3 V
+5 V
J13 Input/Output for
clocks/data
S1 Reset for the CDB5381 - -
S2 CDB5381 Configuration M1/M0 Open
--
*ClosedHiLow
ADC *Open
Closed
HPF
DIV Open
IO_HDR Open
DIF Open
8406 Open
Open
*Closed
*Closed
*Closed
*Closed
*Closed
Power from the Binding Post (J3)
Power from the +3.3 V Regulator
Power from the +5V Supply
Power from the Binding Post (J4)
Power from the +3.3 V Regulator
Power from the +5 V Supply
CS5381 in Master mode
CS5381 in Slave mode
High-pass filter is disabled
High-pass filter is enabled
MCLK is divided by two internally by the
CS5381
MCLK is not divided internally by the
CS5381
Header J3 is an input for clocks
Header J3 is an output for clocks and
data
Digital interface format set to I
Digital interface format set to Left Justified
CS8406 in Master mode
CS8406 in Slave mode
2
S
Table 2. CDB5381 Jumper and Switch Settings
* denotes default factory settings
4 DS563DB1
CDB5381
R
O
T
A
7
L
L
I
G
I
C
F
S
AUDIO
CS8406
DIGITAL
FIG 6
INTERFACE
CRYSTAL
O
RESET
CIRCUIT
FIG 7
I/O FOR
FIG 4
LEVEL
SHIFTER
3
G
I
CS5381
F
T
L
U
A
I
P
T
N
I
N
E
G
2
R
O
G
E
L
I
F
A
F
F
I
N
A
D
FIG 5
CLOCKS
AND DATA
Figure 1. System Block Diagram and Signal Flow
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