Cirrus Logic CDB5378 User Manual
CDB5378
Single-channel Seismic Evaluation System
Features
z Single-channel Seismic Acquisition Node
– CS3301A geophone amplifier
– CS5373A ∆Σ modulator + test DAC
– CS5378 digital filter + PLL
– Precision voltage reference
z On-board Microcontroller
– SPI™ interface to digital filter
– USB communication with PC
z PC Evaluation Software
– Register setup & control
– FFT frequency analysis
– Time domain analysis
– Noise histogram analysis
General Description
The CDB5378 board is used to evaluate the functionality
and performance of the Cirrus Logic single-channel se ismic chip set. Data sheets for the CS3301A, CS5373A,
and CS5378 devices should be consulted when using
the CDB5378 evaluation board.
Screw terminals connect an external differential geophone or hydrophone sensor to the analog inputs of the
measurement channel. An on-board test DAC creates
precision differential analog signals for in-circuit performance testing without an external signal source.
The evaluation board includes an 8051-type microcontroller with hardware SPI™ and USB serial interfaces.
The microcontroller communic ates with the digital filter
via SPI and with the PC evaluation software via USB.
The PC software controls register and coefficient initialization and performs time domain, histogram, and FFT
frequency analysis on captured data.
ORDERING INFORMATION
CDB5378 Evaluation Board
www.cirrus.com
Copyright © Cirrus Logic, Inc. 2007
(All Rights Reserved)
NOV ‘07
DS639DB4
CDB5378
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find the one nearest to you go to www.cirrus.com
IMPORTANT NOTICE
Cirrus Logic, Inc. and its subsidiaries ("Cirru s") b eli eve that the information contained in this document is accurate and reli a b le. However, the information is subjec t
to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant
information to verify, before placing orders, tha t inform ation be ing reli ed on is current an d com plete. A ll prod ucts are sold subj ect to the term s and conditions of sale
supplied at the time of order ackno wledgment, inclu ding those pertaining to warranty, indemn ification, and limitatio n of liability. No responsibility is assumed by Cirrus
for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third
parties. This document is the prop erty o f C irrus a nd by furn ishing this inform ation, Cirru s grants no lice nse, expres s or implied under any patents, mask work rights,
copyrights, trade marks, trade secrets or o ther int ellectual p roperty ri ghts. Cirrus owns the copyr ights ass ociated with t he inf ormation contained herein and gives
consent for copies to be made of the inform ation only for u se withi n your orga nization w ith resp ect to Cirrus integr ated circ uits or other p rodu cts of C irrus. This co nsent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR
USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK
AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER
OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE,
TO FULLY INDEMNI FY CIRRUS , ITS O FFICERS , DIRECT ORS, EMPL OYEES, DIST RIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILI TY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks
or service marks of their respective owners.
Windows is a registered trademark of Microsoft Corporation.
SPI is a trademark of Motorola, Inc.
2
C is a registered trademark of Philips Semiconductor Corporation.
I
USBXpress is a registered trademark of Silicon Laboratories, Inc.
2 DS639DB4
TABLE OF CONTENTS
1. INITIAL SETUP ......................................................................................................................... 5
1.1 Kit Contents ..................................... ....................................... ... ... ... .... .............................. 5
1.2 Hardware Setup ............................... ....................... ...................... ....................... .............. 5
1.2.1 Default Jumper Settings ................................... ....................................... ... ... .... . 6
1.2.2 Default DIP Switch Settings ............................................... .... ... ... ........................ 8
1.3 Software Setup .......................................... ... ....................................... ... ... ... ..................... 9
1.3.1 PC Requirements ............................. ....................................... ... ... ... .... ................. 9
1.3.2 Seismic Evaluation Software Installation .............................................................. 9
1.3.3 USBXpress Driver Installation ............................................................................... 9
1.3.4 Launching the Seismic Evaluation Software .............................. ......................... 10
1.4 Self-testing CDB5378 ............................ .... ... ... ... .... ... ....................................... ... ... ... ...... 11
1.4.1 Noise test ..... .... ... ... ... .... ...................................... .... ... ... ...................................... 11
1.4.2 Distortion Test .. ...................................... .... ... ... ... ....................................... ... ... ... 12
2. HARDWARE DESCRIPTION ................................................................................................. 13
2.1 Block Diagram ................................................................................................................ 13
2.2 Analog Hardware ....................... ... ... ... ... .... ...................................... .... ... ... ...................... 14
2.2.1 Analog Inputs ...... ... ... .... ... ... ....................................... ... ... ... ................................ 14
2.2.2 Differential Amplifiers ................................................. ... ... ... .... ............................ 17
2.2.3 Delta-Sigma Modulator ....................................................................................... 18
2.2.4 Delta-Sigma Test DAC ............................... ...................................... .... ... ... ... ...... 19
2.2.5 Voltage Reference .................... ....................................... ... .... ... ... ...................... 20
2.3 Digital Hardware .............................................................................................................. 20
2.3.1 Digital Filter ................................................ ... ... ... ....................................... ... ... ... 20
2.3.2 Interface CPLD ............................................................. ... ... .... ... ... ...................... 23
2.3.3 Digital Control Signals ......................... ....................................... ... ... .... ... ............ 25
2.3.4 Microcontroller ................................................. ... .... ... ... ... ... .... ............................ 25
2.3.5 RS-485 Telemetry ............................................................................................... 27
2.3.6 UART Connection .. ... .... ... ... ... ....................................... ... ... .... ............................ 29
2.3.7 External Connector .......................... ... ....................................... ... ... .... ... ............ 30
2.4 Power Supplies ................ ....................................... ... ... ... .... ...................................... ...... 30
2.4.1 Analog Voltage Regulators ................. ... .... ... ....................................... ... ... ... ...... 30
2.4.2 Digital Voltage Regulators .................................................................................. 31
2.5 PCB Layout ............................................... ... ... ... .... ...................................... .... ... ... ... ...... 32
2.5.1 Layer Stack ...... ... ... ... .... ... ....................................... ... ... ... ................................... 32
2.5.2 Differential Pairs ............................ ... ....................................... ... ... ... .... ............... 32
2.5.3 Bypass Capacitors ..................................... ... ... ... .... ...................................... ... ... 33
2.5.4 Dual-row Headers .. ... .... ... ....................................... ... ... ... ... ................................ 34
3. SOFTWARE DESCRIPTION .................................................................................................. 35
3.1 Menu Bar ......................................... ... ....................................... ... ... .... ... ......................... 35
3.2 About Panel ..................................................................................................................... 36
3.3 Setup Panel ..................................................................................................................... 37
3.3.1 USB Port ...... .... ... ... ... ....................................... ... .... ... ... ...................................... 38
3.3.2 Digital Filter ................................................ ... ... ... ....................................... ... ... ... 39
3.3.3 Analog Front End ...... .... ... ... ... ... ....................................... ... .... ... ......................... 40
3.3.4 Test Bit Stream ......................... .... ...................................... .... ... ... ... ................... 41
3.3.5 Gain / Offset .................................. ... ... ... ....................................... ... .... ... ... ......... 42
3.3.6 Data Capture .......................... ....................................... ... ... .... ... ......................... 43
3.3.7 External Macros ..... ... .... ... ... ... ....................................... ... ... .... ............................ 44
3.4 Analysis Panel ................................................................................................................. 45
3.4.1 Test Select ... .... ... ... ... ....................................... ... .... ... ... ...................................... 46
3.4.2 Statistics ........................ ... ... ... ... .... ... ... ... ....................................... ... .... ... ... ... ...... 47
CDB5378
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CDB5378
3.4.3 Plot Enable ............................. ... .... ... ... ... ....................................... ... .... ... ............47
3.4.4 Cursor ................................................. ... .... ... ... ... ....................................... ... ... ... 47
3.4.5 Zoom ............................................. ... ... ... ....................................... ... .... ... ............48
3.4.6 Refresh ...................... ....................................... ... .... ... ... ...................................... 48
3.4.7 Harmonics ........................................... ... ....................................... ... .... ... ... .........48
3.4.8 Spot Noise .............. ... .... ... ... ... ... .... ...................................... .... ... ... ... ...................48
3.4.9 Plot Error ............................................. ... .... ... ....................................... ... ... ... ... ... 48
3.5
Control Panel ....................................................... ... ... ... .... ...................................... ... ... 49
3.5.1 DF Registers ............. ....................................... ... .... ... ... ...................................... 50
3.5.2 DF Commands ........................................... ... ....................................... ... ... ... ... ... 50
3.5.3 SPI ................................................... ... ... .... ... ... ....................................... ... ... ... ...50
3.5.4 Macros ................................................ ... .... ... ... ....................................... ... ... ... ... 51
3.5.5 GPIO ............ .... ...................................... .... ... ... ... ....................................... ... ... ... 51
3.5.6 Customize ........... ....................................... ... ... ... .... ...................................... ... ... 52
3.5.7 External Macros ............... ... ....................................... ... ... ... .... ............................ 52
4. BILL OF MATERIALS ........................................................................................................... 53
5. LAYER PLOTS ...................................................................................................................... 56
6. SCHEMATICS ........................................................................................................................ 62
7. REVISION HISTORY ..............................................................................................................72
4 DS639DB4
LIST OF FIGURES
Figure 1. CDB5378 Block Diagram............................................................................................... 13
Figure 2. Quad Group Routing of RC Filter Components ............................................................. 18
Figure 3. CPLD Default Signal Assignments ................................................................................ 24
Figure 4. Differential Pair Routing................................................................................................. 32
Figure 5. Quad Group Routing...................................................................................................... 33
Figure 6. Bypass Capacitor Placement......................................................................................... 33
Figure 7. Dual-row Headers with Shorts....................................................................................... 34
CDB5378
DS639DB4 5
LIST OF TABLES
Table 1. Analog Input Default Jumper Settings...............................................................................6
Table 2. RESET, SPI, SYNC Default Jumper Settings ................................................................... 6
Table 3. VREF, Power Supplies Default Jumper Settings .............................................................. 7
Table 4. Clock Default Jumper Settings............................................... ... ... ... .... ... ... ... .....................7
Table 5. RS-485 Default Jumper Settings.......................................................................................8
Table 6. DIP Switch Default Settings ..............................................................................................8
Table 7. Screw Terminal Input Connectors...................................................................................14
CDB5378
6 DS639DB4
1. INITIAL SETUP
1.1 Kit Contents
The CDB5378 evaluation kit includes:
• CDB5378 Evaluation Board
• USB Cable (A to B)
• Software Download Information Card
The following are required to operate CDB5378, and are not included:
• Bipolar Power Supply with Banana Jack Outputs (+/-12 V @ 100 mA)
• Banana Jack Cables (4x)
• PC Running Windows 2000 or XP with an Available USB Port
• Internet Access to Download the Evaluation Software
CDB5378
1.2 Hardware Setup
To set up the CDB5378 evaluation board:
• Set all jumpers and DIP switches to their default settings (see next sections).
• With power off, connect the CDB5378 power inputs to the power supply outputs.
VA- = -12 V
VA+ = +12 V
GND = 0 V
VD = +12 V
• Connect the USB cable between the CDB5378 USB connector and the PC USB port.
• Proceed to the Software Setup section to install the evaluation software and USB driver.
DS639DB4 7
1.2.1 Default Jumper Settings
DAC_OUT+ 1 **2INA+
DAC_OUT- 3 **4INA-
DAC_OUT- 5 ---------- 6INBDAC_OUT+ 7 ---------- 8INB+
DAC_BUF+ 9 ---------- 10 INA+
DAC_BUF- 11 ---------- 12 INA-
DAC_BUF- 13 **14 INB-
DAC_BUF+ 15 **16 INB+
BNC_IN+ 17 **18 INA+
BNC_IN- 19 **20 INA-
BNC_IN- 21 **22 INB-
BNC_IN+ 23 **24 INB+
CDB5378
J27
Analog Input Selections
Table 1. Analog Input Default Jumper Settings
J40
Digital Filter RESET Selection
RST_PB 1 ---------- 2
RST_MC 3 **4
RST_EXT 5 **6
RST_CPLD 7 **8
SPI Chip Select Input
EECS 4 **3SS
SS 2 ---------- 1SS
SYNC Source Selection
SYNC_IO 2 ---------- 1 SYNC
J58
Microcontroller RESET Selection
RST_PB 1 ---------- 2
RST_EXT 3 **4
RST_CPLD 5 **6
7 **8
J43
J56
Table 2. RESET, SPI, SYNC Default Jumper Settings
8 DS639DB4
CDB5378
J19
Voltage Reference Jumpers
VREF- 4 ---------- 3
VREF+ 2 ---------- 1
J10
VA- Voltage Selection
-2.5VA 1 ---------- 2
GND 3 **4
EXT_VA- 5 **6
J12
VD Input Voltage Source
EXT_VA+ 1 **2
EXT_VD 3 ---------- 4
J22
VD Voltage Selection
+3.3VD 1 ---------- 2
EXT_VD 3 **4
Table 3. VREF, Power Supplies Default Jumper Set ting s
J11
VA+ Voltage Selection
+2.5VA 1 ---------- 2
+5VA 3 **4
EXT_VA+ 5 **6
J13
VCORE Input Voltage Source
EXT_VA+ 1 **2
EXT_VD 3 ---------- 4
J21
VCORE Voltage Selection
+3.3VD 1 ---------- 2
+2.5VD 3 **4
EXT_VD 5 **6
J16, J17, J18
Digital Filter, CPLD,
Microcontroller
Input Clock Selections
32.768 MHz 1 ---------- 2
16.384 MHz 3 **4
8.192 MHz 5 **6
4.096 MHz 7 **8
2.048 MHz 9 **10
1.024 MHz 11 * *12
CLK_EXT 13 **14
15 **16
Table 4. Clock Default Jumper Settings
DS639DB4 9
50 Ohms 2 **1
Clock Input TERM
J5
CDB5378
J15
I2C Data
SDA+ 1 ---------- 2
SDA- 3 ---------- 4
SDA 5 **6
GND 7 **8
J24
Clock Source
CLK+ 1 ---------- 2
CLK- 3 ---------- 4
CLK_I/O 5 **6
GND 7 **8
J14
I2C Clock
SCL+ 1 ---------- 2
SCL- 3 ---------- 4
SCL 5 **6
GND 7 **8
J23
I2C Clock Driver Enable
GND 1 ---------- 2
VD 3 **4
J25
Sync Source
SYNC+ 1 ---------- 2
SYNC- 3 ---------- 4
SYNC_I/O 5 **6
GND 7 **8
J33
Clock Driver Enable
GND 1 ---------- 2
VD 3 **4
Table 5. RS-485 Default Jumper Settings
1.2.2 Default DIP Switch Settings
S5
* = down, - = up
SP_SW1 1 *-2
LOGIC_GND 3 *-4
PWDN 5 *-6
7 *-8
Table 6. DIP Switch Default Settings
J34
Sync Driver Enable
GND 1 ---------- 2
VD 3 **4
S1
* = down, - = up
GAIN0:PLL0 1 *-2
GAIN1:PLL1 3 *-4
GAIN2:PLL2 5 *-6
MUX:BOOT 7 -*8
10 DS639DB4
CDB5378
1.3 Software Setup
1.3.1 PC Requirements
The PC hardware requirements for the Cirrus Seismic Evaluation system are:
• Windows XP, Windows 2000, Windows NT
• Intel Pentium 600MHz or higher microprocessor
• VGA resolution or higher video card
• Minimum 64MB RAM
• Minimum 40MB free hard drive space
1.3.2 Seismic Evaluation Software Installation
Important: For reliable USB communication, the USBXpress driver must be installed after the Seismic
Evaluation Software installation but before launching the application. The USBXpress driver files are in-
cluded in a sub-folder as part of the installation.
To install the Cirrus Logic Seismic Evaluation Software:
• Go to the Cirrus Logic Industrial Software web page (http://www.cirrus.com/industrialsoftware
the link for “Cirrus Seismic Evaluation GUI” to get to the download page and then click the link for “Cir-
rus Seismic Evaluation GUI Release Vxx” (xx indicates the version number).
• Read the software license terms and click “Accept” to download the “SeismicEvalGUI_vxx.zip” file to
any directory on the PC.
• Unzip the downloaded file to any directory and a “Distribution\Volume1” sub-folder containing the installation application will automatically be created.
• Open the “Volume1” sub-folder and run “setup.exe”. If the Seismic Evaluation Software has been previously installed, the uninstall wizard will automatically remove the previous version and you will need
to run “setup.exe” again.
• Follow the instructions presented by the Cirrus Seismic Evaluation Installation Wizard. The default installation location is “C:\Program Files\Cirrus Seismic Evaluation”.
An application note, AN271 - Cirrus Seismic Evaluation GUI Installation Guide, is available from the Cirrus
Logic web site with step-by-step instructions on installing the Seismic Evaluation Software.
). Click
1.3.3 USBXpress Driver Installation
Important: For reliable USB communication, the USBXpress driver must be installed after the Seismic
Evaluation Software installation but before launching the application. The USBXpress driver files are in-
cluded in a sub-folder as part of the installation.
The Cirrus Logic Seismic Evaluation Software communicates with CDB5378 via USB using the USBXpress driver from Silicon Laboratories (http://www.silabs.com
files are included as part of the installation package.
). For convenience, the USBXpress driver
To install the USBXpress driver (after installing the Seismic Evaluation Software):
• Connect CDB5378 to the PC through an available USB port and apply power. The PC will detect
DS639DB4 11
CDB5378
CDB5378 as an unknown USB device.
• If prompted for a USB driver, skip to the next step. If not, using Windows Hardware Device Manager
go to the properties of the unknown USB API device and select “Update Driver”.
• Select “Install from a list or specific location”, then select “Include this location in the search” and then
browse to “C:\Program Files\Cirrus Seismic Evaluation\Driver\”. The PC will recognize and install the
USBXpress device driver.
• After driver installation, cycle power to CDB5378. The PC will automatically detect it and add it as a
USBXpress device in the Windows Hardware Device Manager.
An application note, AN271 - Cirrus Seismic Evaluation GUI Installation Guide, is available from the Cirrus
Logic web site with step-by-step instructions on installing the USBXpress driver.
1.3.4 Launching the Seismic Evaluation Software
Important: For reliable USB communication, the USBXpress driver must be installed after the Seismic
Evaluation Software installation but before launching the application. The USBXpress driver files are in-
cluded in a sub-folder as part of the installation.
To launch the Cirrus Seismic Evaluation Software, go to:
• Start
or:
• C:\Program Files\Cirrus Seismic Evaluation\SeismicGUI.exe
For the most up-to-date information about the software, please refer to its help file:
• Within the software: Help
or:
• C:\Program Files\Cirrus Seismic Evaluation\SEISMICGUI.HLP
Ö
Programs Ö Cirrus Seismic Evaluation Ö Cirrus Seismic Evaluation
Ö
Contents
12 DS639DB4
CDB5378
1.4 Self-testing CDB5378
Noise and distortion self-tests can be performed once hardware and software setup are complete.
First, initialize the CDB5378 evaluation system:
• Launch the evaluation software and apply power to CDB5378.
• Click ‘OK’ on the About panel to get to the Setup panel.
• On the Setup panel, select Open Target on the USB Port sub-panel.
• When connected, the Board Name and MCU code version will be displayed.
1.4.1 Noise test
Noise performance of the measurement channel can be tested as follows:
• Set the controls on the Setup panel to match the picture:
DS639DB4 13
• Once the Setup panel is set, select Configure on the Digital Filter sub-panel.
• After digital filter configuration is complete, click Capture to collect a data record.
• Once the data record is collected, the Analysis panel is automatically displayed.
• Select Noise FFT from the Test Select control to display the calculated noise statistics.
• Verify the noise performance (S/N) is 124 dB or better.
1.4.2 Distortion Test
• Set the controls on the Setup panel to match the picture:
CDB5378
• Once the Setup panel is set, select Configure on the Digital Filter sub-panel.
• After digital filter configuration is complete, click Capture to collect a data record.
• Once the data record is collected, the Analysis panel is automatically displayed.
• Select Signal FFT from the Test Select control to display the calculated signal statistics.
• Verify the distortion performance (S/D) is 112 dB or better.
14 DS639DB4
2. HARDWARE DESCRIPTION
2.1 Block Diagram
CDB5378
Figure 1. CDB5378 Block Diagram
Major blocks of the CDB5378 evaluation board include:
• CS3301A Geophone Amplifier
• CS5373A ∆Σ Modulator + Test DAC
• CS5378 Digital Filter + PLL
• Precision Voltage Reference
• Interface CPLD
• Microcontroller with USB
• RS-485 Transceivers
• Voltage Regulators
DS639DB4 15
CDB5378
2.2 Analog Hardware
2.2.1 Analog Inputs
2.2.1.1 External Inputs - INA, INB, BNC
External signals into CDB5378 are from two major classes of sensors, moving coil geophones and piezoelectric hydrophones. Geophones are low-impedance sensors optimized to measure vibrations in land
applications. Hydrophones are high-impedance sensors optimized to measure pressure in marine applications. Other sensors for earthquake monitoring and military applications are considered as geophones
for this datasheet.
External signals connect to CDB5378 through screw terminals on the left side of the PCB. These screw
terminals make connections to two external differential inputs, INA and INB. In addition, GND and GUARD
connections are provided for connecting sensor cable shields, if present.
Signal Input Screw Terminal
INA J32
INB J41
Table 7. Screw Terminal Input Connectors
BNC inputs for connecting external signals are not populated during board manufacture, but the empty
PCB footprints exist and can be installed. The inner conductors of the BNC inputs make connections to
the + and - differential signal traces, with the outer shields connected to ground. The BNC inputs can be
connected to the INA or INB inputs through the input selection jumpers.
2.2.1.2 GUARD Output, GND Connection
By default, CDB5378 uses the CS3301A differential geophone amplifier. By replacing the amplifier and
changing the pin 13 signal assignment (J42) it is possible to use the CS3302A hydrophone amplifier instead. The CS3301A amplifier expects an MCLK clock input to pin 13 while the CS3302A amplifier produces an analog GUARD signal output to pin 13.
The CS3302A hydrophone amplifier analog GUARD signal output is designed to actively drive the cable
shield of a high impedance sensor with the common mode voltage of the sensor differential signal. This
GUARD output on the cable shield minimizes leakage by minimizing the voltage differential between the
sensor signal and the cable shield.
When using the CS3301A amplifier, which does not have a GUARD output, a separate GND screw terminal is provided for the sensor cable shield. When jumper J42 is set for the CS3301A amplifier the
GUARD output screw terminal is left floating.
2.2.1.3 Internal Inputs - DAC_OUT, DAC_BUF
The CS5373A test DAC has two high-performance differential test outputs, a precision output
(DAC_OUT) and a buffered output (DAC_BUF). These test outputs can be connected to the INA or INB
inputs through the input selection jumpers.
16 DS639DB4
CDB5378
By default, CDB5378 is populated with passive RC filter components on the INA inputs, and no filter components on the INB inputs (though the component footprints are present on the INB inputs). Because the
CS5373A precision output will not tolerate significant loading, the DAC_ OUT signal should only jumper to
the INB inputs on CDB5378. The CS5373A buffered outputs are less sensitive to the RC filter load and
DAC_BUF can be jumpered to either the INA or INB inputs.
2.2.1.4 Input Protection
Sensor inputs must have circuitry to protect the analog electronics from voltage spikes. Geophone coils
are susceptible to magnetic fields (especially from lightning) and hydrophones can produce large voltag e
spikes if located near an air gun source.
Discrete switching diodes quickly clamp the analog inputs to the power supply rails when the input voltage
spikes. These diodes are reverse biased in normal operation and have low reverse bias leakage and capacitance characteristics to maintain high linearity on the analog inputs.
Specification Value
Dual Series Switching Diode - ON Semiconductor BAV99LT1
Surface Mount Package Type SOT-23
Non-Repetitive Peak Forward Current (1 µs, 1 ms, 1 s)
Reverse Bias Leakage (25 C to 85 C)
Reverse Bias Capacitance (0 V to 5 V) 1.5 pF - 0.54 pF
2.0 A, 1.0 A, 500 mA
0.004 µA - 0.4 µA
2.2.1.5 Input RC Filters
Following the diode clamps is an RC filter network that bandwidth limits the sensor inputs into the amp lifier
to “chop the tops off” residual voltage spikes not clamped by the discrete diodes. In addition, all Cirrus
Logic component ICs have built in ESD protection diodes guaranteed to 2000 V HBM / 200 V MM (JEDEC
standard). The small physical size of these ESD diodes restricts their current capacity to 10 mA.
For land applications using the CS3301A amplifier, the INA input has a common mode and differential RC
filter. The common mode filter sets a low-pass corner to shunt very-high-frequency components to ground
with minimal noise contribution. The differential filter sets a low-pass corner high enough not to affect the
magnitude response of the measurement bandwidth.
For marine applications that use the CS3302A amplifier, the inherent capa citance of the piezoelectric sensor is combined with large resistors connected to the input signal common mode to create an analog highpass RC filter to eliminate the low-frequency components of ocean noise. Following the high-pass common mode filter is a differential low-pass filter to reject high-frequency signals into the amplifier. The cutoff
frequency for the low-pass filter is high enough not to affect the magnitude response of the measurement
bandwidth.
By default, CDB5378 uses the CS3301A differential geophone amplifier and so the input RC filter on the
INA inputs are set for land applications. Marine applications using the CS3302A amplifier will need to
modify the input RC filter components.
DS639DB4 17
Land Common Mode Filter Specification Value
Common Mode Capacitance 10 nF + 10%
Common Mode Resistance
200 Ω
Common Mode -3 dB Corner @ 6 dB/octave 80 kHz + 10%
Land Differential Filter Specification Value
Differential Capacitance 10 nF + 10%
Differential Resistance
200 Ω + 200 Ω = 400 Ω
Differential -3 dB Corner @ 6 dB/octave 40 kHz + 10%
Marine Common Mode Filter Specification Value
Hydrophone Group Capacitance 128 nF + 10%
Common Mode Resistance
825 kΩ || 825 kΩ = 412 kΩ
-3 dB Corner @ 6 dB/octave 3 Hz + 10%
Marine Differential Filter Specification Value
Differential Capacitance 10 nF + 10%
Differential Resistance
200 Ω + 200 Ω = 400 Ω
-3 dB Corner @ 6 dB/octave 40 kHz + 10%
CDB5378
2.2.1.6 Common Mode Bias
Differential analog signals into the CS3301A/02A amplifiers are required to be biased to the center of the
power supply voltage range, which for bipolar supplies is near ground potential. This common mode bias
voltage is created by buffering the voltage reference, which is nominally +2.5 V relative to the VA- power
supply.
By default, CDB5378 uses the CS3301A differential geophone amplifier and so the common mode bias
resistors on the INA inputs are set for land applications. Marine application s using the CS3302A amplifier
will need to modify the default common mode bias resistors.
Resistors to create the common mode bias are normally selected based on the sensor impedance and
may need to be modified from the CDB5378 defaults depending on the sensor used. Refer to the recommended operating bias conditions for the selected sensor, which are available from the sensor manufacturer.
Specification Value
Geophone Sensor Bias Resistance
Hydrophone Sensor Bias Resistance
20 kΩ || 20 kΩ = 10 kΩ
18 MΩ || 18 MΩ = 9 MΩ
18 DS639DB4
CDB5378
2.2.2 Differential Amplifiers
The CS3301A/02A amplifiers act as a low-noise gain stage for internal or e xternal differe ntial analog signals.
Analog Signals Description
INA Sensor analog input
INB Test DAC analog input
OUTR, OUTF Analog rough / fine outputs
GUARD CS3302A guard output (jumper selection)
Digital Signals Description
MUX[0..1] Input mux selection
GAIN[0..2] Gain range selection
PWDN Power down mode enable
CLK CS3301A clock input (jumper selection)
2.2.2.1 MCLK Input vs. GUARD Output
By default, CDB5378 uses the CS3301A geophone amplifier which is chopper stabilized. The CS3301A
connects pin 13 to a clock source (MCLK) to run the chopper circuitry synchronous to the modulator analog sampling clock. The CS3302A hydrophone amplifier is not chopper stabilized (with 1/f noise typically
buried below the low-frequency ocean noise) to achieve very high input impedance. To minimize le akage
from high-impedance sensors connected to the CS3302A amplifier, pin 13 produces a GUARD signal output to actively drive a sensor cable shield with the common mode voltage of the sensor signal.
Comparing the CS3301A and CS3302A amplifiers, the functionality of pin 13 (MCLK input vs. GUARD
output) is the only external difference. CDB5378 can be converted to use either the CS3301A or CS3302A
by replacing the amplifier device and properly setting the pin 13 jumper (J42). By default this jumper is not
populated and has a shorting trace between pins on the back side of the PCB. Converting between amplifier types requires carefully cutting the default short and installing a jumper. A replacement amplifier
can be requested as a sample from your local Cirrus Logic sales representative.
2.2.2.2 Rough-Fine Outputs - OUTR, OUTF
The analog outputs of the CS3301A/02A differential amplifiers are split into rough-charge and fine-charge
signals for input to the CS5373A ∆Σ modulator.
Analog signal traces out of the CS3301A/02A amplifiers and into the CS5373A modulator are 4-wire
INR+ / INF+ / INF- / INR- quad groups, and are routed with INF+ and INF- as a traditional differential pair
and INR+ and INR- as guard traces outside the respective INF+ and INF- traces.
2.2.2.3 Anti-alias RC Filters
The CS5373A ∆Σ modulator is 4th order and high-frequency input signals can cause instability. Simple
single-pole anti-alias RC filters are required between the CS3301A/02A amplifier outputs and the
CS5373A modulator inputs to bandwidth limit analog signals into the modulator.
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CDB5378
The CS3301A/02A amplifier outputs require a differential anti-alias RC filter, which is created by connecting external 680
tween each half of the rough and fine signals.
Ω series resistors with 20 nF of high-linearity differential capacitance (2x 10 nF C0G) be-
INR+
INF+
INFINR-
Figure 2. Quad Group Routing of RC Filter Components
INR+
INF+
INFINR-
2.2.3 Delta-Sigma Modulator
The CS5373A ∆Σ modulator performs the A/D function for the differential analog signal from the
CS3301A/02A amplifier. The digital output from the modulator is an oversampled ∆Σ bit stream.
Analog Signals Description
INR, INF Modulator analog rough / fine inputs
VREF Voltage reference analog inputs
Digital Signals Description
MDATA Modulator delta-sigma data output
MFLAG Modulator over-range flag output
MCLK Clock input
MSYNC Synchronization input
2.2.3.1 Rough-Fine Inputs - INR, INF
The modulator analog inputs are separated into rough and fine signals, each of which has a differential
anti-alias RC filter to limit the input signal bandwidth.
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CDB5378
2.2.4 Delta-Sigma Test DAC
The CS5373A ∆Σ DAC creates differential analog signals for system tests. Multiple test modes are available and their use is described in the CS5373A data sheet.
Analog Signals Description
OUT Precision differential analog output
BUF Buffered differential analog output
CAP Capacitor connection for internal anti-alias filter
VREF Voltage reference analog inputs
Digital Signals Description
TDATA Delta-sigma test data input
MCLK Clock input
MSYNC Synchronization input
MODE[0..2] Test mode selection
ATT[0..2] Attenuation range selection
2.2.4.1 Precision Output - DAC_OUT
The CS5373A test DAC has a precision output (DAC_OUT) that is routed to the input selection jumper.
This output is sensitive to loading, and on CDB5378 should only be jumpered into the INB input which
does not have passive RC filter components installed. The input impedance of the CS3301A/02A amplifiers are high enough that the DAC precision output can be connected to the INB input directly.
2.2.4.2 Buffered Output - DAC_BUF
The CS5373A test DAC has a buffered output (DAC_BUF) that is also routed to the input selection jumper. This output is less sensitive to loading than the precision output, and can be jumpered into either the
INA or INB input without affecting performance. The buffered output can also drive a sensor attached to
the input screw terminals, provided the sensor meets the impedance requirements specified in the
CS5373A data sheet.
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CDB5378
2.2.5 Voltage Reference
A voltage reference on CDB5378 creates a precision voltage from the regulated analog supplies for the
CS5373A VREF input. Because the voltage reference output is generated relative to the negative analog
power supply, VREF+ is near GND potential for bipolar power supplies.
Specification Value
Precision Reference - Linear Tech LT1019AIS8-2.5
Surface Mount Package Type SO-8
Output Voltage Tolerance +/- 0.05%
Temperature Drift 10 ppm / degC
Quiescent Current 0.65 mA
Output Voltage Noise, 10 Hz - 1 kHz 4 ppm
Ripple Rejection, 10 Hz - 200 Hz > 100 dB
2.2.5.1 VREF_MOD
The voltage reference output is provided to the CS5373A modulator and test DAC through a low-pass RC
filter. By filtering the voltage reference input to the device, high-frequency noise is eliminated and any signal-dependent sampling of VREF is isolated. The voltage reference signal is routed as a differential pair
from the large RC filter capacitor to control the sensitive VREF source-return currents and keep them out
of the ground plane. In addition to the RC filter function, the 100 uF filter capacitor provides a large chargewell to help settle voltage reference sampling transients.
RMS
2.2.5.2 Common Mode Bias
A buffered version of the voltage reference is created as a low-impedance common mode bias source for
the analog signal inputs. The bias resistors connected between the buffered voltage reference and each
analog signal input half depends on the sensor type and should be modified to match the sensor manufacturer recommendations.
2.3 Digital Hardware
2.3.1 Digital Filter
The CS5378 digital filter performs filtering and decimation of the ∆Σ bit stream from the CS5373A modulator. It also creates a ∆Σ test bit stream output to create analog test signals in the CS5373A DAC.
The CS5378 requires several control signal inputs from the external system.
Control Signals Description
CLK Master clock input.
RESETz Reset input, active low
SYNC Master synchronization input, rising edge triggered
TIMEB Time Break input, rising edge triggered
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CDB5378
Configuration and data collection are through the SPI port.
SPI1 Signals Description
DRDYz Data ready output, active low
SCK Serial clock
MISO Master in / slave out serial data
MOSI Master out / slave in serial data
SS:EECSz Serial chip select, active low
Modulator ∆Σ data is input through the modula tor interface, and test DAC ∆Σ data is generated by the test
bit stream generator.
Modulator Signals Description
MCLK Modulator clock output
MSYNC Modulator synchronization output
MDATA Modulator delta-sigma data inputs
MFLAG Modulator over-range flag inputs
TBSDATA Test DAC delta-sigma data output
Amplifier, modulator and test DAC pin settings are controlled through the GPIO port.
GPIO Signals Description
GPIO[0]:MUX[0] Amplifier input mux selection
GPIO[1..3]:MODE[0..2] Test DAC mode selection
GPIO[4..6]:GAIN[0..2] Amplifier gain / test DAC attenuation
GPIO[7]:MUX[1] Amplifier input mux selection
2.3.1.1 Reset Options - BOOT, PLL
Immediately following the reset signal rising edge, the CS5378 digital filter latches the states of the
GPIO[4..6]:PLL[0..2] and GPIO7:BOOT pins. The reset states of the GPIO[4..6]:PLL[0..2] pins select the
master clock input frequency and type, while the reset state of the GPIO7:BOOT pin selects how the
CS5378 digital filter receives configuration data.
At reset the CS5378 digital filter GPIO pins default as inputs with weak pull-up resistors enabled. If left
floating, the GPIO state reads high at reset because of the internal pull-up resistor. A four-position DIP
switch on CDB5378 (S5) can connect 10k Ω pull-down resistors to the GPIO[4..6]:PLL[0..2] or
GPIO7:BOOT pins so they will read low at reset. Because the pin states are latched at reset, GPIO pins
can be programmed and used normally after reset without affecting the PLL and BOOT selections.
Detailed information about the PLL input clock and BOOT mode selections at reset can be found in the
CS5378 data sheet.
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