Cirrus Logic CDB5376 User Manual
CDB5376
Multichannel Seismic Evaluation System
Features
z Four-channel Seismic Acquisition Node
– CS3301A geophone amplifiers (2x)
– CS3302A hydrophone amplifiers (2x)
– CS5372A dual ∆Σ modulators (2x)
– CS5376A quad digital filter (1x)
– CS4373A ∆Σ test DAC (1x)
– Precision voltage reference
– Clock recovery PLL
z On-board Microcontroller
– SPI™ interface to digital filter
– USB communication with PC
z PC Evaluation Software
– Register setup & control
– FFT frequency analysis
– Time domain analysis
– Noise histogram analysis
General Description
The CDB5376 board is used to evaluate the functionality
and performance of the Cirrus Logic multichannel seismic chip set. Data sheets for the CS3301A, CS3302A,
CS4373A, CS5371A/72A, and CS5376A devices should
be consulted when using the CDB5376 evaluation
board.
Screw terminals connect external differential geophone
or hydrophone sensors to the analog inputs of the measurement channels. An on-board test DAC creates
precision differential analog signals for in-circuit performance testing without an external signal source.
The evaluation board includes an 8051-type microcontroller with hardware SPI
The microcontroller communic ates with the digital filter
via SPI and with the PC evaluation software via USB.
The PC software controls register and coefficient initialization and performs time domain, histogram, and FFT
frequency analysis on captured data.
ORDERING INFORMATION
CDB5376 Evaluation Board
™ and USB serial interfaces.
www.cirrus.com
Copyright © Cirrus Logic, Inc. 2008
(All Rights Reserved)
JAN ‘08
DS612DB3
REVISION HISTORY
Revision Date Changes
DB1 FEB 2006 Initial release.
DB2 MAR 2006 Added USB support.
DB3 DEC 2007
Updated schematics:
CS3301 to CS3301A
CS3302 to CS3302A
CS5372 to CS5372A
CDB5376
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Re presentative. To find the one near est to you
go to www.cirrus.com
IMPORTANT NOTICE
Cirrus Logic, Inc. and its subsidiaries ("Cirru s") believe that the information contained in this document is accurate and reli a b le. However, the information is subject
to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant
information to verify, before placing or ders, that in formatio n be ing relied on is current and comple te. All products a re sold s ubj ect to the term s and conditions of sa le
supplied at the time of order acknow ledgment, includin g those pertaining to warranty, indemni fication, and limitatio n of liability. No responsibility is assumed by Cirrus
for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third
parties. This document is the prop erty o f C irrus a nd b y furn ishing this inform ation, Cirru s grants no lice nse, expres s or implied under any patents, mask work rights,
copyrights, trade marks, trad e secrets or other int ellectual property r ights. Cirr us owns the co pyrights a ssociated wit h the inf ormation contained herein and gives
consent for copies to be made of the inform ation only for us e withi n your o rgani zation w ith resp ect to Cir rus in tegrate d circui ts or other p rodu cts of C irrus. This co nsent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR
USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK
AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER
OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE,
TO FULLY INDEMNI FY CIRRUS , ITS O FFICERS, DIRECTOR S, EMPLOY EES, DIST RIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILI TY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks
or service marks of their respective owners.
Windows, Windows XP, Windows 2000, and Windows NT are trademarks or registered trademarks of Microsoft Corporation.
Intel and Pentium are registered trademarks of Intel Corporation.
SPI is a trademark of Motorola, Inc.
I2C (I2C) is a registered trademark of Philips Semiconductor Corporation.
USBExpress is a registered trademark of Silicon Laboratories, Inc.
2 DS612DB3
CDB5376
TABLE OF CONTENTS
1. INITIAL SETUP ......................................................................................................................... 7
1.1 Kit Contents ..................................... ... ............................................................................... 7
1.2 Hardware Setup ............................... ....................... ...................... ....................... .............. 7
1.2.1 Default Jumper Settings ............................. ... ... ... .... ... ... ... ... .... .............................. 8
1.2.2 Default DIP Switch Settings ......................................... ... ................................... 10
1.3 Software Setup .......................................... ... ... ... .... ... ... .......................................... ......... 11
1.3.1 PC Requirements ............................. ... ... .... ... ... .......................................... ......... 11
1.3.2 Seismic Evaluation Software Installation ............................................................ 11
1.3.3 USBXpress Driver Installation ............................................................................. 11
1.3.4 Launching the Seismic Evaluation Software .............................. ......................... 12
1.4 Self-testing CDB5376 ............................ .... ... ... ... .... ... ....................................... ... ... ... ... ... 13
1.4.1 Noise test ..... .... ... ... ... .... ...................................... .... ... ... ... ... .... ............................ 13
1.4.2 Distortion Test .. ... .......................................... .......................................... ... ......... 14
2. HARDWARE DESCRIPTION ................................................................................................. 15
2.1 Block Diagram ................................................................................................................ 15
2.2 Analog Hardware .......................... .......................................... ......................................... 16
2.2.1 Analog Inputs ...... ... ... .... ... ... ... ... ....................................... ... .... ... ... ... .... ... ... ......... 16
2.2.2 Differential Amplifiers .... ... .......................................... ......................................... 19
2.2.3 Delta-Sigma Modulators ..................................................................................... 20
2.2.4 Delta-Sigma Test DAC ............................... ... ... ... .... ... ... ... ... .... ............................ 21
2.2.5 Voltage Reference .................... .... ...................................... .... ... ... ... .... ... ... ... ...... 22
2.3 Digital Hardware .............................................................................................................. 23
2.3.1 Digital Filter ................................................ ... ....................................... ... ... ... ... ... 23
2.3.2 Interface CPLD ....................................................................... ............................ 25
2.3.3 Digital Control Signals ......................... ... .... ...................................... .... ... ... ... ... ... 27
2.3.4 Microcontroller ........................................................ ... ... ... ... .... ... ... ... ................... 27
2.3.5 Phase Locked Loop ......................... ... ... .... .......................................... ............... 29
2.3.6 RS-485 Telemetry .. ... .......................................................................................... 31
2.3.7 UART Connection .. ... .... ... ... ... ... .... ... ... ... .......................................... ................... 32
2.3.8 External Connector .......................... ... ... .... ... ... .......................................... ......... 33
2.4 Power Supplies ................ ... ... .... .......................................... ............................................ 33
2.4.1 Analog Voltage Regulators ................. ... .... ... ... ... .... ... ......................................... 33
2.4.2 Digital Voltage Regulators .................................................................................. 34
2.5 PCB Layout ..................................................... ... .... ... ... ....................................... ... ... ...... 35
2.5.1 Layer Stack ...... ... ... ... .... ... ... ... ....................................... ... ... .... ... ... ... .... ... ............ 35
2.5.2 Differential Pairs ............................ ... ... ... .... ... ... ... .......................................... ...... 35
2.5.3 Bypass Capacitors . ... .... ...................................... .... ... ... ... ... .... ... ... ...................... 36
2.5.4 Dual Row Headers .............................................................................................. 37
3. SOFTWARE DESCRIPTION .................................................................................................. 38
3.1 Menu Bar ......................................... ... ... .... ...................................... .... ... ... ... .... ... ... ......... 38
3.2 About Panel ..................................................................................................................... 39
3.3 Setup Panel ..................................................................................................................... 40
3.3.1 USB Port ...... .... ... ... ... .... ...................................... .... ... ... ... ... .... ............................ 41
3.3.2 Digital Filter ................................................ ... ....................................... ... ... ... ... ... 42
3.3.3 Analog Front End ...... .... ... ... ... ... .... ... ... ... .......................................... .... ............... 43
3.3.4 Test Bit Stream ......................... .... ... ................................................................... 43
3.3.5 Gain/Offset ............................. ... .... ... ... ... .... ...................................... .... ... ... ... ... ... 44
3.3.6 Data Capture .......................... ....................................... ... ... .... ... ... ...................... 45
3.3.7 External Macros ..... ... .... ... ... ... ... .... ... ....................................... ... ... ... .... ... ... ... ... ... 46
3.4 Analysis Panel ................................................................................................................. 47
3.4.1 Test Select ... .... ... ... ... .... ...................................... .... ... ... ... ... .... ... ......................... 48
3.4.2 Statistics ........................ ... ... ... ... .... ... ... ... ....................................... ... .... ... ... ... ... ... 49
DS612DB3 3
CDB5376
3.4.3 Plot Enable .................................................................... ... ... .... ... ... ... .... ... ............49
3.4.4 Cursor ........................................................ ... ....................................... ... ... ... ... ... 50
3.4.5 Zoom ............................................. ... ....................................... ... ... ... .... ... ............50
3.4.6 Refresh ...................... .... ............................................................................. ... ... ... 50
3.4.7 Harmonics ........................................... ... .... .........................................................50
3.4.8 Spot Noise ..................................................... ... ... .... ... ... ...................................... 50
3.4.9 Plot Error ............................................. ... ....................................... ... .... ... ... ... ......50
3.5 Control Panel ...................................................................................................................51
3.5.1 DF Registers ............. .............................................................................. ... ... ... ... 52
3.5.2 DF Commands ........................................... ... ... ...................................................52
3.5.3 SPI ......................................................... .... ...................................... .... ... ... ... ... ...52
3.5.4 Macros ....................................................... ...................................... .... ... ... ... ... ... 53
3.5.5 GPIO ............ ....................................... ... .... ... ... ... .... ...................................... ... ... 53
3.5.6 Customize .............................................. .... ... ... ... .... ... ...................................... ... 54
3.5.7 External Macros ............... ... ... ............................................................................. 54
4. BILL OF MATERIALS ........................................................................................................... 55
5. LAYER PLOTS ...................................................................................................................... 58
6. SCHEMATICS ........................................................................................................................ 66
4 DS612DB3
LIST OF FIGURES
Figure 1. CDB5376 Block Diagram............................................................................................... 15
Figure 2. RC Filter External Components..................................................................................... 20
Figure 3. CPLD Default Signal Assignments ................................................................................ 26
Figure 4. Differential Pair Routing................................................................................................. 35
Figure 5. Quad Group Routing...................................................................................................... 36
Figure 6. Bypass Capacitor Placement......................................................................................... 36
Figure 7. Dual-row Headers with Shorts....................................................................................... 37
CDB5376
DS612DB3 5
LIST OF TABLES
Table 1. Analog Inputs Default Jumper Settings........................ ... .... ... ... ... ... .... .............................. 8
Table 2. VREF, SPI, SYNC, RESET Default Jumper Settings........................................................8
Table 3. Power Supplies Default Jumper Settings..........................................................................9
Table 4. Clock Inputs Default Jumper Settings .............................................................. ... ... ... ... .... . 9
Table 5. RS-485 Default Jumper Settings..................................................................................... 10
Table 6. DIP Switch Default Settings ............................................................................................10
Table 7. Screw Terminal Input Connectors...................................................................................16
CDB5376
6 DS612DB3
1. INITIAL SETUP
1.1 Kit Contents
The CDB5376 evaluation kit includes:
• CDB5376 Evaluation Board
• USB Cable (A to B)
• Software Download Information Card
The following are required to operate CDB5376, and are not included:
• Bipolar Power Supply with Banana Jack Outputs (+/-12 V @ 300 mA)
• Banana Jack Cables (4x)
• PC Running Windows 2000 or XP with an Available USB Port
• Internet Access to Download the Evaluation Software
CDB5376
1.2 Hardware Setup
To set up the CDB5376 evaluation board:
• Set all jumpers and DIP switches to their default settings (see next sections).
• With power off, connect the CDB5376 power inputs to the power supply outputs.
VA- = -12 V
VA+ = +12 V
GND = 0 V
VD = +12 V
• Connect the USB cable between the CDB5376 USB connector and the PC USB port.
• Proceed to the Software Setup section to install the evaluation software and USB driver.
DS612DB3 7
1.2.1 Default Jumper Settings
DAC_OUT+ 1 **2INA+
DAC_OUT- 3 **4INA-
DAC_OUT- 5 ---------- 6INBDAC_OUT+ 7 ---------- 8INB+
DAC_BUF+ 9 ---------- 10 INA+
DAC_BUF- 11 ---------- 12 INA-
DAC_BUF- 13 **14 INB-
DAC_BUF+ 15 **16 INB+
BNC_IN+ 17 **18 INA+
BNC_IN- 19 **20 INA-
BNC_IN- 21 **22 INB-
BNC_IN+ 23 **24 INB+
CDB5376
J27, J227, J327, J427
CH1, CH2, CH3, CH4
Analog Input Selections
Table 1. Analog Inputs Default Jumper Settings
J519, J19, J20
Voltage Reference Jumpers
VREF+ 1 ---------- 2
VREF- 3 ---------- 4
J56
SYNC Source Selection
SYNC_IO 1 ---------- 2 SYNC
Table 2. VREF, SPI, SYNC, RESET Default Jumper Settings
EECS 3 **4 SSI
J43
SPI Chip Select Input
SSI 1 ---------- 2 SSI
J58
RESET Source Selection
RST_PB 1 ---------- 2
RST_EXT 3 **4
8 DS612DB3
CDB5376
J10
VA- Voltage Selection
-2.5VA 1 ---------- 2
GND 3 **4
EXT_VA- 5 **6
J12
VD Input Voltage Source
EXT_VA+ 1 **2
EXT_VD 3 ---------- 4
J22
VD Voltage Selection
+3.3VD 1 ---------- 2
EXT_VD 3 **4
Table 3. Power Supplies Default Jumper Settings
J11
VA+ Voltage Selection
+2.5VA 1 ---------- 2
+5VA 3 **4
EXT_VA+ 5 **6
J13
VCORE Input Voltage Source
EXT_VA+ 1 **2
EXT_VD 3 ---------- 4
J21
VCORE Voltage Selection
+3.3VD 1 ---------- 2
+2.5VD 3 **4
EXT_VD 3 **4
J16
PLL Input Clock Selection
32.768 MHz 1 ---------- 2
16.384 MHz 3 **4
8.192 MHz 5 **6
4.096 MHz 7 **8
2.048 MHz 9 **10
1.024 MHz 11 **12
Table 4. Clock Inputs Default Jumper Settings
DS612DB3 9
CPLD, Microcontroller
Input Clock Selections
32.768 MHz 1 **2
16.384 MHz 3 **4
8.192 MHz 5 **6
4.096 MHz 7 **8
2.048 MHz 9 **10
1.024 MHz 11 ---------- 12
CLK_EXT 13 **14
J17, J18
15 **16
CDB5376
J15
I2C Data
SDA+ 1 ---------- 2
SDA- 3 ---------- 4
SDA 5 **6
GND 7 **8
J24
Clock Source
CLK+ 1 ---------- 2
CLK- 3 ---------- 4
CLK_I/O 5 **6
GND 7 **8
J14
I2C Clock
SCL+ 1 ---------- 2
SCL- 3 ---------- 4
SCL 5 **6
GND 7 **8
J23
I2C Clock Driver Enable
GND 1 ---------- 2
VD 3 **4
J25
Sync Source
SYNC+ 1 ---------- 2
SYNC- 3 ---------- 4
SYNC_I/O 5 **6
GND 7 **8
J33
Clock Driver Enable
GND 1 ---------- 2
VD 3 **4
Table 5. RS-485 Default Jumper Settings
1.2.2 Default DIP Switch Settings
BOOT 1 *-2
LGND 5 *-6
OFST 7 -*8
Table 6. DIP Switch Default Settings
J34
Sync Driver Enable
GND 1 ---------- 2
VD 3 **4
S5
* = down, - = up
3 *-4
10 DS612DB3
1.3 Software Setup
1.3.1 PC Requirements
The PC hardware requirements for the Cirrus Seismic Evaluation system are:
CDB5376
• Windows XP®, Windows 2000™, Windows NT
®
•Intel® Pentium® 600MHz or higher microprocessor
• VGA resolution or higher video card
• Minimum 64MB RAM
• Minimum 40MB free hard drive space
1.3.2 Seismic Evaluation Software Installation
Important: For reliable USB communication, the USBXpress® driver must be installed after the Seismic
Evaluation Software installation but before launching the application. The USBXpress driver files are in-
cluded in a sub-folder as part of the installation.
To install the Cirrus Logic Seismic Evaluation Software:
• Go to the Cirrus Logic Industrial Software web page (http://www.cirrus.com/industrialsoftware
the link for “Cirrus Seismic Evaluation GUI” to get to the download page and then click the link for “Cir-
rus Seismic Evaluation GUI Release Vxx” (xx indicates the version number).
• Read the software license terms and click “Accept” to download the “SeismicEvalGUI_vxx.zip” file to
any directory on the PC.
• Unzip the downloaded file to any directory and a “Distribution\Volume1” sub-folder containing the installation application will automatically be created.
• Open the “Volume1” sub-folder and run “setup.exe”. If the Seismic Evaluation Software has been previously installed, the uninstall wizard will automatically remove the previous version during install.
• Follow the instructions presented by the Cirrus Seismic Evaluation Installation Wizard. The default installation location is “C:\Program Files\Cirrus Seismic Evaluation”.
). Click
An application note, AN271 - Cirrus Seismic Evaluation GUI Installation Guide, is available from the Cirrus
Logic web site with step-by-step instructions on installing the Seismic Evaluation Software.
1.3.3 USBXpress Driver Installation
Important: For reliable USB communication, the USBXpress driver must be installed after the Seismic
Evaluation Software installation but before launching the application. The USBXpress driver files are in-
cluded in a sub-folder as part of the installation.
The Cirrus Logic Seismic Evaluation Software communicates with CDB5376 via USB using the USBXpress driver from Silicon Laboratories (http://www.silabs.com
files are included as part of the installation package.
To install the USBXpress driver (after installing the Seismic Evaluation Software):
• Connect CDB5376 to the PC through an available USB port and apply power. The PC will detect
DS612DB3 11
). For convenience, the USBXpress driver
CDB5376
CDB5376 as an unknown USB device.
• If prompted for a USB driver, skip to the next step. If not, using Windows Hardware Device Manager
go to the properties of the unknown USB API device and select “Update Driver”.
• Select “Install from a list or specific location”, then select “Include this location in the search” and then
browse to “C:\Program Files\Cirrus Seismic Evaluation\Driver\”. The PC will recognize and install the
USBXpress device driver.
• After driver installation, cycle power to CDB5376. The PC will automatically detect it and add it as a
USBXpress device in the Windows Hardware Device Manager.
An application note, AN271 - Cirrus Seismic Evaluation GUI Installation Guide, is available from the Cirrus
Logic web site with step-by-step instructions on installing the USBXpress driver.
1.3.4 Launching the Seismic Evaluation Software
Important: For reliable USB communication, the USBXpress driver must be installed after the Seismic
Evaluation Software installation but before launching the application. The USBXpress driver files are in-
cluded in a sub-folder as part of the installation.
To launch the Cirrus Seismic Evaluation Software, go to:
• Start
or:
• C:\Program Files\Cirrus Seismic Evaluation\SeismicGUI.exe
For the most up-to-date information about the software, please refer to its help file:
• Within the software: Help
or:
• C:\Program Files\Cirrus Seismic Evaluation\SEISMICGUI.HLP
Ö
Programs Ö Cirrus Seismic Evaluation Ö Cirrus Seismic Evaluation
Ö
Contents
12 DS612DB3
CDB5376
1.4 Self-testing CDB5376
Noise and distortion self-tests can be performed once hardware and software setup are complete.
First, initialize the CDB5376 evaluation system:
• Launch the evaluation software and apply power to CDB5376.
• Click ‘OK’ on the About panel to get to the Setup panel.
• On the Setup panel, select Open Target on the USB Port sub-panel.
• When connected, the Board Name and MCU code version will be displayed.
1.4.1 Noise test
Noise performance of the measurement channel can be tested as follows:
• Set the controls on the Setup panel to match the picture:
DS612DB3 13
• Once the Setup panel is set, select Configure on the Digital Filter sub-panel.
• After digital filter configuration is complete, click Capture to collect a data record.
• Once the data record is collected, the Analysis panel is automatically displayed.
• Select Noise FFT from the Test Select control to display the calculated noise statistics.
• Verify the noise performance (S/N) is 124 dB or better.
1.4.2 Distortion Test
• Set the controls on the Setup panel to match the picture:
CDB5376
• Once the Setup panel is set, select Configure on the Digital Filter sub-panel.
• After digital filter configuration is complete, click Capture to collect a data record.
• Once the data record is collected, the Analysis panel is automatically displayed.
• Select Signal FFT from the Test Select control to display the calculated signal statistics.
• Verify the distortion performance (S/D) is 112 dB or better.
14 DS612DB3
2. HARDWARE DESCRIPTION
2.1 Block Diagram
CDB5376
Figure 1. CDB5376 Block Diagram
Major blocks of the CDB5376 evaluation board include:
• CS3301A Geophone Amplifier (2x)
• CS3302A Hydrophone Amplifier (2x)
• CS5372A Dual ∆Σ Modulators (2x)
• CS5376A Quad Digital Filter
• CS4373A ∆Σ Test DAC
• Precision Voltage Reference
• Interface CPLD
• Microcontroller with USB
• Phase Locked Loop
• RS-485 Transceivers
• Voltage Regulators
DS612DB3 15
CDB5376
2.2 Analog Hardware
2.2.1 Analog Inputs
2.2.1.1 External Inputs - INA, INB, BNC
External signals into CDB5376 are from two major classes of sensors: moving coil geophones and piezoelectric hydrophones. Geophones are low-impedance sensors optimized to measure vibrations in land
applications. Hydrophones are high-impedance sensors optimized to measure pressure in marine applications. Other sensors for earthquake monitoring and military applications are considered as geophones
for this datasheet.
External signals connect to CDB5376 through screw terminals on the left side of the PCB. For each channel (CH1, CH2, CH3, CH4), these screw terminals make connections to two external differential inputs,
INA and INB. In addition, GND and GUARD connections are provided for connecting sensor cable shields,
if present.
Signal Input Screw Terminal
CH1 INA J32
CH1 INB J41
CH2 INA J232
CH2 INB J241
CH3 INA J332
CH3 INB J341
CH4 INA J432
CH4 INB J441
Table 7. Screw Terminal Input Connectors
BNC inputs for connecting external signals are not populated during board manufacture, but the empty
PCB footprints exist and can be installed. The inner conductors of the BNC inputs make connections to
the differential signal traces, with the outer shields connected to ground. The BNC inputs can be connected to any channel’s INA or INB inputs through the input selection jumpers.
2.2.1.2 GUARD Output, GND Connection
The CS3302A hydrophone amplifier provides a GUARD signal output designed to actively drive the cable
shield of a high impedance sensor with the common mode voltage of the sensor differential signal. This
GUARD output on the cable shield minimizes leakage by minimizing the voltage differential between the
sensor signal and the cable shield.
By default, the GUARD signal is output to screw terminals on the left side of the PCB for channels 3 and
4, which use the CS3302A amplifier. There is no GUARD signal output for channels 1 and 2 since they
use the CS3301A amplifier, so the GUARD screw terminals for these channels are left floating.
A separate GND connection screw terminal for each channel is also provided if a ground connection to
the sensor cable shield is preferred.
16 DS612DB3
CDB5376
2.2.1.3 Internal Inputs - DAC_OUT, DAC_BUF
The CS4373A test DAC has two high-performance differential test outputs, a precision output
(DAC_OUT) and a buffered output (DAC_BUF). These test outputs can be connected to the INA or INB
inputs of any channel through the input selection jumpers.
By default, CDB5376 is populated with passive RC filter components on the INA inputs, and no filter components on the INB inputs (though the component footprints are present on the INB inputs). Because the
CS4373A precision output will not tolerate significant loading, on CDB5376 the DAC_OUT signal should
only jumper to the INB inputs. The CS4373A buffered outputs are less sensitive to the RC filter load and
DAC_BUF can be jumpered to either the INA or INB inputs.
2.2.1.4 Input Protection
Sensor inputs must have circuitry to protect the analog electronics from voltage spikes. Geophone coils
are susceptible to magnetic fields (especially from lightning) and hydrophones can produce large voltag e
spikes if located near an air gun source.
Discrete switching diodes quickly clamp the analog inputs to the power supply rails when the input voltage
spikes. These diodes are reverse biased in normal operation and have low reverse bias leakage and capacitance characteristics to maintain high linearity on the analog inputs.
Specification Value
Dual Series Switching Diode - ON Semiconductor BAV99LT1
Surface Mount Package Type SOT-23
Non-Repetitive Peak Forward Current (1 µs, 1 ms, 1 s)
Reverse Bias Leakage (25 C to 85 C)
2.0 A, 1.0 A, 500 mA
0.004 µA - 0.4 µA
Reverse Bias Capacitance (0 V to 5 V) 1.5 pF - 0.54 pF
2.2.1.5 Input RC Filters
Following the diode clamps is an RC filter network that bandwidth limits the sensor inputs into the amplifiers to “chop the tops off” residual voltage spikes not clamped by the discrete diodes. In addition , all Cirrus
Logic component ICs have built in ESD protection diodes guaranteed to 2000 V HBM / 200 V MM (JEDEC
standard). The small physical size of these ESD diodes restricts their current capacity to 10 mA.
For land applications using the CS3301A amplifier (CDB5376 channels 1 and 2), the INA input has a common mode and differential RC filter. The common mode filter sets a low-pass corner to shunt very highfrequency components to ground with minimal noise contribution. The differential filter sets a low-pass
corner high enough not to affect the magnitude response of the measurement bandwidth.
For marine applications that use the CS3302A amplifier, the inherent capa citance of the piezoelectric sensor is combined with large resistors to create an analog high-pass RC filter to eliminate the low-frequencycomponents of ocean noise.
DS612DB3 17
Land Common Mode Filter Specification Value
Common Mode Capacitance 10 nF + 10%
Common Mode Resistance
200 Ω
Common Mode -3 dB Corner @ 6 dB/octave 80 kHz + 10%
Land Differential Filter Specification Value
Differential Capacitance 10 nF + 10%
Differential Resistance
200 Ω + 200 Ω = 400 Ω
Differential -3 dB Corner @ 6 dB/octave 40 kHz + 10%
Marine Differential Filter Specification Value
Hydrophone Group Capacitance 128 nF + 10%
Differential Resistance
412 kΩ + 2 kΩ = 400 Ω
-3 dB Corner @ 6 dB/octave 40 kHz + 10%
CDB5376
2.2.1.6 Common Mode Bias
Differential analog signals into the CS3301A/02A amplifiers are required to be biased to the center of the
power supply voltage range, which for bipolar supplies is near ground potential. This common mode bias
voltage is created by buffering the voltage reference, which is nominally +2.5 V relative to the VA- power
supply.
Resistors to create the common mode bias are selected based on the sensor impedance and may need
to be modified from the CDB5376 defaults depending on the sensor to be used. Refer to the recommended operating bias conditions for the selected sensor, which are available from the sensor manufacturer.
Specification Value
Geophone Sensor Bias Resistance
Hydrophone Sensor Bias Resistance
20 kΩ || 20 kΩ = 10 kΩ
18 MΩ || 18 MΩ = 9 MΩ
18 DS612DB3
CDB5376
2.2.2 Differential Amplifiers
The CS3301A/02A amplifiers act as a low-noise gain stage for internal or e xternal differe ntial analog signals.
Analog Signals Description
INA Sensor analog input
INB Test DAC analog input
OUTR, OUTF Analog rough / fine outputs
GUARD CS3302A guard output (jumper selection)
Digital Signals Description
MUX[0..1] Input mux selection
GAIN[0..2] Gain range selection
PWDN Power down mode enable
CLK CS3301A clock input (jumper selection)
2.2.2.1 ACLK Input vs. GUARD Output
By default, channels 1 and 2 of CDB5376 use the CS3301A geophone amplifier while channels 3 and 4
use the CS3302A hydrophone amplifier. The CS3301A amplifier is chopper stabilized and connects pin
13 to a clock source (ACLK) to run the chopper circuitry synchronous to the modulator analog sampling
clock. The CS3302A device is not chopper stabilized (with 1/f noise typically buried below the low-frequency ocean noise) to achieve very high input impedance. To minimize leakage from high-impedance
sensors connected to the CS3302A amplifier, pin 13 produces a GUARD sig nal output to actively drive a
sensor cable shield with the common mode voltage of the sensor signal.
Comparing the CS3301A and CS3302A amplifiers, the functionality of pin 13 (ACLK input vs. GUARD output) is the only external difference. CDB5376 can be converted to use any combination of CS3301A and
CS3302A amplifiers by replacing the amplifier device and properly setting the pin 13 jumper (J42, J242,
J342, J442). By default these jumpers are not populated and have shorting traces between pins on the
back side of the PCB. Converting between amplifier types requires carefully
installing a jumper.
Common amplifier configurations for CDB5376 include 3x or 4x CS3301A amplifiers for land applications,
4x CS3302A amplifiers for marine streamer applications, and 3x CS3301A amplifiers plus 1x CS3302A
amplifier for seabed reservoir monitoring applications. Replacement amplifiers can be requested as samples from your local Cirrus Logic sales representative.
cutting the default short and
2.2.2.2 Rough-Fine Outputs - OUTR, OUTF
The analog outputs of the CS3301A/02A differential amplifiers are split into rough-charge and fine-charge
signals for input to the CS5372A ∆Σ modulators. The amplifier outputs include integ rated series resistors
to create the anti-alias RC filters required to limit the modulator input signal bandwidth.
Analog signal traces out of the CS3301A/02A amplifiers and into the CS5372A modulators are 4-wire
INR+ / INF+ / INF- / INR- quad groups, and are routed with INF+ and INF- as a traditional differential pair
and INR+ and INR- as guard traces outside the respective INF+ and INF- traces.
DS612DB3 19
CDB5376
2.2.2.3 Anti-alias RC Filters
The CS5372A ∆Σ modulator is 4th order and high-frequency input signals can cause instability. Simple
single-pole anti-alias RC filters are required between the CS3301A/02A amplifier outputs and the
CS5372A modulator inputs to bandwidth limit analog signals into the modulator.
The CS3301A/02A amplifier outputs are connected to external 680
anti-alias RC filter is created by connecting 20 nF of high-linearity differential capacitance (2x 10 nF C0G)
between each half of the rough and fine signals.
INR+
INF+
INFINR-
Figure 2. RC Filter External Components
Ω series resistors and a differential
INR+
INF+
INF-
INR-
2.2.3 Delta-Sigma Modulators
A single CS5372A dual modulator performs the A/D function for differential analog signals from two
CS3301A/02A amplifiers. The digital outputs are oversampled ∆Σ bit streams.
Analog Signals Description
INR1, INF1 Channel 1 analog rough / fine inputs
INR2, INF2 Channel 2 analog rough / fine inputs
VREF Voltage reference analog inputs
Digital Signals Description
MDATA[1..2] Modulator delta-sigma data outputs
MFLAG[1..2] Modulator over-range flag outputs
MCLK Modulator clock input
MSYNC Modulator synchronization input
PWDN[1..2] Power down mode enable
OFST Internal offset enable (+VD when using CS3301A/02A)
2.2.3.1 Rough-Fine Inputs - INR, INF
The modulator analog inputs are separated into rough and fine signals, each of which has an anti-alias
RC filter to limit the signal bandwidth into the modulator inputs.
20 DS612DB3
CDB5376
2.2.3.2 Offset Enable - OFST
The CS5372A ∆Σ modulator requires differential offset to be enabled to eliminate idle tones for a terminated input. The use of internal offset to eliminate idle tones is described in the CS5372A data sheet.
OFST is enabled by closing dip switch #4 (S5, #4 - HI).
2.2.4 Delta-Sigma Test DAC
The CS4373A DAC creates differential analog signals for system tests. Multiple test modes are available
and their use is described in the CS4373A data sheet.
Analog Signals Description
OUT Precision differential analog output
BUF Buffered differential analog output
CAP Capacitor connection for internal anti-alias filter
VREF Voltage reference analog inputs
Digital Signals Description
TDATA Delta-sigma test data input
MCLK Clock input
SYNC Synchronization input
MODE[0..2] Test mode selection
ATT[0..2] Attenuation range selection
2.2.4.1 Precision Output - DAC_OUT
The CS4373A test DAC has a precision output (DAC_OUT) that is routed to the input selection jumpers
for each channel. This output is sensitive to loading, and on CDB5376 should only be jumpered into the
INB inputs which do not have passive RC filter components installed. The input impedance of the
CS3301A/02A INB amplifier inputs are high enough that the precision output can be directly connected to
the INB inputs of all channels simultaneously.
2.2.4.2 Buffered Output - DAC_BUF
The CS4373A test DAC has a buffered output (DAC_BUF) that is routed to the input selection jumpers
for each channel. This output is less sensitive to loading than the precision outputs, and can be jumpered
into either the INA or INB inputs without affecting performance. The b uffered output can a lso drive a se nsor attached to the input screw terminals, provided the sensor meets the impedance requirements specified in the CS4373A data sheet.
DS612DB3 21
CDB5376
2.2.5 Voltage Reference
A voltage reference on CDB5376 creates a precision voltage from the regulated analog supplies for the
modulator and test DAC VREF inputs. Because the voltage reference output is generated relative to the
negative analog power supply, VREF+ is near GND potential for bipolar power supplies.
Specification Value
Precision Reference - Linear Tech LT1019AIS8-2.5
Surface Mount Package Type SO-8
Output Voltage Tolerance +/- 0.05%
Temperature Drift 10 ppm / degC
Quiescent Current 0.65 mA
Output Voltage Noise, 10 Hz - 1 kHz 4 ppm
Ripple Rejection, 10 Hz - 200 Hz > 100 dB
2.2.5.1 VREF_MOD12, VREF_MOD34, VREF_DAC
The voltage reference output is provided to the CS5372A ∆Σ modulators and the CS4373A test DAC
through separate low-pass RC filters. By separately filtering the voltage reference for each device, signaldependent sampling of VREF by one device is isolat ed from other devices. Each voltage reference signal
is routed as a separate differential pair from the large RC filter capacitor to control the sensitive VREF
source-return currents and keep them out of the ground plane. In addition to the RC filter function, the
100 uF filter capacitor provides a large charge well to help settle voltage reference sampling transients.
RMS
2.2.5.2 Common Mode Bias
A buffered version of the voltage reference is created as a low-impedance common mode bias source for
the analog signal inputs. The bias resistors connected between the buffered voltage reference and each
analog signal input half depends on the sensor type and should be modified to match the sensor manufacturer recommendations.
22 DS612DB3
CDB5376
2.3 Digital Hardware
2.3.1 Digital Filter
The CS5376A quad digital filter performs filtering and decimation of four delta-sigma bit streams from the
CS5372A modulators. It also creates a delta-sigma bit stream output to create analog test signals in the
CS4373A test DAC.
The CS5376A requires several control signal inputs from the external system.
Control Signals Description
RESETz Reset input, active low
BOOT Microcontroller / EEPROM boot mode select
TIMEB Time Break input, rising edge triggered
CLK Master clock input, 32.768 MHz
SYNC Master synchronization input, rising edge triggered
Configuration is completed through the SPI 1 port.
SPI1 Signals Description
SSIz Serial chip select input, active low
SCK1 Serial clock input
MISO Master in / slave out serial data
MOSI Master out / slave in serial data
SINTz Serial acknowledge output, active low
SSOz Serial chip select output (unused on CDB5376)
Data is collected through the SD port.
SD Port Signals Description
SDTKI Token input to initiate an SD port transaction
SDRDYz Data ready acknowledge, active low
SDCLK Serial clock input
SDDAT Serial data output
SDTKO Token output (unused on CDB5376)
DS612DB3 23
Modulator ∆Σ data is input through the modulator interface.
Modulator Signals Description
MCLK Modulator clock output
MCLK/2 Modulator clock output, half-speed
MSYNC Modulator synchronization output
MDATA[1..4] Modulator delta-sigma data inputs
MFLAG[1..4] Modulator over-range flag inputs
Test DAC ∆Σ data is generated by the test bit stream generator.
Test Bit Stream Signals Description
TBSDATA Test DAC delta-sigma data output
TBSCLK Test DAC clock output (unused on CDB5376)
Amplifier, modulator, and test DAC digital pins are controlled by the GPIO port.
CDB5376
GPIO Signals Description
GPIO[0..1]:MUX[0..1] Amplifier input mux selection
GPIO[2..4]:GAIN[0..2] Amplifier gain / test DAC attenuation
GPIO[5..7]:MODE[0..2] Test DAC mode selection
GPIO[8]:PWDN Amplifier / modulator power down
GPIO[9..10] Available general purpose input/output
GPIO[11]:EECS Chip select for boot EEPROM
The secondary serial port (SPI 2) and boundary scan JTAG port are unused on CDB5376.
SPI2 Signals Description
SCK2 Serial clock output (unused on CDB5376)
SO Serial data output (unused on CDB5376)
SI[1..4] Serial data inputs (unused on CDB5376)
JTAG Signals Description
TRSTz JTAG reset (unused on CDB5376)
TMS JTAG test mode select (unused on CDB5376)
TCK JTAG test clock input (unused on CDB5376)
TDI JTAG test data input (unused on CDB5376)
TDO JTAG test data output (unused on CDB5376)
24 DS612DB3
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